1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 50 #include <linux/mlx5/device.h> 51 #include <linux/mlx5/doorbell.h> 52 #include <linux/mlx5/srq.h> 53 #include <linux/timecounter.h> 54 #include <linux/ptp_clock_kernel.h> 55 56 enum { 57 MLX5_BOARD_ID_LEN = 64, 58 MLX5_MAX_NAME_LEN = 16, 59 }; 60 61 enum { 62 /* one minute for the sake of bringup. Generally, commands must always 63 * complete and we may need to increase this timeout value 64 */ 65 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 66 MLX5_CMD_WQ_MAX_NAME = 32, 67 }; 68 69 enum { 70 CMD_OWNER_SW = 0x0, 71 CMD_OWNER_HW = 0x1, 72 CMD_STATUS_SUCCESS = 0, 73 }; 74 75 enum mlx5_sqp_t { 76 MLX5_SQP_SMI = 0, 77 MLX5_SQP_GSI = 1, 78 MLX5_SQP_IEEE_1588 = 2, 79 MLX5_SQP_SNIFFER = 3, 80 MLX5_SQP_SYNC_UMR = 4, 81 }; 82 83 enum { 84 MLX5_MAX_PORTS = 2, 85 }; 86 87 enum { 88 MLX5_EQ_VEC_PAGES = 0, 89 MLX5_EQ_VEC_CMD = 1, 90 MLX5_EQ_VEC_ASYNC = 2, 91 MLX5_EQ_VEC_PFAULT = 3, 92 MLX5_EQ_VEC_COMP_BASE, 93 }; 94 95 enum { 96 MLX5_MAX_IRQ_NAME = 32 97 }; 98 99 enum { 100 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 101 MLX5_ATOMIC_MODE_CX = 2 << 16, 102 MLX5_ATOMIC_MODE_8B = 3 << 16, 103 MLX5_ATOMIC_MODE_16B = 4 << 16, 104 MLX5_ATOMIC_MODE_32B = 5 << 16, 105 MLX5_ATOMIC_MODE_64B = 6 << 16, 106 MLX5_ATOMIC_MODE_128B = 7 << 16, 107 MLX5_ATOMIC_MODE_256B = 8 << 16, 108 }; 109 110 enum { 111 MLX5_REG_QPTS = 0x4002, 112 MLX5_REG_QETCR = 0x4005, 113 MLX5_REG_QTCT = 0x400a, 114 MLX5_REG_QPDPM = 0x4013, 115 MLX5_REG_QCAM = 0x4019, 116 MLX5_REG_DCBX_PARAM = 0x4020, 117 MLX5_REG_DCBX_APP = 0x4021, 118 MLX5_REG_FPGA_CAP = 0x4022, 119 MLX5_REG_FPGA_CTRL = 0x4023, 120 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 121 MLX5_REG_PCAP = 0x5001, 122 MLX5_REG_PMTU = 0x5003, 123 MLX5_REG_PTYS = 0x5004, 124 MLX5_REG_PAOS = 0x5006, 125 MLX5_REG_PFCC = 0x5007, 126 MLX5_REG_PPCNT = 0x5008, 127 MLX5_REG_PMAOS = 0x5012, 128 MLX5_REG_PUDE = 0x5009, 129 MLX5_REG_PMPE = 0x5010, 130 MLX5_REG_PELC = 0x500e, 131 MLX5_REG_PVLC = 0x500f, 132 MLX5_REG_PCMR = 0x5041, 133 MLX5_REG_PMLP = 0x5002, 134 MLX5_REG_PCAM = 0x507f, 135 MLX5_REG_NODE_DESC = 0x6001, 136 MLX5_REG_HOST_ENDIANNESS = 0x7004, 137 MLX5_REG_MCIA = 0x9014, 138 MLX5_REG_MLCR = 0x902b, 139 MLX5_REG_MPCNT = 0x9051, 140 MLX5_REG_MTPPS = 0x9053, 141 MLX5_REG_MTPPSE = 0x9054, 142 MLX5_REG_MCQI = 0x9061, 143 MLX5_REG_MCC = 0x9062, 144 MLX5_REG_MCDA = 0x9063, 145 MLX5_REG_MCAM = 0x907f, 146 }; 147 148 enum mlx5_qpts_trust_state { 149 MLX5_QPTS_TRUST_PCP = 1, 150 MLX5_QPTS_TRUST_DSCP = 2, 151 }; 152 153 enum mlx5_dcbx_oper_mode { 154 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 155 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 156 }; 157 158 enum { 159 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 160 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 161 }; 162 163 enum mlx5_page_fault_resume_flags { 164 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 165 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 166 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 167 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 168 }; 169 170 enum dbg_rsc_type { 171 MLX5_DBG_RSC_QP, 172 MLX5_DBG_RSC_EQ, 173 MLX5_DBG_RSC_CQ, 174 }; 175 176 enum port_state_policy { 177 MLX5_POLICY_DOWN = 0, 178 MLX5_POLICY_UP = 1, 179 MLX5_POLICY_FOLLOW = 2, 180 MLX5_POLICY_INVALID = 0xffffffff 181 }; 182 183 struct mlx5_field_desc { 184 struct dentry *dent; 185 int i; 186 }; 187 188 struct mlx5_rsc_debug { 189 struct mlx5_core_dev *dev; 190 void *object; 191 enum dbg_rsc_type type; 192 struct dentry *root; 193 struct mlx5_field_desc fields[0]; 194 }; 195 196 enum mlx5_dev_event { 197 MLX5_DEV_EVENT_SYS_ERROR, 198 MLX5_DEV_EVENT_PORT_UP, 199 MLX5_DEV_EVENT_PORT_DOWN, 200 MLX5_DEV_EVENT_PORT_INITIALIZED, 201 MLX5_DEV_EVENT_LID_CHANGE, 202 MLX5_DEV_EVENT_PKEY_CHANGE, 203 MLX5_DEV_EVENT_GUID_CHANGE, 204 MLX5_DEV_EVENT_CLIENT_REREG, 205 MLX5_DEV_EVENT_PPS, 206 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 207 }; 208 209 enum mlx5_port_status { 210 MLX5_PORT_UP = 1, 211 MLX5_PORT_DOWN = 2, 212 }; 213 214 enum mlx5_eq_type { 215 MLX5_EQ_TYPE_COMP, 216 MLX5_EQ_TYPE_ASYNC, 217 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 218 MLX5_EQ_TYPE_PF, 219 #endif 220 }; 221 222 struct mlx5_bfreg_info { 223 u32 *sys_pages; 224 int num_low_latency_bfregs; 225 unsigned int *count; 226 227 /* 228 * protect bfreg allocation data structs 229 */ 230 struct mutex lock; 231 u32 ver; 232 bool lib_uar_4k; 233 u32 num_sys_pages; 234 }; 235 236 struct mlx5_cmd_first { 237 __be32 data[4]; 238 }; 239 240 struct mlx5_cmd_msg { 241 struct list_head list; 242 struct cmd_msg_cache *parent; 243 u32 len; 244 struct mlx5_cmd_first first; 245 struct mlx5_cmd_mailbox *next; 246 }; 247 248 struct mlx5_cmd_debug { 249 struct dentry *dbg_root; 250 struct dentry *dbg_in; 251 struct dentry *dbg_out; 252 struct dentry *dbg_outlen; 253 struct dentry *dbg_status; 254 struct dentry *dbg_run; 255 void *in_msg; 256 void *out_msg; 257 u8 status; 258 u16 inlen; 259 u16 outlen; 260 }; 261 262 struct cmd_msg_cache { 263 /* protect block chain allocations 264 */ 265 spinlock_t lock; 266 struct list_head head; 267 unsigned int max_inbox_size; 268 unsigned int num_ent; 269 }; 270 271 enum { 272 MLX5_NUM_COMMAND_CACHES = 5, 273 }; 274 275 struct mlx5_cmd_stats { 276 u64 sum; 277 u64 n; 278 struct dentry *root; 279 struct dentry *avg; 280 struct dentry *count; 281 /* protect command average calculations */ 282 spinlock_t lock; 283 }; 284 285 struct mlx5_cmd { 286 void *cmd_alloc_buf; 287 dma_addr_t alloc_dma; 288 int alloc_size; 289 void *cmd_buf; 290 dma_addr_t dma; 291 u16 cmdif_rev; 292 u8 log_sz; 293 u8 log_stride; 294 int max_reg_cmds; 295 int events; 296 u32 __iomem *vector; 297 298 /* protect command queue allocations 299 */ 300 spinlock_t alloc_lock; 301 302 /* protect token allocations 303 */ 304 spinlock_t token_lock; 305 u8 token; 306 unsigned long bitmask; 307 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 308 struct workqueue_struct *wq; 309 struct semaphore sem; 310 struct semaphore pages_sem; 311 int mode; 312 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 313 struct dma_pool *pool; 314 struct mlx5_cmd_debug dbg; 315 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 316 int checksum_disabled; 317 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 318 }; 319 320 struct mlx5_port_caps { 321 int gid_table_len; 322 int pkey_table_len; 323 u8 ext_port_cap; 324 bool has_smi; 325 }; 326 327 struct mlx5_cmd_mailbox { 328 void *buf; 329 dma_addr_t dma; 330 struct mlx5_cmd_mailbox *next; 331 }; 332 333 struct mlx5_buf_list { 334 void *buf; 335 dma_addr_t map; 336 }; 337 338 struct mlx5_buf { 339 struct mlx5_buf_list direct; 340 int npages; 341 int size; 342 u8 page_shift; 343 }; 344 345 struct mlx5_frag_buf { 346 struct mlx5_buf_list *frags; 347 int npages; 348 int size; 349 u8 page_shift; 350 }; 351 352 struct mlx5_eq_tasklet { 353 struct list_head list; 354 struct list_head process_list; 355 struct tasklet_struct task; 356 /* lock on completion tasklet list */ 357 spinlock_t lock; 358 }; 359 360 struct mlx5_eq_pagefault { 361 struct work_struct work; 362 /* Pagefaults lock */ 363 spinlock_t lock; 364 struct workqueue_struct *wq; 365 mempool_t *pool; 366 }; 367 368 struct mlx5_eq { 369 struct mlx5_core_dev *dev; 370 __be32 __iomem *doorbell; 371 u32 cons_index; 372 struct mlx5_buf buf; 373 int size; 374 unsigned int irqn; 375 u8 eqn; 376 int nent; 377 u64 mask; 378 struct list_head list; 379 int index; 380 struct mlx5_rsc_debug *dbg; 381 enum mlx5_eq_type type; 382 union { 383 struct mlx5_eq_tasklet tasklet_ctx; 384 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 385 struct mlx5_eq_pagefault pf_ctx; 386 #endif 387 }; 388 }; 389 390 struct mlx5_core_psv { 391 u32 psv_idx; 392 struct psv_layout { 393 u32 pd; 394 u16 syndrome; 395 u16 reserved; 396 u16 bg; 397 u16 app_tag; 398 u32 ref_tag; 399 } psv; 400 }; 401 402 struct mlx5_core_sig_ctx { 403 struct mlx5_core_psv psv_memory; 404 struct mlx5_core_psv psv_wire; 405 struct ib_sig_err err_item; 406 bool sig_status_checked; 407 bool sig_err_exists; 408 u32 sigerr_count; 409 }; 410 411 enum { 412 MLX5_MKEY_MR = 1, 413 MLX5_MKEY_MW, 414 }; 415 416 struct mlx5_core_mkey { 417 u64 iova; 418 u64 size; 419 u32 key; 420 u32 pd; 421 u32 type; 422 }; 423 424 #define MLX5_24BIT_MASK ((1 << 24) - 1) 425 426 enum mlx5_res_type { 427 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 428 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 429 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 430 MLX5_RES_SRQ = 3, 431 MLX5_RES_XSRQ = 4, 432 MLX5_RES_XRQ = 5, 433 }; 434 435 struct mlx5_core_rsc_common { 436 enum mlx5_res_type res; 437 atomic_t refcount; 438 struct completion free; 439 }; 440 441 struct mlx5_core_srq { 442 struct mlx5_core_rsc_common common; /* must be first */ 443 u32 srqn; 444 int max; 445 int max_gs; 446 int max_avail_gather; 447 int wqe_shift; 448 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 449 450 atomic_t refcount; 451 struct completion free; 452 }; 453 454 struct mlx5_eq_table { 455 void __iomem *update_ci; 456 void __iomem *update_arm_ci; 457 struct list_head comp_eqs_list; 458 struct mlx5_eq pages_eq; 459 struct mlx5_eq async_eq; 460 struct mlx5_eq cmd_eq; 461 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 462 struct mlx5_eq pfault_eq; 463 #endif 464 int num_comp_vectors; 465 /* protect EQs list 466 */ 467 spinlock_t lock; 468 }; 469 470 struct mlx5_uars_page { 471 void __iomem *map; 472 bool wc; 473 u32 index; 474 struct list_head list; 475 unsigned int bfregs; 476 unsigned long *reg_bitmap; /* for non fast path bf regs */ 477 unsigned long *fp_bitmap; 478 unsigned int reg_avail; 479 unsigned int fp_avail; 480 struct kref ref_count; 481 struct mlx5_core_dev *mdev; 482 }; 483 484 struct mlx5_bfreg_head { 485 /* protect blue flame registers allocations */ 486 struct mutex lock; 487 struct list_head list; 488 }; 489 490 struct mlx5_bfreg_data { 491 struct mlx5_bfreg_head reg_head; 492 struct mlx5_bfreg_head wc_head; 493 }; 494 495 struct mlx5_sq_bfreg { 496 void __iomem *map; 497 struct mlx5_uars_page *up; 498 bool wc; 499 u32 index; 500 unsigned int offset; 501 }; 502 503 struct mlx5_core_health { 504 struct health_buffer __iomem *health; 505 __be32 __iomem *health_counter; 506 struct timer_list timer; 507 u32 prev; 508 int miss_counter; 509 bool sick; 510 /* wq spinlock to synchronize draining */ 511 spinlock_t wq_lock; 512 struct workqueue_struct *wq; 513 unsigned long flags; 514 struct work_struct work; 515 struct delayed_work recover_work; 516 }; 517 518 struct mlx5_cq_table { 519 /* protect radix tree 520 */ 521 spinlock_t lock; 522 struct radix_tree_root tree; 523 }; 524 525 struct mlx5_qp_table { 526 /* protect radix tree 527 */ 528 spinlock_t lock; 529 struct radix_tree_root tree; 530 }; 531 532 struct mlx5_srq_table { 533 /* protect radix tree 534 */ 535 spinlock_t lock; 536 struct radix_tree_root tree; 537 }; 538 539 struct mlx5_mkey_table { 540 /* protect radix tree 541 */ 542 rwlock_t lock; 543 struct radix_tree_root tree; 544 }; 545 546 struct mlx5_vf_context { 547 int enabled; 548 u64 port_guid; 549 u64 node_guid; 550 enum port_state_policy policy; 551 }; 552 553 struct mlx5_core_sriov { 554 struct mlx5_vf_context *vfs_ctx; 555 int num_vfs; 556 int enabled_vfs; 557 }; 558 559 struct mlx5_irq_info { 560 cpumask_var_t mask; 561 char name[MLX5_MAX_IRQ_NAME]; 562 }; 563 564 struct mlx5_fc_stats { 565 struct rb_root counters; 566 struct list_head addlist; 567 /* protect addlist add/splice operations */ 568 spinlock_t addlist_lock; 569 570 struct workqueue_struct *wq; 571 struct delayed_work work; 572 unsigned long next_query; 573 unsigned long sampling_interval; /* jiffies */ 574 }; 575 576 struct mlx5_mpfs; 577 struct mlx5_eswitch; 578 struct mlx5_lag; 579 struct mlx5_pagefault; 580 581 struct mlx5_rl_entry { 582 u32 rate; 583 u16 index; 584 u16 refcount; 585 }; 586 587 struct mlx5_rl_table { 588 /* protect rate limit table */ 589 struct mutex rl_lock; 590 u16 max_size; 591 u32 max_rate; 592 u32 min_rate; 593 struct mlx5_rl_entry *rl_entry; 594 }; 595 596 enum port_module_event_status_type { 597 MLX5_MODULE_STATUS_PLUGGED = 0x1, 598 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 599 MLX5_MODULE_STATUS_ERROR = 0x3, 600 MLX5_MODULE_STATUS_NUM = 0x3, 601 }; 602 603 enum port_module_event_error_type { 604 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, 605 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, 606 MLX5_MODULE_EVENT_ERROR_BUS_STUCK, 607 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, 608 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, 609 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, 610 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, 611 MLX5_MODULE_EVENT_ERROR_BAD_CABLE, 612 MLX5_MODULE_EVENT_ERROR_UNKNOWN, 613 MLX5_MODULE_EVENT_ERROR_NUM, 614 }; 615 616 struct mlx5_port_module_event_stats { 617 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 618 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 619 }; 620 621 struct mlx5_priv { 622 char name[MLX5_MAX_NAME_LEN]; 623 struct mlx5_eq_table eq_table; 624 struct mlx5_irq_info *irq_info; 625 626 /* pages stuff */ 627 struct workqueue_struct *pg_wq; 628 struct rb_root page_root; 629 int fw_pages; 630 atomic_t reg_pages; 631 struct list_head free_list; 632 int vfs_pages; 633 634 struct mlx5_core_health health; 635 636 struct mlx5_srq_table srq_table; 637 638 /* start: qp staff */ 639 struct mlx5_qp_table qp_table; 640 struct dentry *qp_debugfs; 641 struct dentry *eq_debugfs; 642 struct dentry *cq_debugfs; 643 struct dentry *cmdif_debugfs; 644 /* end: qp staff */ 645 646 /* start: cq staff */ 647 struct mlx5_cq_table cq_table; 648 /* end: cq staff */ 649 650 /* start: mkey staff */ 651 struct mlx5_mkey_table mkey_table; 652 /* end: mkey staff */ 653 654 /* start: alloc staff */ 655 /* protect buffer alocation according to numa node */ 656 struct mutex alloc_mutex; 657 int numa_node; 658 659 struct mutex pgdir_mutex; 660 struct list_head pgdir_list; 661 /* end: alloc staff */ 662 struct dentry *dbg_root; 663 664 /* protect mkey key part */ 665 spinlock_t mkey_lock; 666 u8 mkey_key; 667 668 struct list_head dev_list; 669 struct list_head ctx_list; 670 spinlock_t ctx_lock; 671 672 struct list_head waiting_events_list; 673 bool is_accum_events; 674 675 struct mlx5_flow_steering *steering; 676 struct mlx5_mpfs *mpfs; 677 struct mlx5_eswitch *eswitch; 678 struct mlx5_core_sriov sriov; 679 struct mlx5_lag *lag; 680 unsigned long pci_dev_data; 681 struct mlx5_fc_stats fc_stats; 682 struct mlx5_rl_table rl_table; 683 684 struct mlx5_port_module_event_stats pme_stats; 685 686 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 687 void (*pfault)(struct mlx5_core_dev *dev, 688 void *context, 689 struct mlx5_pagefault *pfault); 690 void *pfault_ctx; 691 struct srcu_struct pfault_srcu; 692 #endif 693 struct mlx5_bfreg_data bfregs; 694 struct mlx5_uars_page *uar; 695 }; 696 697 enum mlx5_device_state { 698 MLX5_DEVICE_STATE_UP, 699 MLX5_DEVICE_STATE_INTERNAL_ERROR, 700 }; 701 702 enum mlx5_interface_state { 703 MLX5_INTERFACE_STATE_UP = BIT(0), 704 }; 705 706 enum mlx5_pci_status { 707 MLX5_PCI_STATUS_DISABLED, 708 MLX5_PCI_STATUS_ENABLED, 709 }; 710 711 enum mlx5_pagefault_type_flags { 712 MLX5_PFAULT_REQUESTOR = 1 << 0, 713 MLX5_PFAULT_WRITE = 1 << 1, 714 MLX5_PFAULT_RDMA = 1 << 2, 715 }; 716 717 /* Contains the details of a pagefault. */ 718 struct mlx5_pagefault { 719 u32 bytes_committed; 720 u32 token; 721 u8 event_subtype; 722 u8 type; 723 union { 724 /* Initiator or send message responder pagefault details. */ 725 struct { 726 /* Received packet size, only valid for responders. */ 727 u32 packet_size; 728 /* 729 * Number of resource holding WQE, depends on type. 730 */ 731 u32 wq_num; 732 /* 733 * WQE index. Refers to either the send queue or 734 * receive queue, according to event_subtype. 735 */ 736 u16 wqe_index; 737 } wqe; 738 /* RDMA responder pagefault details */ 739 struct { 740 u32 r_key; 741 /* 742 * Received packet size, minimal size page fault 743 * resolution required for forward progress. 744 */ 745 u32 packet_size; 746 u32 rdma_op_len; 747 u64 rdma_va; 748 } rdma; 749 }; 750 751 struct mlx5_eq *eq; 752 struct work_struct work; 753 }; 754 755 struct mlx5_td { 756 struct list_head tirs_list; 757 u32 tdn; 758 }; 759 760 struct mlx5e_resources { 761 u32 pdn; 762 struct mlx5_td td; 763 struct mlx5_core_mkey mkey; 764 struct mlx5_sq_bfreg bfreg; 765 }; 766 767 #define MLX5_MAX_RESERVED_GIDS 8 768 769 struct mlx5_rsvd_gids { 770 unsigned int start; 771 unsigned int count; 772 struct ida ida; 773 }; 774 775 #define MAX_PIN_NUM 8 776 struct mlx5_pps { 777 u8 pin_caps[MAX_PIN_NUM]; 778 struct work_struct out_work; 779 u64 start[MAX_PIN_NUM]; 780 u8 enabled; 781 }; 782 783 struct mlx5_clock { 784 rwlock_t lock; 785 struct cyclecounter cycles; 786 struct timecounter tc; 787 struct hwtstamp_config hwtstamp_config; 788 u32 nominal_c_mult; 789 unsigned long overflow_period; 790 struct delayed_work overflow_work; 791 struct ptp_clock *ptp; 792 struct ptp_clock_info ptp_info; 793 struct mlx5_pps pps_info; 794 }; 795 796 struct mlx5_core_dev { 797 struct pci_dev *pdev; 798 /* sync pci state */ 799 struct mutex pci_status_mutex; 800 enum mlx5_pci_status pci_status; 801 u8 rev_id; 802 char board_id[MLX5_BOARD_ID_LEN]; 803 struct mlx5_cmd cmd; 804 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 805 struct { 806 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 807 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 808 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 809 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 810 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 811 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 812 } caps; 813 phys_addr_t iseg_base; 814 struct mlx5_init_seg __iomem *iseg; 815 enum mlx5_device_state state; 816 /* sync interface state */ 817 struct mutex intf_state_mutex; 818 unsigned long intf_state; 819 void (*event) (struct mlx5_core_dev *dev, 820 enum mlx5_dev_event event, 821 unsigned long param); 822 struct mlx5_priv priv; 823 struct mlx5_profile *profile; 824 atomic_t num_qps; 825 u32 issi; 826 struct mlx5e_resources mlx5e_res; 827 struct { 828 struct mlx5_rsvd_gids reserved_gids; 829 atomic_t roce_en; 830 } roce; 831 #ifdef CONFIG_MLX5_FPGA 832 struct mlx5_fpga_device *fpga; 833 #endif 834 #ifdef CONFIG_RFS_ACCEL 835 struct cpu_rmap *rmap; 836 #endif 837 struct mlx5_clock clock; 838 }; 839 840 struct mlx5_db { 841 __be32 *db; 842 union { 843 struct mlx5_db_pgdir *pgdir; 844 struct mlx5_ib_user_db_page *user_page; 845 } u; 846 dma_addr_t dma; 847 int index; 848 }; 849 850 enum { 851 MLX5_COMP_EQ_SIZE = 1024, 852 }; 853 854 enum { 855 MLX5_PTYS_IB = 1 << 0, 856 MLX5_PTYS_EN = 1 << 2, 857 }; 858 859 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 860 861 enum { 862 MLX5_CMD_ENT_STATE_PENDING_COMP, 863 }; 864 865 struct mlx5_cmd_work_ent { 866 unsigned long state; 867 struct mlx5_cmd_msg *in; 868 struct mlx5_cmd_msg *out; 869 void *uout; 870 int uout_size; 871 mlx5_cmd_cbk_t callback; 872 struct delayed_work cb_timeout_work; 873 void *context; 874 int idx; 875 struct completion done; 876 struct mlx5_cmd *cmd; 877 struct work_struct work; 878 struct mlx5_cmd_layout *lay; 879 int ret; 880 int page_queue; 881 u8 status; 882 u8 token; 883 u64 ts1; 884 u64 ts2; 885 u16 op; 886 bool polling; 887 }; 888 889 struct mlx5_pas { 890 u64 pa; 891 u8 log_sz; 892 }; 893 894 enum phy_port_state { 895 MLX5_AAA_111 896 }; 897 898 struct mlx5_hca_vport_context { 899 u32 field_select; 900 bool sm_virt_aware; 901 bool has_smi; 902 bool has_raw; 903 enum port_state_policy policy; 904 enum phy_port_state phys_state; 905 enum ib_port_state vport_state; 906 u8 port_physical_state; 907 u64 sys_image_guid; 908 u64 port_guid; 909 u64 node_guid; 910 u32 cap_mask1; 911 u32 cap_mask1_perm; 912 u32 cap_mask2; 913 u32 cap_mask2_perm; 914 u16 lid; 915 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 916 u8 lmc; 917 u8 subnet_timeout; 918 u16 sm_lid; 919 u8 sm_sl; 920 u16 qkey_violation_counter; 921 u16 pkey_violation_counter; 922 bool grh_required; 923 }; 924 925 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 926 { 927 return buf->direct.buf + offset; 928 } 929 930 #define STRUCT_FIELD(header, field) \ 931 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 932 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 933 934 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 935 { 936 return pci_get_drvdata(pdev); 937 } 938 939 extern struct dentry *mlx5_debugfs_root; 940 941 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 942 { 943 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 944 } 945 946 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 947 { 948 return ioread32be(&dev->iseg->fw_rev) >> 16; 949 } 950 951 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 952 { 953 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 954 } 955 956 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 957 { 958 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 959 } 960 961 static inline u32 mlx5_base_mkey(const u32 key) 962 { 963 return key & 0xffffff00u; 964 } 965 966 int mlx5_cmd_init(struct mlx5_core_dev *dev); 967 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 968 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 969 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 970 971 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 972 int out_size); 973 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 974 void *out, int out_size, mlx5_cmd_cbk_t callback, 975 void *context); 976 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 977 void *out, int out_size); 978 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 979 980 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 981 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 982 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 983 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 984 int mlx5_health_init(struct mlx5_core_dev *dev); 985 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 986 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 987 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 988 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 989 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 990 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 991 struct mlx5_buf *buf, int node); 992 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); 993 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 994 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 995 struct mlx5_frag_buf *buf, int node); 996 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 997 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 998 gfp_t flags, int npages); 999 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 1000 struct mlx5_cmd_mailbox *head); 1001 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1002 struct mlx5_srq_attr *in); 1003 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 1004 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1005 struct mlx5_srq_attr *out); 1006 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1007 u16 lwm, int is_srq); 1008 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 1009 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 1010 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 1011 struct mlx5_core_mkey *mkey, 1012 u32 *in, int inlen, 1013 u32 *out, int outlen, 1014 mlx5_cmd_cbk_t callback, void *context); 1015 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 1016 struct mlx5_core_mkey *mkey, 1017 u32 *in, int inlen); 1018 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 1019 struct mlx5_core_mkey *mkey); 1020 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 1021 u32 *out, int outlen); 1022 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, 1023 u32 *mkey); 1024 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 1025 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 1026 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 1027 u16 opmod, u8 port); 1028 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 1029 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 1030 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 1031 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 1032 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 1033 s32 npages); 1034 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 1035 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 1036 void mlx5_register_debugfs(void); 1037 void mlx5_unregister_debugfs(void); 1038 int mlx5_eq_init(struct mlx5_core_dev *dev); 1039 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 1040 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 1041 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 1042 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 1043 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1044 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1045 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1046 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); 1047 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 1048 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 1049 int nent, u64 mask, const char *name, 1050 enum mlx5_eq_type type); 1051 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1052 int mlx5_start_eqs(struct mlx5_core_dev *dev); 1053 void mlx5_stop_eqs(struct mlx5_core_dev *dev); 1054 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 1055 unsigned int *irqn); 1056 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1057 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1058 1059 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1060 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1061 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1062 int size_in, void *data_out, int size_out, 1063 u16 reg_num, int arg, int write); 1064 1065 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1066 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1067 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1068 u32 *out, int outlen); 1069 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1070 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1071 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1072 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1073 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1074 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1075 int node); 1076 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1077 1078 const char *mlx5_command_str(int command); 1079 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1080 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1081 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1082 int npsvs, u32 *sig_index); 1083 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1084 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1085 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 1086 struct mlx5_odp_caps *odp_caps); 1087 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 1088 u8 port_num, void *out, size_t sz); 1089 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1090 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, 1091 u32 wq_num, u8 type, int error); 1092 #endif 1093 1094 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1095 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1096 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); 1097 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); 1098 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 1099 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 1100 bool map_wc, bool fast_path); 1101 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 1102 1103 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1104 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1105 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1106 const u8 *mac, bool vlan, u16 vlan_id); 1107 1108 static inline int fw_initializing(struct mlx5_core_dev *dev) 1109 { 1110 return ioread32be(&dev->iseg->initializing) >> 31; 1111 } 1112 1113 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1114 { 1115 return mkey >> 8; 1116 } 1117 1118 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1119 { 1120 return mkey_idx << 8; 1121 } 1122 1123 static inline u8 mlx5_mkey_variant(u32 mkey) 1124 { 1125 return mkey & 0xff; 1126 } 1127 1128 enum { 1129 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1130 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1131 }; 1132 1133 enum { 1134 MR_CACHE_LAST_STD_ENTRY = 20, 1135 MLX5_IMR_MTT_CACHE_ENTRY, 1136 MLX5_IMR_KSM_CACHE_ENTRY, 1137 MAX_MR_CACHE_ENTRIES 1138 }; 1139 1140 enum { 1141 MLX5_INTERFACE_PROTOCOL_IB = 0, 1142 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1143 }; 1144 1145 struct mlx5_interface { 1146 void * (*add)(struct mlx5_core_dev *dev); 1147 void (*remove)(struct mlx5_core_dev *dev, void *context); 1148 int (*attach)(struct mlx5_core_dev *dev, void *context); 1149 void (*detach)(struct mlx5_core_dev *dev, void *context); 1150 void (*event)(struct mlx5_core_dev *dev, void *context, 1151 enum mlx5_dev_event event, unsigned long param); 1152 void (*pfault)(struct mlx5_core_dev *dev, 1153 void *context, 1154 struct mlx5_pagefault *pfault); 1155 void * (*get_dev)(void *context); 1156 int protocol; 1157 struct list_head list; 1158 }; 1159 1160 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1161 int mlx5_register_interface(struct mlx5_interface *intf); 1162 void mlx5_unregister_interface(struct mlx5_interface *intf); 1163 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1164 1165 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1166 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1167 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1168 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1169 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1170 u64 *values, 1171 int num_counters, 1172 size_t *offsets); 1173 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1174 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1175 1176 #ifndef CONFIG_MLX5_CORE_IPOIB 1177 static inline 1178 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1179 struct ib_device *ibdev, 1180 const char *name, 1181 void (*setup)(struct net_device *)) 1182 { 1183 return ERR_PTR(-EOPNOTSUPP); 1184 } 1185 1186 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {} 1187 #else 1188 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1189 struct ib_device *ibdev, 1190 const char *name, 1191 void (*setup)(struct net_device *)); 1192 void mlx5_rdma_netdev_free(struct net_device *netdev); 1193 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1194 1195 struct mlx5_profile { 1196 u64 mask; 1197 u8 log_max_qp; 1198 struct { 1199 int size; 1200 int limit; 1201 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1202 }; 1203 1204 enum { 1205 MLX5_PCI_DEV_IS_VF = 1 << 0, 1206 }; 1207 1208 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1209 { 1210 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1211 } 1212 1213 static inline int mlx5_get_gid_table_len(u16 param) 1214 { 1215 if (param > 4) { 1216 pr_warn("gid table length is zero\n"); 1217 return 0; 1218 } 1219 1220 return 8 * (1 << param); 1221 } 1222 1223 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1224 { 1225 return !!(dev->priv.rl_table.max_size); 1226 } 1227 1228 enum { 1229 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1230 }; 1231 1232 static inline const struct cpumask * 1233 mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector) 1234 { 1235 const struct cpumask *mask; 1236 struct irq_desc *desc; 1237 unsigned int irq; 1238 int eqn; 1239 int err; 1240 1241 err = mlx5_vector2eqn(dev, vector, &eqn, &irq); 1242 if (err) 1243 return NULL; 1244 1245 desc = irq_to_desc(irq); 1246 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 1247 mask = irq_data_get_effective_affinity_mask(&desc->irq_data); 1248 #else 1249 mask = desc->irq_common_data.affinity; 1250 #endif 1251 return mask; 1252 } 1253 1254 #endif /* MLX5_DRIVER_H */ 1255