xref: /linux-6.15/include/linux/mlx5/driver.h (revision a7f0636d) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53 
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <linux/ptp_clock_kernel.h>
59 #include <net/devlink.h>
60 
61 #define MLX5_ADEV_NAME "mlx5_core"
62 
63 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
64 
65 enum {
66 	MLX5_BOARD_ID_LEN = 64,
67 };
68 
69 enum {
70 	MLX5_CMD_WQ_MAX_NAME	= 32,
71 };
72 
73 enum {
74 	CMD_OWNER_SW		= 0x0,
75 	CMD_OWNER_HW		= 0x1,
76 	CMD_STATUS_SUCCESS	= 0,
77 };
78 
79 enum mlx5_sqp_t {
80 	MLX5_SQP_SMI		= 0,
81 	MLX5_SQP_GSI		= 1,
82 	MLX5_SQP_IEEE_1588	= 2,
83 	MLX5_SQP_SNIFFER	= 3,
84 	MLX5_SQP_SYNC_UMR	= 4,
85 };
86 
87 enum {
88 	MLX5_MAX_PORTS	= 4,
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFFSET = 16,
93 	MLX5_ATOMIC_MODE_IB_COMP = 1,
94 	MLX5_ATOMIC_MODE_CX = 2,
95 	MLX5_ATOMIC_MODE_8B = 3,
96 	MLX5_ATOMIC_MODE_16B = 4,
97 	MLX5_ATOMIC_MODE_32B = 5,
98 	MLX5_ATOMIC_MODE_64B = 6,
99 	MLX5_ATOMIC_MODE_128B = 7,
100 	MLX5_ATOMIC_MODE_256B = 8,
101 };
102 
103 enum {
104 	MLX5_REG_SBPR            = 0xb001,
105 	MLX5_REG_SBCM            = 0xb002,
106 	MLX5_REG_QPTS            = 0x4002,
107 	MLX5_REG_QETCR		 = 0x4005,
108 	MLX5_REG_QTCT		 = 0x400a,
109 	MLX5_REG_QPDPM           = 0x4013,
110 	MLX5_REG_QCAM            = 0x4019,
111 	MLX5_REG_DCBX_PARAM      = 0x4020,
112 	MLX5_REG_DCBX_APP        = 0x4021,
113 	MLX5_REG_FPGA_CAP	 = 0x4022,
114 	MLX5_REG_FPGA_CTRL	 = 0x4023,
115 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
116 	MLX5_REG_CORE_DUMP	 = 0x402e,
117 	MLX5_REG_PCAP		 = 0x5001,
118 	MLX5_REG_PMTU		 = 0x5003,
119 	MLX5_REG_PTYS		 = 0x5004,
120 	MLX5_REG_PAOS		 = 0x5006,
121 	MLX5_REG_PFCC            = 0x5007,
122 	MLX5_REG_PPCNT		 = 0x5008,
123 	MLX5_REG_PPTB            = 0x500b,
124 	MLX5_REG_PBMC            = 0x500c,
125 	MLX5_REG_PMAOS		 = 0x5012,
126 	MLX5_REG_PUDE		 = 0x5009,
127 	MLX5_REG_PMPE		 = 0x5010,
128 	MLX5_REG_PELC		 = 0x500e,
129 	MLX5_REG_PVLC		 = 0x500f,
130 	MLX5_REG_PCMR		 = 0x5041,
131 	MLX5_REG_PDDR		 = 0x5031,
132 	MLX5_REG_PMLP		 = 0x5002,
133 	MLX5_REG_PPLM		 = 0x5023,
134 	MLX5_REG_PCAM		 = 0x507f,
135 	MLX5_REG_NODE_DESC	 = 0x6001,
136 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 	MLX5_REG_MTCAP		 = 0x9009,
138 	MLX5_REG_MTMP		 = 0x900A,
139 	MLX5_REG_MCIA		 = 0x9014,
140 	MLX5_REG_MFRL		 = 0x9028,
141 	MLX5_REG_MLCR		 = 0x902b,
142 	MLX5_REG_MRTC		 = 0x902d,
143 	MLX5_REG_MTRC_CAP	 = 0x9040,
144 	MLX5_REG_MTRC_CONF	 = 0x9041,
145 	MLX5_REG_MTRC_STDB	 = 0x9042,
146 	MLX5_REG_MTRC_CTRL	 = 0x9043,
147 	MLX5_REG_MPEIN		 = 0x9050,
148 	MLX5_REG_MPCNT		 = 0x9051,
149 	MLX5_REG_MTPPS		 = 0x9053,
150 	MLX5_REG_MTPPSE		 = 0x9054,
151 	MLX5_REG_MTUTC		 = 0x9055,
152 	MLX5_REG_MPEGC		 = 0x9056,
153 	MLX5_REG_MCQS		 = 0x9060,
154 	MLX5_REG_MCQI		 = 0x9061,
155 	MLX5_REG_MCC		 = 0x9062,
156 	MLX5_REG_MCDA		 = 0x9063,
157 	MLX5_REG_MCAM		 = 0x907f,
158 	MLX5_REG_MSECQ		 = 0x9155,
159 	MLX5_REG_MSEES		 = 0x9156,
160 	MLX5_REG_MIRC		 = 0x9162,
161 	MLX5_REG_SBCAM		 = 0xB01F,
162 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
163 	MLX5_REG_DTOR            = 0xC00E,
164 };
165 
166 enum mlx5_qpts_trust_state {
167 	MLX5_QPTS_TRUST_PCP  = 1,
168 	MLX5_QPTS_TRUST_DSCP = 2,
169 };
170 
171 enum mlx5_dcbx_oper_mode {
172 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
173 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
174 };
175 
176 enum {
177 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
178 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
179 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
180 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
181 };
182 
183 enum mlx5_page_fault_resume_flags {
184 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
185 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
186 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
187 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
188 };
189 
190 enum dbg_rsc_type {
191 	MLX5_DBG_RSC_QP,
192 	MLX5_DBG_RSC_EQ,
193 	MLX5_DBG_RSC_CQ,
194 };
195 
196 enum port_state_policy {
197 	MLX5_POLICY_DOWN	= 0,
198 	MLX5_POLICY_UP		= 1,
199 	MLX5_POLICY_FOLLOW	= 2,
200 	MLX5_POLICY_INVALID	= 0xffffffff
201 };
202 
203 enum mlx5_coredev_type {
204 	MLX5_COREDEV_PF,
205 	MLX5_COREDEV_VF,
206 	MLX5_COREDEV_SF,
207 };
208 
209 struct mlx5_field_desc {
210 	int			i;
211 };
212 
213 struct mlx5_rsc_debug {
214 	struct mlx5_core_dev   *dev;
215 	void		       *object;
216 	enum dbg_rsc_type	type;
217 	struct dentry	       *root;
218 	struct mlx5_field_desc	fields[];
219 };
220 
221 enum mlx5_dev_event {
222 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
223 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
224 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
225 };
226 
227 enum mlx5_port_status {
228 	MLX5_PORT_UP        = 1,
229 	MLX5_PORT_DOWN      = 2,
230 };
231 
232 enum mlx5_cmdif_state {
233 	MLX5_CMDIF_STATE_UNINITIALIZED,
234 	MLX5_CMDIF_STATE_UP,
235 	MLX5_CMDIF_STATE_DOWN,
236 };
237 
238 struct mlx5_cmd_first {
239 	__be32		data[4];
240 };
241 
242 struct mlx5_cmd_msg {
243 	struct list_head		list;
244 	struct cmd_msg_cache	       *parent;
245 	u32				len;
246 	struct mlx5_cmd_first		first;
247 	struct mlx5_cmd_mailbox	       *next;
248 };
249 
250 struct mlx5_cmd_debug {
251 	struct dentry	       *dbg_root;
252 	void		       *in_msg;
253 	void		       *out_msg;
254 	u8			status;
255 	u16			inlen;
256 	u16			outlen;
257 };
258 
259 struct cmd_msg_cache {
260 	/* protect block chain allocations
261 	 */
262 	spinlock_t		lock;
263 	struct list_head	head;
264 	unsigned int		max_inbox_size;
265 	unsigned int		num_ent;
266 };
267 
268 enum {
269 	MLX5_NUM_COMMAND_CACHES = 5,
270 };
271 
272 struct mlx5_cmd_stats {
273 	u64		sum;
274 	u64		n;
275 	/* number of times command failed */
276 	u64		failed;
277 	/* number of times command failed on bad status returned by FW */
278 	u64		failed_mbox_status;
279 	/* last command failed returned errno */
280 	u32		last_failed_errno;
281 	/* last bad status returned by FW */
282 	u8		last_failed_mbox_status;
283 	/* last command failed syndrome returned by FW */
284 	u32		last_failed_syndrome;
285 	struct dentry  *root;
286 	/* protect command average calculations */
287 	spinlock_t	lock;
288 };
289 
290 struct mlx5_cmd {
291 	struct mlx5_nb    nb;
292 
293 	/* members which needs to be queried or reinitialized each reload */
294 	struct {
295 		u16		cmdif_rev;
296 		u8		log_sz;
297 		u8		log_stride;
298 		int		max_reg_cmds;
299 		unsigned long	bitmask;
300 		struct semaphore sem;
301 		struct semaphore pages_sem;
302 		struct semaphore throttle_sem;
303 	} vars;
304 	enum mlx5_cmdif_state	state;
305 	void	       *cmd_alloc_buf;
306 	dma_addr_t	alloc_dma;
307 	int		alloc_size;
308 	void	       *cmd_buf;
309 	dma_addr_t	dma;
310 
311 	/* protect command queue allocations
312 	 */
313 	spinlock_t	alloc_lock;
314 
315 	/* protect token allocations
316 	 */
317 	spinlock_t	token_lock;
318 	u8		token;
319 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
320 	struct workqueue_struct *wq;
321 	int	mode;
322 	u16     allowed_opcode;
323 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
324 	struct dma_pool *pool;
325 	struct mlx5_cmd_debug dbg;
326 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
327 	int checksum_disabled;
328 	struct xarray stats;
329 };
330 
331 struct mlx5_cmd_mailbox {
332 	void	       *buf;
333 	dma_addr_t	dma;
334 	struct mlx5_cmd_mailbox *next;
335 };
336 
337 struct mlx5_buf_list {
338 	void		       *buf;
339 	dma_addr_t		map;
340 };
341 
342 struct mlx5_frag_buf {
343 	struct mlx5_buf_list	*frags;
344 	int			npages;
345 	int			size;
346 	u8			page_shift;
347 };
348 
349 struct mlx5_frag_buf_ctrl {
350 	struct mlx5_buf_list   *frags;
351 	u32			sz_m1;
352 	u16			frag_sz_m1;
353 	u16			strides_offset;
354 	u8			log_sz;
355 	u8			log_stride;
356 	u8			log_frag_strides;
357 };
358 
359 struct mlx5_core_psv {
360 	u32	psv_idx;
361 	struct psv_layout {
362 		u32	pd;
363 		u16	syndrome;
364 		u16	reserved;
365 		u16	bg;
366 		u16	app_tag;
367 		u32	ref_tag;
368 	} psv;
369 };
370 
371 struct mlx5_core_sig_ctx {
372 	struct mlx5_core_psv	psv_memory;
373 	struct mlx5_core_psv	psv_wire;
374 	struct ib_sig_err       err_item;
375 	bool			sig_status_checked;
376 	bool			sig_err_exists;
377 	u32			sigerr_count;
378 };
379 
380 #define MLX5_24BIT_MASK		((1 << 24) - 1)
381 
382 enum mlx5_res_type {
383 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
384 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
385 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
386 	MLX5_RES_SRQ	= 3,
387 	MLX5_RES_XSRQ	= 4,
388 	MLX5_RES_XRQ	= 5,
389 };
390 
391 struct mlx5_core_rsc_common {
392 	enum mlx5_res_type	res;
393 	refcount_t		refcount;
394 	struct completion	free;
395 };
396 
397 struct mlx5_uars_page {
398 	void __iomem	       *map;
399 	bool			wc;
400 	u32			index;
401 	struct list_head	list;
402 	unsigned int		bfregs;
403 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
404 	unsigned long	       *fp_bitmap;
405 	unsigned int		reg_avail;
406 	unsigned int		fp_avail;
407 	struct kref		ref_count;
408 	struct mlx5_core_dev   *mdev;
409 };
410 
411 struct mlx5_bfreg_head {
412 	/* protect blue flame registers allocations */
413 	struct mutex		lock;
414 	struct list_head	list;
415 };
416 
417 struct mlx5_bfreg_data {
418 	struct mlx5_bfreg_head	reg_head;
419 	struct mlx5_bfreg_head	wc_head;
420 };
421 
422 struct mlx5_sq_bfreg {
423 	void __iomem	       *map;
424 	struct mlx5_uars_page  *up;
425 	bool			wc;
426 	u32			index;
427 	unsigned int		offset;
428 };
429 
430 struct mlx5_core_health {
431 	struct health_buffer __iomem   *health;
432 	__be32 __iomem		       *health_counter;
433 	struct timer_list		timer;
434 	u32				prev;
435 	int				miss_counter;
436 	u8				synd;
437 	u32				fatal_error;
438 	u32				crdump_size;
439 	struct workqueue_struct	       *wq;
440 	unsigned long			flags;
441 	struct work_struct		fatal_report_work;
442 	struct work_struct		report_work;
443 	struct devlink_health_reporter *fw_reporter;
444 	struct devlink_health_reporter *fw_fatal_reporter;
445 	struct devlink_health_reporter *vnic_reporter;
446 	struct delayed_work		update_fw_log_ts_work;
447 };
448 
449 enum {
450 	MLX5_PF_NOTIFY_DISABLE_VF,
451 	MLX5_PF_NOTIFY_ENABLE_VF,
452 };
453 
454 struct mlx5_vf_context {
455 	int	enabled;
456 	u64	port_guid;
457 	u64	node_guid;
458 	/* Valid bits are used to validate administrative guid only.
459 	 * Enabled after ndo_set_vf_guid
460 	 */
461 	u8	port_guid_valid:1;
462 	u8	node_guid_valid:1;
463 	enum port_state_policy	policy;
464 	struct blocking_notifier_head notifier;
465 };
466 
467 struct mlx5_core_sriov {
468 	struct mlx5_vf_context	*vfs_ctx;
469 	int			num_vfs;
470 	u16			max_vfs;
471 	u16			max_ec_vfs;
472 };
473 
474 struct mlx5_fc_pool {
475 	struct mlx5_core_dev *dev;
476 	struct mutex pool_lock; /* protects pool lists */
477 	struct list_head fully_used;
478 	struct list_head partially_used;
479 	struct list_head unused;
480 	int available_fcs;
481 	int used_fcs;
482 	int threshold;
483 };
484 
485 struct mlx5_fc_stats {
486 	spinlock_t counters_idr_lock; /* protects counters_idr */
487 	struct idr counters_idr;
488 	struct list_head counters;
489 	struct llist_head addlist;
490 	struct llist_head dellist;
491 
492 	struct workqueue_struct *wq;
493 	struct delayed_work work;
494 	unsigned long next_query;
495 	unsigned long sampling_interval; /* jiffies */
496 	u32 *bulk_query_out;
497 	int bulk_query_len;
498 	size_t num_counters;
499 	bool bulk_query_alloc_failed;
500 	unsigned long next_bulk_query_alloc;
501 	struct mlx5_fc_pool fc_pool;
502 };
503 
504 struct mlx5_events;
505 struct mlx5_mpfs;
506 struct mlx5_eswitch;
507 struct mlx5_lag;
508 struct mlx5_devcom_dev;
509 struct mlx5_fw_reset;
510 struct mlx5_eq_table;
511 struct mlx5_irq_table;
512 struct mlx5_vhca_state_notifier;
513 struct mlx5_sf_dev_table;
514 struct mlx5_sf_hw_table;
515 struct mlx5_sf_table;
516 struct mlx5_crypto_dek_priv;
517 
518 struct mlx5_rate_limit {
519 	u32			rate;
520 	u32			max_burst_sz;
521 	u16			typical_pkt_sz;
522 };
523 
524 struct mlx5_rl_entry {
525 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
526 	u64 refcount;
527 	u16 index;
528 	u16 uid;
529 	u8 dedicated : 1;
530 };
531 
532 struct mlx5_rl_table {
533 	/* protect rate limit table */
534 	struct mutex            rl_lock;
535 	u16                     max_size;
536 	u32                     max_rate;
537 	u32                     min_rate;
538 	struct mlx5_rl_entry   *rl_entry;
539 	u64 refcount;
540 };
541 
542 struct mlx5_core_roce {
543 	struct mlx5_flow_table *ft;
544 	struct mlx5_flow_group *fg;
545 	struct mlx5_flow_handle *allow_rule;
546 };
547 
548 enum {
549 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
550 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
551 	/* Set during device detach to block any further devices
552 	 * creation/deletion on drivers rescan. Unset during device attach.
553 	 */
554 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
555 };
556 
557 struct mlx5_adev {
558 	struct auxiliary_device adev;
559 	struct mlx5_core_dev *mdev;
560 	int idx;
561 };
562 
563 struct mlx5_debugfs_entries {
564 	struct dentry *dbg_root;
565 	struct dentry *qp_debugfs;
566 	struct dentry *eq_debugfs;
567 	struct dentry *cq_debugfs;
568 	struct dentry *cmdif_debugfs;
569 	struct dentry *pages_debugfs;
570 	struct dentry *lag_debugfs;
571 };
572 
573 enum mlx5_func_type {
574 	MLX5_PF,
575 	MLX5_VF,
576 	MLX5_SF,
577 	MLX5_HOST_PF,
578 	MLX5_EC_VF,
579 	MLX5_FUNC_TYPE_NUM,
580 };
581 
582 struct mlx5_ft_pool;
583 struct mlx5_priv {
584 	/* IRQ table valid only for real pci devices PF or VF */
585 	struct mlx5_irq_table   *irq_table;
586 	struct mlx5_eq_table	*eq_table;
587 
588 	/* pages stuff */
589 	struct mlx5_nb          pg_nb;
590 	struct workqueue_struct *pg_wq;
591 	struct xarray           page_root_xa;
592 	atomic_t		reg_pages;
593 	struct list_head	free_list;
594 	u32			fw_pages;
595 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
596 	u32			fw_pages_alloc_failed;
597 	u32			give_pages_dropped;
598 	u32			reclaim_pages_discard;
599 
600 	struct mlx5_core_health health;
601 	struct list_head	traps;
602 
603 	struct mlx5_debugfs_entries dbg;
604 
605 	/* start: alloc staff */
606 	/* protect buffer allocation according to numa node */
607 	struct mutex            alloc_mutex;
608 	int                     numa_node;
609 
610 	struct mutex            pgdir_mutex;
611 	struct list_head        pgdir_list;
612 	/* end: alloc staff */
613 
614 	struct mlx5_adev       **adev;
615 	int			adev_idx;
616 	int			sw_vhca_id;
617 	struct mlx5_events      *events;
618 	struct mlx5_vhca_events *vhca_events;
619 
620 	struct mlx5_flow_steering *steering;
621 	struct mlx5_mpfs        *mpfs;
622 	struct mlx5_eswitch     *eswitch;
623 	struct mlx5_core_sriov	sriov;
624 	struct mlx5_lag		*lag;
625 	u32			flags;
626 	struct mlx5_devcom_dev	*devc;
627 	struct mlx5_devcom_comp_dev *hca_devcom_comp;
628 	struct mlx5_fw_reset	*fw_reset;
629 	struct mlx5_core_roce	roce;
630 	struct mlx5_fc_stats		fc_stats;
631 	struct mlx5_rl_table            rl_table;
632 	struct mlx5_ft_pool		*ft_pool;
633 
634 	struct mlx5_bfreg_data		bfregs;
635 	struct mlx5_uars_page	       *uar;
636 #ifdef CONFIG_MLX5_SF
637 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
638 	struct mlx5_sf_dev_table *sf_dev_table;
639 	struct mlx5_core_dev *parent_mdev;
640 #endif
641 #ifdef CONFIG_MLX5_SF_MANAGER
642 	struct mlx5_sf_hw_table *sf_hw_table;
643 	struct mlx5_sf_table *sf_table;
644 #endif
645 };
646 
647 enum mlx5_device_state {
648 	MLX5_DEVICE_STATE_UP = 1,
649 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
650 };
651 
652 enum mlx5_interface_state {
653 	MLX5_INTERFACE_STATE_UP = BIT(0),
654 	MLX5_BREAK_FW_WAIT = BIT(1),
655 };
656 
657 enum mlx5_pci_status {
658 	MLX5_PCI_STATUS_DISABLED,
659 	MLX5_PCI_STATUS_ENABLED,
660 };
661 
662 enum mlx5_pagefault_type_flags {
663 	MLX5_PFAULT_REQUESTOR = 1 << 0,
664 	MLX5_PFAULT_WRITE     = 1 << 1,
665 	MLX5_PFAULT_RDMA      = 1 << 2,
666 };
667 
668 struct mlx5_td {
669 	/* protects tirs list changes while tirs refresh */
670 	struct mutex     list_lock;
671 	struct list_head tirs_list;
672 	u32              tdn;
673 };
674 
675 struct mlx5e_resources {
676 	struct mlx5e_hw_objs {
677 		u32                        pdn;
678 		struct mlx5_td             td;
679 		u32			   mkey;
680 		struct mlx5_sq_bfreg       bfreg;
681 	} hw_objs;
682 	struct net_device *uplink_netdev;
683 	struct mutex uplink_netdev_lock;
684 	struct mlx5_crypto_dek_priv *dek_priv;
685 };
686 
687 enum mlx5_sw_icm_type {
688 	MLX5_SW_ICM_TYPE_STEERING,
689 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
690 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
691 	MLX5_SW_ICM_TYPE_SW_ENCAP,
692 };
693 
694 #define MLX5_MAX_RESERVED_GIDS 8
695 
696 struct mlx5_rsvd_gids {
697 	unsigned int start;
698 	unsigned int count;
699 	struct ida ida;
700 };
701 
702 #define MAX_PIN_NUM	8
703 struct mlx5_pps {
704 	u8                         pin_caps[MAX_PIN_NUM];
705 	struct work_struct         out_work;
706 	u64                        start[MAX_PIN_NUM];
707 	u8                         enabled;
708 	u64                        min_npps_period;
709 	u64                        min_out_pulse_duration_ns;
710 };
711 
712 struct mlx5_timer {
713 	struct cyclecounter        cycles;
714 	struct timecounter         tc;
715 	u32                        nominal_c_mult;
716 	unsigned long              overflow_period;
717 	struct delayed_work        overflow_work;
718 };
719 
720 struct mlx5_clock {
721 	struct mlx5_nb             pps_nb;
722 	seqlock_t                  lock;
723 	struct hwtstamp_config     hwtstamp_config;
724 	struct ptp_clock          *ptp;
725 	struct ptp_clock_info      ptp_info;
726 	struct mlx5_pps            pps_info;
727 	struct mlx5_timer          timer;
728 };
729 
730 struct mlx5_dm;
731 struct mlx5_fw_tracer;
732 struct mlx5_vxlan;
733 struct mlx5_geneve;
734 struct mlx5_hv_vhca;
735 
736 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
737 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
738 
739 enum {
740 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
741 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
742 };
743 
744 enum {
745 	MKEY_CACHE_LAST_STD_ENTRY = 20,
746 	MLX5_IMR_KSM_CACHE_ENTRY,
747 	MAX_MKEY_CACHE_ENTRIES
748 };
749 
750 struct mlx5_profile {
751 	u64	mask;
752 	u8	log_max_qp;
753 	u8	num_cmd_caches;
754 	struct {
755 		int	size;
756 		int	limit;
757 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
758 };
759 
760 struct mlx5_hca_cap {
761 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
762 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
763 };
764 
765 struct mlx5_core_dev {
766 	struct device *device;
767 	enum mlx5_coredev_type coredev_type;
768 	struct pci_dev	       *pdev;
769 	/* sync pci state */
770 	struct mutex		pci_status_mutex;
771 	enum mlx5_pci_status	pci_status;
772 	u8			rev_id;
773 	char			board_id[MLX5_BOARD_ID_LEN];
774 	struct mlx5_cmd		cmd;
775 	struct {
776 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
777 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
778 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
779 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
780 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
781 		u8  embedded_cpu;
782 	} caps;
783 	struct mlx5_timeouts	*timeouts;
784 	u64			sys_image_guid;
785 	phys_addr_t		iseg_base;
786 	struct mlx5_init_seg __iomem *iseg;
787 	phys_addr_t             bar_addr;
788 	enum mlx5_device_state	state;
789 	/* sync interface state */
790 	struct mutex		intf_state_mutex;
791 	struct lock_class_key	lock_key;
792 	unsigned long		intf_state;
793 	struct mlx5_priv	priv;
794 	struct mlx5_profile	profile;
795 	u32			issi;
796 	struct mlx5e_resources  mlx5e_res;
797 	struct mlx5_dm          *dm;
798 	struct mlx5_vxlan       *vxlan;
799 	struct mlx5_geneve      *geneve;
800 	struct {
801 		struct mlx5_rsvd_gids	reserved_gids;
802 		u32			roce_en;
803 	} roce;
804 #ifdef CONFIG_MLX5_FPGA
805 	struct mlx5_fpga_device *fpga;
806 #endif
807 	struct mlx5_clock        clock;
808 	struct mlx5_ib_clock_info  *clock_info;
809 	struct mlx5_fw_tracer   *tracer;
810 	struct mlx5_rsc_dump    *rsc_dump;
811 	u32                      vsc_addr;
812 	struct mlx5_hv_vhca	*hv_vhca;
813 	struct mlx5_hwmon	*hwmon;
814 	u64			num_block_tc;
815 	u64			num_block_ipsec;
816 #ifdef CONFIG_MLX5_MACSEC
817 	struct mlx5_macsec_fs *macsec_fs;
818 	/* MACsec notifier chain to sync MACsec core and IB database */
819 	struct blocking_notifier_head macsec_nh;
820 #endif
821 	u64 num_ipsec_offloads;
822 };
823 
824 struct mlx5_db {
825 	__be32			*db;
826 	union {
827 		struct mlx5_db_pgdir		*pgdir;
828 		struct mlx5_ib_user_db_page	*user_page;
829 	}			u;
830 	dma_addr_t		dma;
831 	int			index;
832 };
833 
834 enum {
835 	MLX5_COMP_EQ_SIZE = 1024,
836 };
837 
838 enum {
839 	MLX5_PTYS_IB = 1 << 0,
840 	MLX5_PTYS_EN = 1 << 2,
841 };
842 
843 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
844 
845 enum {
846 	MLX5_CMD_ENT_STATE_PENDING_COMP,
847 };
848 
849 struct mlx5_cmd_work_ent {
850 	unsigned long		state;
851 	struct mlx5_cmd_msg    *in;
852 	struct mlx5_cmd_msg    *out;
853 	void		       *uout;
854 	int			uout_size;
855 	mlx5_cmd_cbk_t		callback;
856 	struct delayed_work	cb_timeout_work;
857 	void		       *context;
858 	int			idx;
859 	struct completion	handling;
860 	struct completion	done;
861 	struct mlx5_cmd        *cmd;
862 	struct work_struct	work;
863 	struct mlx5_cmd_layout *lay;
864 	int			ret;
865 	int			page_queue;
866 	u8			status;
867 	u8			token;
868 	u64			ts1;
869 	u64			ts2;
870 	u16			op;
871 	bool			polling;
872 	/* Track the max comp handlers */
873 	refcount_t              refcnt;
874 };
875 
876 enum phy_port_state {
877 	MLX5_AAA_111
878 };
879 
880 struct mlx5_hca_vport_context {
881 	u32			field_select;
882 	bool			sm_virt_aware;
883 	bool			has_smi;
884 	bool			has_raw;
885 	enum port_state_policy	policy;
886 	enum phy_port_state	phys_state;
887 	enum ib_port_state	vport_state;
888 	u8			port_physical_state;
889 	u64			sys_image_guid;
890 	u64			port_guid;
891 	u64			node_guid;
892 	u32			cap_mask1;
893 	u32			cap_mask1_perm;
894 	u16			cap_mask2;
895 	u16			cap_mask2_perm;
896 	u16			lid;
897 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
898 	u8			lmc;
899 	u8			subnet_timeout;
900 	u16			sm_lid;
901 	u8			sm_sl;
902 	u16			qkey_violation_counter;
903 	u16			pkey_violation_counter;
904 	bool			grh_required;
905 };
906 
907 #define STRUCT_FIELD(header, field) \
908 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
909 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
910 
911 extern struct dentry *mlx5_debugfs_root;
912 
913 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
914 {
915 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
916 }
917 
918 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
919 {
920 	return ioread32be(&dev->iseg->fw_rev) >> 16;
921 }
922 
923 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
924 {
925 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
926 }
927 
928 static inline u32 mlx5_base_mkey(const u32 key)
929 {
930 	return key & 0xffffff00u;
931 }
932 
933 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
934 {
935 	return ((u32)1 << log_sz) << log_stride;
936 }
937 
938 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
939 					u8 log_stride, u8 log_sz,
940 					u16 strides_offset,
941 					struct mlx5_frag_buf_ctrl *fbc)
942 {
943 	fbc->frags      = frags;
944 	fbc->log_stride = log_stride;
945 	fbc->log_sz     = log_sz;
946 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
947 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
948 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
949 	fbc->strides_offset = strides_offset;
950 }
951 
952 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
953 				 u8 log_stride, u8 log_sz,
954 				 struct mlx5_frag_buf_ctrl *fbc)
955 {
956 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
957 }
958 
959 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
960 					  u32 ix)
961 {
962 	unsigned int frag;
963 
964 	ix  += fbc->strides_offset;
965 	frag = ix >> fbc->log_frag_strides;
966 
967 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
968 }
969 
970 static inline u32
971 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
972 {
973 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
974 
975 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
976 }
977 
978 enum {
979 	CMD_ALLOWED_OPCODE_ALL,
980 };
981 
982 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
983 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
984 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
985 
986 struct mlx5_async_ctx {
987 	struct mlx5_core_dev *dev;
988 	atomic_t num_inflight;
989 	struct completion inflight_done;
990 };
991 
992 struct mlx5_async_work;
993 
994 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
995 
996 struct mlx5_async_work {
997 	struct mlx5_async_ctx *ctx;
998 	mlx5_async_cbk_t user_callback;
999 	u16 opcode; /* cmd opcode */
1000 	u16 op_mod; /* cmd op_mod */
1001 	void *out; /* pointer to the cmd output buffer */
1002 };
1003 
1004 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1005 			     struct mlx5_async_ctx *ctx);
1006 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
1007 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1008 		     void *out, int out_size, mlx5_async_cbk_t callback,
1009 		     struct mlx5_async_work *work);
1010 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1011 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1012 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1013 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1014 		  int out_size);
1015 
1016 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1017 	({                                                                     \
1018 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1019 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1020 	})
1021 
1022 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1023 	({                                                                     \
1024 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1025 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1026 	})
1027 
1028 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1029 			  void *out, int out_size);
1030 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1031 
1032 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1033 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1034 
1035 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1036 
1037 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1038 int mlx5_health_init(struct mlx5_core_dev *dev);
1039 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1040 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1041 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1042 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1043 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1044 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1045 			     struct mlx5_frag_buf *buf, int node);
1046 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1047 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1048 			  int inlen);
1049 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1050 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1051 			 int outlen);
1052 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1053 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1054 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1055 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1056 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1057 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1058 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1059 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1060 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1061 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1062 void mlx5_register_debugfs(void);
1063 void mlx5_unregister_debugfs(void);
1064 
1065 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1066 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1067 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1068 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1069 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1070 
1071 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1072 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1073 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1074 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1075 		    void *data_out, int size_out, u16 reg_id, int arg,
1076 		    int write, bool verbose);
1077 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1078 			 int size_in, void *data_out, int size_out,
1079 			 u16 reg_num, int arg, int write);
1080 
1081 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1082 		       int node);
1083 
1084 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1085 {
1086 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1087 }
1088 
1089 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1090 
1091 const char *mlx5_command_str(int command);
1092 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1093 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1094 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1095 			 int npsvs, u32 *sig_index);
1096 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1097 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1098 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1099 
1100 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1101 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1102 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1103 		     struct mlx5_rate_limit *rl);
1104 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1105 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1106 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1107 			 bool dedicated_entry, u16 *index);
1108 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1109 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1110 		       struct mlx5_rate_limit *rl_1);
1111 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1112 		     bool map_wc, bool fast_path);
1113 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1114 
1115 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1116 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1117 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1118 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1119 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1120 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1121 
1122 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1123 {
1124 	return mkey >> 8;
1125 }
1126 
1127 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1128 {
1129 	return mkey_idx << 8;
1130 }
1131 
1132 static inline u8 mlx5_mkey_variant(u32 mkey)
1133 {
1134 	return mkey & 0xff;
1135 }
1136 
1137 /* Async-atomic event notifier used by mlx5 core to forward FW
1138  * evetns received from event queue to mlx5 consumers.
1139  * Optimise event queue dipatching.
1140  */
1141 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1143 
1144 /* Async-atomic event notifier used for forwarding
1145  * evetns from the event queue into the to mlx5 events dispatcher,
1146  * eswitch, clock and others.
1147  */
1148 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1149 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1150 
1151 /* Blocking event notifier used to forward SW events, used for slow path */
1152 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1153 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1154 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1155 				      void *data);
1156 
1157 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1158 
1159 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1160 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1161 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1162 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1163 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1164 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1165 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1166 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1167 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1168 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1169 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1170 			   struct net_device *slave);
1171 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1172 				 u64 *values,
1173 				 int num_counters,
1174 				 size_t *offsets);
1175 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1176 
1177 #define mlx5_lag_for_each_peer_mdev(dev, peer, i)				\
1178 	for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i);		\
1179 	     peer;								\
1180 	     peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1181 
1182 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1183 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1184 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1185 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1186 			 u64 length, u32 log_alignment, u16 uid,
1187 			 phys_addr_t *addr, u32 *obj_id);
1188 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1189 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1190 
1191 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1192 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1193 
1194 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1195 					  int vf_id,
1196 					  struct notifier_block *nb);
1197 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1198 					     int vf_id,
1199 					     struct notifier_block *nb);
1200 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1201 			    struct ib_device *device,
1202 			    struct rdma_netdev_alloc_params *params);
1203 
1204 enum {
1205 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1206 };
1207 
1208 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1209 {
1210 	return dev->coredev_type == MLX5_COREDEV_PF;
1211 }
1212 
1213 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1214 {
1215 	return dev->coredev_type == MLX5_COREDEV_VF;
1216 }
1217 
1218 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1219 {
1220 	return dev->caps.embedded_cpu;
1221 }
1222 
1223 static inline bool
1224 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1225 {
1226 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1227 }
1228 
1229 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1230 {
1231 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1232 }
1233 
1234 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1235 {
1236 	return dev->priv.sriov.max_vfs;
1237 }
1238 
1239 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1240 {
1241 	/* LACP owner conditions:
1242 	 * 1) Function is physical.
1243 	 * 2) LAG is supported by FW.
1244 	 * 3) LAG is managed by driver (currently the only option).
1245 	 */
1246 	return  MLX5_CAP_GEN(dev, vport_group_manager) &&
1247 		   (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1248 		    MLX5_CAP_GEN(dev, lag_master);
1249 }
1250 
1251 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1252 {
1253 	return dev->priv.sriov.max_ec_vfs;
1254 }
1255 
1256 static inline int mlx5_get_gid_table_len(u16 param)
1257 {
1258 	if (param > 4) {
1259 		pr_warn("gid table length is zero\n");
1260 		return 0;
1261 	}
1262 
1263 	return 8 * (1 << param);
1264 }
1265 
1266 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1267 {
1268 	return !!(dev->priv.rl_table.max_size);
1269 }
1270 
1271 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1272 {
1273 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1274 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1275 }
1276 
1277 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1278 {
1279 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1280 }
1281 
1282 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1283 {
1284 	return mlx5_core_is_mp_slave(dev) ||
1285 	       mlx5_core_is_mp_master(dev);
1286 }
1287 
1288 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1289 {
1290 	if (!mlx5_core_mp_enabled(dev))
1291 		return 1;
1292 
1293 	return MLX5_CAP_GEN(dev, native_port_num);
1294 }
1295 
1296 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1297 {
1298 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1299 
1300 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1301 		return idx - 1;
1302 	else
1303 		return PCI_FUNC(dev->pdev->devfn);
1304 }
1305 
1306 enum {
1307 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1308 };
1309 
1310 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1311 
1312 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1313 {
1314 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1315 		return MLX5_CAP_GEN(dev, roce);
1316 
1317 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1318 	 * in order to support RoCE enable/disable feature
1319 	 */
1320 	return mlx5_is_roce_on(dev);
1321 }
1322 
1323 #ifdef CONFIG_MLX5_MACSEC
1324 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1325 {
1326 	if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1327 	    MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1328 		return false;
1329 
1330 	if (!MLX5_CAP_GEN(mdev, log_max_dek))
1331 		return false;
1332 
1333 	if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1334 		return false;
1335 
1336 	if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1337 	    !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1338 		return false;
1339 
1340 	if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1341 	    !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1342 		return false;
1343 
1344 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1345 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1346 		return false;
1347 
1348 	if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1349 	    !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1350 		return false;
1351 
1352 	return true;
1353 }
1354 
1355 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1356 
1357 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1358 {
1359 	if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1360 	     NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1361 	     !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1362 	     !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1363 		return false;
1364 
1365 	return true;
1366 }
1367 #endif
1368 
1369 enum {
1370 	MLX5_OCTWORD = 16,
1371 };
1372 
1373 struct msi_map mlx5_msix_alloc(struct mlx5_core_dev *dev,
1374 			       irqreturn_t (*handler)(int, void *),
1375 			       const struct irq_affinity_desc *affdesc,
1376 			       const char *name);
1377 void mlx5_msix_free(struct mlx5_core_dev *dev, struct msi_map map);
1378 
1379 #endif /* MLX5_DRIVER_H */
1380