xref: /linux-6.15/include/linux/mlx5/driver.h (revision 982c97ee) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63 
64 enum {
65 	MLX5_BOARD_ID_LEN = 64,
66 };
67 
68 enum {
69 	MLX5_CMD_WQ_MAX_NAME	= 32,
70 };
71 
72 enum {
73 	CMD_OWNER_SW		= 0x0,
74 	CMD_OWNER_HW		= 0x1,
75 	CMD_STATUS_SUCCESS	= 0,
76 };
77 
78 enum mlx5_sqp_t {
79 	MLX5_SQP_SMI		= 0,
80 	MLX5_SQP_GSI		= 1,
81 	MLX5_SQP_IEEE_1588	= 2,
82 	MLX5_SQP_SNIFFER	= 3,
83 	MLX5_SQP_SYNC_UMR	= 4,
84 };
85 
86 enum {
87 	MLX5_MAX_PORTS	= 4,
88 };
89 
90 enum {
91 	MLX5_ATOMIC_MODE_OFFSET = 16,
92 	MLX5_ATOMIC_MODE_IB_COMP = 1,
93 	MLX5_ATOMIC_MODE_CX = 2,
94 	MLX5_ATOMIC_MODE_8B = 3,
95 	MLX5_ATOMIC_MODE_16B = 4,
96 	MLX5_ATOMIC_MODE_32B = 5,
97 	MLX5_ATOMIC_MODE_64B = 6,
98 	MLX5_ATOMIC_MODE_128B = 7,
99 	MLX5_ATOMIC_MODE_256B = 8,
100 };
101 
102 enum {
103 	MLX5_REG_QPTS            = 0x4002,
104 	MLX5_REG_QETCR		 = 0x4005,
105 	MLX5_REG_QTCT		 = 0x400a,
106 	MLX5_REG_QPDPM           = 0x4013,
107 	MLX5_REG_QCAM            = 0x4019,
108 	MLX5_REG_DCBX_PARAM      = 0x4020,
109 	MLX5_REG_DCBX_APP        = 0x4021,
110 	MLX5_REG_FPGA_CAP	 = 0x4022,
111 	MLX5_REG_FPGA_CTRL	 = 0x4023,
112 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 	MLX5_REG_CORE_DUMP	 = 0x402e,
114 	MLX5_REG_PCAP		 = 0x5001,
115 	MLX5_REG_PMTU		 = 0x5003,
116 	MLX5_REG_PTYS		 = 0x5004,
117 	MLX5_REG_PAOS		 = 0x5006,
118 	MLX5_REG_PFCC            = 0x5007,
119 	MLX5_REG_PPCNT		 = 0x5008,
120 	MLX5_REG_PPTB            = 0x500b,
121 	MLX5_REG_PBMC            = 0x500c,
122 	MLX5_REG_PMAOS		 = 0x5012,
123 	MLX5_REG_PUDE		 = 0x5009,
124 	MLX5_REG_PMPE		 = 0x5010,
125 	MLX5_REG_PELC		 = 0x500e,
126 	MLX5_REG_PVLC		 = 0x500f,
127 	MLX5_REG_PCMR		 = 0x5041,
128 	MLX5_REG_PDDR		 = 0x5031,
129 	MLX5_REG_PMLP		 = 0x5002,
130 	MLX5_REG_PPLM		 = 0x5023,
131 	MLX5_REG_PCAM		 = 0x507f,
132 	MLX5_REG_NODE_DESC	 = 0x6001,
133 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 	MLX5_REG_MCIA		 = 0x9014,
135 	MLX5_REG_MFRL		 = 0x9028,
136 	MLX5_REG_MLCR		 = 0x902b,
137 	MLX5_REG_MRTC		 = 0x902d,
138 	MLX5_REG_MTRC_CAP	 = 0x9040,
139 	MLX5_REG_MTRC_CONF	 = 0x9041,
140 	MLX5_REG_MTRC_STDB	 = 0x9042,
141 	MLX5_REG_MTRC_CTRL	 = 0x9043,
142 	MLX5_REG_MPEIN		 = 0x9050,
143 	MLX5_REG_MPCNT		 = 0x9051,
144 	MLX5_REG_MTPPS		 = 0x9053,
145 	MLX5_REG_MTPPSE		 = 0x9054,
146 	MLX5_REG_MTUTC		 = 0x9055,
147 	MLX5_REG_MPEGC		 = 0x9056,
148 	MLX5_REG_MCQS		 = 0x9060,
149 	MLX5_REG_MCQI		 = 0x9061,
150 	MLX5_REG_MCC		 = 0x9062,
151 	MLX5_REG_MCDA		 = 0x9063,
152 	MLX5_REG_MCAM		 = 0x907f,
153 	MLX5_REG_MIRC		 = 0x9162,
154 	MLX5_REG_SBCAM		 = 0xB01F,
155 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
156 	MLX5_REG_DTOR            = 0xC00E,
157 };
158 
159 enum mlx5_qpts_trust_state {
160 	MLX5_QPTS_TRUST_PCP  = 1,
161 	MLX5_QPTS_TRUST_DSCP = 2,
162 };
163 
164 enum mlx5_dcbx_oper_mode {
165 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
166 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
167 };
168 
169 enum {
170 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
171 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
172 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
174 };
175 
176 enum mlx5_page_fault_resume_flags {
177 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
179 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
180 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
181 };
182 
183 enum dbg_rsc_type {
184 	MLX5_DBG_RSC_QP,
185 	MLX5_DBG_RSC_EQ,
186 	MLX5_DBG_RSC_CQ,
187 };
188 
189 enum port_state_policy {
190 	MLX5_POLICY_DOWN	= 0,
191 	MLX5_POLICY_UP		= 1,
192 	MLX5_POLICY_FOLLOW	= 2,
193 	MLX5_POLICY_INVALID	= 0xffffffff
194 };
195 
196 enum mlx5_coredev_type {
197 	MLX5_COREDEV_PF,
198 	MLX5_COREDEV_VF,
199 	MLX5_COREDEV_SF,
200 };
201 
202 struct mlx5_field_desc {
203 	int			i;
204 };
205 
206 struct mlx5_rsc_debug {
207 	struct mlx5_core_dev   *dev;
208 	void		       *object;
209 	enum dbg_rsc_type	type;
210 	struct dentry	       *root;
211 	struct mlx5_field_desc	fields[];
212 };
213 
214 enum mlx5_dev_event {
215 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
217 };
218 
219 enum mlx5_port_status {
220 	MLX5_PORT_UP        = 1,
221 	MLX5_PORT_DOWN      = 2,
222 };
223 
224 enum mlx5_cmdif_state {
225 	MLX5_CMDIF_STATE_UNINITIALIZED,
226 	MLX5_CMDIF_STATE_UP,
227 	MLX5_CMDIF_STATE_DOWN,
228 };
229 
230 struct mlx5_cmd_first {
231 	__be32		data[4];
232 };
233 
234 struct mlx5_cmd_msg {
235 	struct list_head		list;
236 	struct cmd_msg_cache	       *parent;
237 	u32				len;
238 	struct mlx5_cmd_first		first;
239 	struct mlx5_cmd_mailbox	       *next;
240 };
241 
242 struct mlx5_cmd_debug {
243 	struct dentry	       *dbg_root;
244 	void		       *in_msg;
245 	void		       *out_msg;
246 	u8			status;
247 	u16			inlen;
248 	u16			outlen;
249 };
250 
251 struct cmd_msg_cache {
252 	/* protect block chain allocations
253 	 */
254 	spinlock_t		lock;
255 	struct list_head	head;
256 	unsigned int		max_inbox_size;
257 	unsigned int		num_ent;
258 };
259 
260 enum {
261 	MLX5_NUM_COMMAND_CACHES = 5,
262 };
263 
264 struct mlx5_cmd_stats {
265 	u64		sum;
266 	u64		n;
267 	/* number of times command failed */
268 	u64		failed;
269 	/* number of times command failed on bad status returned by FW */
270 	u64		failed_mbox_status;
271 	/* last command failed returned errno */
272 	u32		last_failed_errno;
273 	/* last bad status returned by FW */
274 	u8		last_failed_mbox_status;
275 	struct dentry  *root;
276 	/* protect command average calculations */
277 	spinlock_t	lock;
278 };
279 
280 struct mlx5_cmd {
281 	struct mlx5_nb    nb;
282 
283 	enum mlx5_cmdif_state	state;
284 	void	       *cmd_alloc_buf;
285 	dma_addr_t	alloc_dma;
286 	int		alloc_size;
287 	void	       *cmd_buf;
288 	dma_addr_t	dma;
289 	u16		cmdif_rev;
290 	u8		log_sz;
291 	u8		log_stride;
292 	int		max_reg_cmds;
293 	int		events;
294 	u32 __iomem    *vector;
295 
296 	/* protect command queue allocations
297 	 */
298 	spinlock_t	alloc_lock;
299 
300 	/* protect token allocations
301 	 */
302 	spinlock_t	token_lock;
303 	u8		token;
304 	unsigned long	bitmask;
305 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
306 	struct workqueue_struct *wq;
307 	struct semaphore sem;
308 	struct semaphore pages_sem;
309 	int	mode;
310 	u16     allowed_opcode;
311 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
312 	struct dma_pool *pool;
313 	struct mlx5_cmd_debug dbg;
314 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
315 	int checksum_disabled;
316 	struct mlx5_cmd_stats *stats;
317 };
318 
319 struct mlx5_cmd_mailbox {
320 	void	       *buf;
321 	dma_addr_t	dma;
322 	struct mlx5_cmd_mailbox *next;
323 };
324 
325 struct mlx5_buf_list {
326 	void		       *buf;
327 	dma_addr_t		map;
328 };
329 
330 struct mlx5_frag_buf {
331 	struct mlx5_buf_list	*frags;
332 	int			npages;
333 	int			size;
334 	u8			page_shift;
335 };
336 
337 struct mlx5_frag_buf_ctrl {
338 	struct mlx5_buf_list   *frags;
339 	u32			sz_m1;
340 	u16			frag_sz_m1;
341 	u16			strides_offset;
342 	u8			log_sz;
343 	u8			log_stride;
344 	u8			log_frag_strides;
345 };
346 
347 struct mlx5_core_psv {
348 	u32	psv_idx;
349 	struct psv_layout {
350 		u32	pd;
351 		u16	syndrome;
352 		u16	reserved;
353 		u16	bg;
354 		u16	app_tag;
355 		u32	ref_tag;
356 	} psv;
357 };
358 
359 struct mlx5_core_sig_ctx {
360 	struct mlx5_core_psv	psv_memory;
361 	struct mlx5_core_psv	psv_wire;
362 	struct ib_sig_err       err_item;
363 	bool			sig_status_checked;
364 	bool			sig_err_exists;
365 	u32			sigerr_count;
366 };
367 
368 #define MLX5_24BIT_MASK		((1 << 24) - 1)
369 
370 enum mlx5_res_type {
371 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
372 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
373 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
374 	MLX5_RES_SRQ	= 3,
375 	MLX5_RES_XSRQ	= 4,
376 	MLX5_RES_XRQ	= 5,
377 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
378 };
379 
380 struct mlx5_core_rsc_common {
381 	enum mlx5_res_type	res;
382 	refcount_t		refcount;
383 	struct completion	free;
384 };
385 
386 struct mlx5_uars_page {
387 	void __iomem	       *map;
388 	bool			wc;
389 	u32			index;
390 	struct list_head	list;
391 	unsigned int		bfregs;
392 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
393 	unsigned long	       *fp_bitmap;
394 	unsigned int		reg_avail;
395 	unsigned int		fp_avail;
396 	struct kref		ref_count;
397 	struct mlx5_core_dev   *mdev;
398 };
399 
400 struct mlx5_bfreg_head {
401 	/* protect blue flame registers allocations */
402 	struct mutex		lock;
403 	struct list_head	list;
404 };
405 
406 struct mlx5_bfreg_data {
407 	struct mlx5_bfreg_head	reg_head;
408 	struct mlx5_bfreg_head	wc_head;
409 };
410 
411 struct mlx5_sq_bfreg {
412 	void __iomem	       *map;
413 	struct mlx5_uars_page  *up;
414 	bool			wc;
415 	u32			index;
416 	unsigned int		offset;
417 };
418 
419 struct mlx5_core_health {
420 	struct health_buffer __iomem   *health;
421 	__be32 __iomem		       *health_counter;
422 	struct timer_list		timer;
423 	u32				prev;
424 	int				miss_counter;
425 	u8				synd;
426 	u32				fatal_error;
427 	u32				crdump_size;
428 	/* wq spinlock to synchronize draining */
429 	spinlock_t			wq_lock;
430 	struct workqueue_struct	       *wq;
431 	unsigned long			flags;
432 	struct work_struct		fatal_report_work;
433 	struct work_struct		report_work;
434 	struct devlink_health_reporter *fw_reporter;
435 	struct devlink_health_reporter *fw_fatal_reporter;
436 	struct delayed_work		update_fw_log_ts_work;
437 };
438 
439 struct mlx5_qp_table {
440 	struct notifier_block   nb;
441 
442 	/* protect radix tree
443 	 */
444 	spinlock_t		lock;
445 	struct radix_tree_root	tree;
446 };
447 
448 struct mlx5_vf_context {
449 	int	enabled;
450 	u64	port_guid;
451 	u64	node_guid;
452 	/* Valid bits are used to validate administrative guid only.
453 	 * Enabled after ndo_set_vf_guid
454 	 */
455 	u8	port_guid_valid:1;
456 	u8	node_guid_valid:1;
457 	enum port_state_policy	policy;
458 };
459 
460 struct mlx5_core_sriov {
461 	struct mlx5_vf_context	*vfs_ctx;
462 	int			num_vfs;
463 	u16			max_vfs;
464 };
465 
466 struct mlx5_fc_pool {
467 	struct mlx5_core_dev *dev;
468 	struct mutex pool_lock; /* protects pool lists */
469 	struct list_head fully_used;
470 	struct list_head partially_used;
471 	struct list_head unused;
472 	int available_fcs;
473 	int used_fcs;
474 	int threshold;
475 };
476 
477 struct mlx5_fc_stats {
478 	spinlock_t counters_idr_lock; /* protects counters_idr */
479 	struct idr counters_idr;
480 	struct list_head counters;
481 	struct llist_head addlist;
482 	struct llist_head dellist;
483 
484 	struct workqueue_struct *wq;
485 	struct delayed_work work;
486 	unsigned long next_query;
487 	unsigned long sampling_interval; /* jiffies */
488 	u32 *bulk_query_out;
489 	int bulk_query_len;
490 	size_t num_counters;
491 	bool bulk_query_alloc_failed;
492 	unsigned long next_bulk_query_alloc;
493 	struct mlx5_fc_pool fc_pool;
494 };
495 
496 struct mlx5_events;
497 struct mlx5_mpfs;
498 struct mlx5_eswitch;
499 struct mlx5_lag;
500 struct mlx5_devcom;
501 struct mlx5_fw_reset;
502 struct mlx5_eq_table;
503 struct mlx5_irq_table;
504 struct mlx5_vhca_state_notifier;
505 struct mlx5_sf_dev_table;
506 struct mlx5_sf_hw_table;
507 struct mlx5_sf_table;
508 
509 struct mlx5_rate_limit {
510 	u32			rate;
511 	u32			max_burst_sz;
512 	u16			typical_pkt_sz;
513 };
514 
515 struct mlx5_rl_entry {
516 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
517 	u64 refcount;
518 	u16 index;
519 	u16 uid;
520 	u8 dedicated : 1;
521 };
522 
523 struct mlx5_rl_table {
524 	/* protect rate limit table */
525 	struct mutex            rl_lock;
526 	u16                     max_size;
527 	u32                     max_rate;
528 	u32                     min_rate;
529 	struct mlx5_rl_entry   *rl_entry;
530 	u64 refcount;
531 };
532 
533 struct mlx5_core_roce {
534 	struct mlx5_flow_table *ft;
535 	struct mlx5_flow_group *fg;
536 	struct mlx5_flow_handle *allow_rule;
537 };
538 
539 enum {
540 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
541 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
542 	/* Set during device detach to block any further devices
543 	 * creation/deletion on drivers rescan. Unset during device attach.
544 	 */
545 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
546 };
547 
548 struct mlx5_adev {
549 	struct auxiliary_device adev;
550 	struct mlx5_core_dev *mdev;
551 	int idx;
552 };
553 
554 struct mlx5_debugfs_entries {
555 	struct dentry *dbg_root;
556 	struct dentry *qp_debugfs;
557 	struct dentry *eq_debugfs;
558 	struct dentry *cq_debugfs;
559 	struct dentry *cmdif_debugfs;
560 	struct dentry *pages_debugfs;
561 	struct dentry *lag_debugfs;
562 };
563 
564 struct mlx5_ft_pool;
565 struct mlx5_priv {
566 	/* IRQ table valid only for real pci devices PF or VF */
567 	struct mlx5_irq_table   *irq_table;
568 	struct mlx5_eq_table	*eq_table;
569 
570 	/* pages stuff */
571 	struct mlx5_nb          pg_nb;
572 	struct workqueue_struct *pg_wq;
573 	struct xarray           page_root_xa;
574 	u32			fw_pages;
575 	atomic_t		reg_pages;
576 	struct list_head	free_list;
577 	u32			vfs_pages;
578 	u32			host_pf_pages;
579 	u32			fw_pages_alloc_failed;
580 	u32			give_pages_dropped;
581 	u32			reclaim_pages_discard;
582 
583 	struct mlx5_core_health health;
584 	struct list_head	traps;
585 
586 	struct mlx5_debugfs_entries dbg;
587 
588 	/* start: alloc staff */
589 	/* protect buffer allocation according to numa node */
590 	struct mutex            alloc_mutex;
591 	int                     numa_node;
592 
593 	struct mutex            pgdir_mutex;
594 	struct list_head        pgdir_list;
595 	/* end: alloc staff */
596 
597 	struct list_head        ctx_list;
598 	spinlock_t              ctx_lock;
599 	struct mlx5_adev       **adev;
600 	int			adev_idx;
601 	struct mlx5_events      *events;
602 
603 	struct mlx5_flow_steering *steering;
604 	struct mlx5_mpfs        *mpfs;
605 	struct mlx5_eswitch     *eswitch;
606 	struct mlx5_core_sriov	sriov;
607 	struct mlx5_lag		*lag;
608 	u32			flags;
609 	struct mlx5_devcom	*devcom;
610 	struct mlx5_fw_reset	*fw_reset;
611 	struct mlx5_core_roce	roce;
612 	struct mlx5_fc_stats		fc_stats;
613 	struct mlx5_rl_table            rl_table;
614 	struct mlx5_ft_pool		*ft_pool;
615 
616 	struct mlx5_bfreg_data		bfregs;
617 	struct mlx5_uars_page	       *uar;
618 #ifdef CONFIG_MLX5_SF
619 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
620 	struct mlx5_sf_dev_table *sf_dev_table;
621 	struct mlx5_core_dev *parent_mdev;
622 #endif
623 #ifdef CONFIG_MLX5_SF_MANAGER
624 	struct mlx5_sf_hw_table *sf_hw_table;
625 	struct mlx5_sf_table *sf_table;
626 #endif
627 };
628 
629 enum mlx5_device_state {
630 	MLX5_DEVICE_STATE_UP = 1,
631 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
632 };
633 
634 enum mlx5_interface_state {
635 	MLX5_INTERFACE_STATE_UP = BIT(0),
636 	MLX5_BREAK_FW_WAIT = BIT(1),
637 };
638 
639 enum mlx5_pci_status {
640 	MLX5_PCI_STATUS_DISABLED,
641 	MLX5_PCI_STATUS_ENABLED,
642 };
643 
644 enum mlx5_pagefault_type_flags {
645 	MLX5_PFAULT_REQUESTOR = 1 << 0,
646 	MLX5_PFAULT_WRITE     = 1 << 1,
647 	MLX5_PFAULT_RDMA      = 1 << 2,
648 };
649 
650 struct mlx5_td {
651 	/* protects tirs list changes while tirs refresh */
652 	struct mutex     list_lock;
653 	struct list_head tirs_list;
654 	u32              tdn;
655 };
656 
657 struct mlx5e_resources {
658 	struct mlx5e_hw_objs {
659 		u32                        pdn;
660 		struct mlx5_td             td;
661 		u32			   mkey;
662 		struct mlx5_sq_bfreg       bfreg;
663 	} hw_objs;
664 	struct devlink_port dl_port;
665 	struct net_device *uplink_netdev;
666 };
667 
668 enum mlx5_sw_icm_type {
669 	MLX5_SW_ICM_TYPE_STEERING,
670 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
671 };
672 
673 #define MLX5_MAX_RESERVED_GIDS 8
674 
675 struct mlx5_rsvd_gids {
676 	unsigned int start;
677 	unsigned int count;
678 	struct ida ida;
679 };
680 
681 #define MAX_PIN_NUM	8
682 struct mlx5_pps {
683 	u8                         pin_caps[MAX_PIN_NUM];
684 	struct work_struct         out_work;
685 	u64                        start[MAX_PIN_NUM];
686 	u8                         enabled;
687 };
688 
689 struct mlx5_timer {
690 	struct cyclecounter        cycles;
691 	struct timecounter         tc;
692 	u32                        nominal_c_mult;
693 	unsigned long              overflow_period;
694 	struct delayed_work        overflow_work;
695 };
696 
697 struct mlx5_clock {
698 	struct mlx5_nb             pps_nb;
699 	seqlock_t                  lock;
700 	struct hwtstamp_config     hwtstamp_config;
701 	struct ptp_clock          *ptp;
702 	struct ptp_clock_info      ptp_info;
703 	struct mlx5_pps            pps_info;
704 	struct mlx5_timer          timer;
705 };
706 
707 struct mlx5_dm;
708 struct mlx5_fw_tracer;
709 struct mlx5_vxlan;
710 struct mlx5_geneve;
711 struct mlx5_hv_vhca;
712 
713 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
714 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
715 
716 enum {
717 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
718 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
719 };
720 
721 enum {
722 	MR_CACHE_LAST_STD_ENTRY = 20,
723 	MLX5_IMR_MTT_CACHE_ENTRY,
724 	MLX5_IMR_KSM_CACHE_ENTRY,
725 	MAX_MR_CACHE_ENTRIES
726 };
727 
728 struct mlx5_profile {
729 	u64	mask;
730 	u8	log_max_qp;
731 	struct {
732 		int	size;
733 		int	limit;
734 	} mr_cache[MAX_MR_CACHE_ENTRIES];
735 };
736 
737 struct mlx5_hca_cap {
738 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
739 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
740 };
741 
742 struct mlx5_core_dev {
743 	struct device *device;
744 	enum mlx5_coredev_type coredev_type;
745 	struct pci_dev	       *pdev;
746 	/* sync pci state */
747 	struct mutex		pci_status_mutex;
748 	enum mlx5_pci_status	pci_status;
749 	u8			rev_id;
750 	char			board_id[MLX5_BOARD_ID_LEN];
751 	struct mlx5_cmd		cmd;
752 	struct {
753 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
754 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
755 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
756 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
757 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
758 		u8  embedded_cpu;
759 	} caps;
760 	struct mlx5_timeouts	*timeouts;
761 	u64			sys_image_guid;
762 	phys_addr_t		iseg_base;
763 	struct mlx5_init_seg __iomem *iseg;
764 	phys_addr_t             bar_addr;
765 	enum mlx5_device_state	state;
766 	/* sync interface state */
767 	struct mutex		intf_state_mutex;
768 	unsigned long		intf_state;
769 	struct mlx5_priv	priv;
770 	struct mlx5_profile	profile;
771 	u32			issi;
772 	struct mlx5e_resources  mlx5e_res;
773 	struct mlx5_dm          *dm;
774 	struct mlx5_vxlan       *vxlan;
775 	struct mlx5_geneve      *geneve;
776 	struct {
777 		struct mlx5_rsvd_gids	reserved_gids;
778 		u32			roce_en;
779 	} roce;
780 #ifdef CONFIG_MLX5_FPGA
781 	struct mlx5_fpga_device *fpga;
782 #endif
783 	struct mlx5_clock        clock;
784 	struct mlx5_ib_clock_info  *clock_info;
785 	struct mlx5_fw_tracer   *tracer;
786 	struct mlx5_rsc_dump    *rsc_dump;
787 	u32                      vsc_addr;
788 	struct mlx5_hv_vhca	*hv_vhca;
789 };
790 
791 struct mlx5_db {
792 	__be32			*db;
793 	union {
794 		struct mlx5_db_pgdir		*pgdir;
795 		struct mlx5_ib_user_db_page	*user_page;
796 	}			u;
797 	dma_addr_t		dma;
798 	int			index;
799 };
800 
801 enum {
802 	MLX5_COMP_EQ_SIZE = 1024,
803 };
804 
805 enum {
806 	MLX5_PTYS_IB = 1 << 0,
807 	MLX5_PTYS_EN = 1 << 2,
808 };
809 
810 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
811 
812 enum {
813 	MLX5_CMD_ENT_STATE_PENDING_COMP,
814 };
815 
816 struct mlx5_cmd_work_ent {
817 	unsigned long		state;
818 	struct mlx5_cmd_msg    *in;
819 	struct mlx5_cmd_msg    *out;
820 	void		       *uout;
821 	int			uout_size;
822 	mlx5_cmd_cbk_t		callback;
823 	struct delayed_work	cb_timeout_work;
824 	void		       *context;
825 	int			idx;
826 	struct completion	handling;
827 	struct completion	done;
828 	struct mlx5_cmd        *cmd;
829 	struct work_struct	work;
830 	struct mlx5_cmd_layout *lay;
831 	int			ret;
832 	int			page_queue;
833 	u8			status;
834 	u8			token;
835 	u64			ts1;
836 	u64			ts2;
837 	u16			op;
838 	bool			polling;
839 	/* Track the max comp handlers */
840 	refcount_t              refcnt;
841 };
842 
843 struct mlx5_pas {
844 	u64	pa;
845 	u8	log_sz;
846 };
847 
848 enum phy_port_state {
849 	MLX5_AAA_111
850 };
851 
852 struct mlx5_hca_vport_context {
853 	u32			field_select;
854 	bool			sm_virt_aware;
855 	bool			has_smi;
856 	bool			has_raw;
857 	enum port_state_policy	policy;
858 	enum phy_port_state	phys_state;
859 	enum ib_port_state	vport_state;
860 	u8			port_physical_state;
861 	u64			sys_image_guid;
862 	u64			port_guid;
863 	u64			node_guid;
864 	u32			cap_mask1;
865 	u32			cap_mask1_perm;
866 	u16			cap_mask2;
867 	u16			cap_mask2_perm;
868 	u16			lid;
869 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
870 	u8			lmc;
871 	u8			subnet_timeout;
872 	u16			sm_lid;
873 	u8			sm_sl;
874 	u16			qkey_violation_counter;
875 	u16			pkey_violation_counter;
876 	bool			grh_required;
877 };
878 
879 #define STRUCT_FIELD(header, field) \
880 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
881 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
882 
883 extern struct dentry *mlx5_debugfs_root;
884 
885 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
886 {
887 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
888 }
889 
890 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
891 {
892 	return ioread32be(&dev->iseg->fw_rev) >> 16;
893 }
894 
895 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
896 {
897 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
898 }
899 
900 static inline u32 mlx5_base_mkey(const u32 key)
901 {
902 	return key & 0xffffff00u;
903 }
904 
905 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
906 {
907 	return ((u32)1 << log_sz) << log_stride;
908 }
909 
910 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
911 					u8 log_stride, u8 log_sz,
912 					u16 strides_offset,
913 					struct mlx5_frag_buf_ctrl *fbc)
914 {
915 	fbc->frags      = frags;
916 	fbc->log_stride = log_stride;
917 	fbc->log_sz     = log_sz;
918 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
919 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
920 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
921 	fbc->strides_offset = strides_offset;
922 }
923 
924 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
925 				 u8 log_stride, u8 log_sz,
926 				 struct mlx5_frag_buf_ctrl *fbc)
927 {
928 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
929 }
930 
931 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
932 					  u32 ix)
933 {
934 	unsigned int frag;
935 
936 	ix  += fbc->strides_offset;
937 	frag = ix >> fbc->log_frag_strides;
938 
939 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
940 }
941 
942 static inline u32
943 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
944 {
945 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
946 
947 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
948 }
949 
950 enum {
951 	CMD_ALLOWED_OPCODE_ALL,
952 };
953 
954 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
955 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
956 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
957 
958 struct mlx5_async_ctx {
959 	struct mlx5_core_dev *dev;
960 	atomic_t num_inflight;
961 	struct wait_queue_head wait;
962 };
963 
964 struct mlx5_async_work;
965 
966 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
967 
968 struct mlx5_async_work {
969 	struct mlx5_async_ctx *ctx;
970 	mlx5_async_cbk_t user_callback;
971 	u16 opcode; /* cmd opcode */
972 	void *out; /* pointer to the cmd output buffer */
973 };
974 
975 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
976 			     struct mlx5_async_ctx *ctx);
977 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
978 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
979 		     void *out, int out_size, mlx5_async_cbk_t callback,
980 		     struct mlx5_async_work *work);
981 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
982 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
983 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
984 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
985 		  int out_size);
986 
987 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
988 	({                                                                     \
989 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
990 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
991 	})
992 
993 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
994 	({                                                                     \
995 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
996 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
997 	})
998 
999 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1000 			  void *out, int out_size);
1001 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1002 
1003 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1004 void mlx5_health_flush(struct mlx5_core_dev *dev);
1005 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1006 int mlx5_health_init(struct mlx5_core_dev *dev);
1007 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1008 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1009 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1010 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1011 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1012 			     struct mlx5_frag_buf *buf, int node);
1013 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1014 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1015 						      gfp_t flags, int npages);
1016 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1017 				 struct mlx5_cmd_mailbox *head);
1018 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1019 			  int inlen);
1020 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1021 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1022 			 int outlen);
1023 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1024 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1025 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1026 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1027 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1028 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1029 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1030 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1031 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1032 				 s32 npages, bool ec_function);
1033 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1034 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1035 void mlx5_register_debugfs(void);
1036 void mlx5_unregister_debugfs(void);
1037 
1038 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1039 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1040 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1041 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1042 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1043 
1044 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1045 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1046 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1047 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1048 		    void *data_out, int size_out, u16 reg_id, int arg,
1049 		    int write, bool verbose);
1050 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1051 			 int size_in, void *data_out, int size_out,
1052 			 u16 reg_num, int arg, int write);
1053 
1054 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1055 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1056 		       int node);
1057 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1058 
1059 const char *mlx5_command_str(int command);
1060 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1061 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1062 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1063 			 int npsvs, u32 *sig_index);
1064 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1065 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1066 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1067 			struct mlx5_odp_caps *odp_caps);
1068 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1069 			     u8 port_num, void *out, size_t sz);
1070 
1071 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1072 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1073 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1074 		     struct mlx5_rate_limit *rl);
1075 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1076 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1077 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1078 			 bool dedicated_entry, u16 *index);
1079 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1080 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1081 		       struct mlx5_rate_limit *rl_1);
1082 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1083 		     bool map_wc, bool fast_path);
1084 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1085 
1086 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1087 struct cpumask *
1088 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1089 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1090 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1091 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1092 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1093 
1094 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1095 {
1096 	return mkey >> 8;
1097 }
1098 
1099 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1100 {
1101 	return mkey_idx << 8;
1102 }
1103 
1104 static inline u8 mlx5_mkey_variant(u32 mkey)
1105 {
1106 	return mkey & 0xff;
1107 }
1108 
1109 /* Async-atomic event notifier used by mlx5 core to forward FW
1110  * evetns received from event queue to mlx5 consumers.
1111  * Optimise event queue dipatching.
1112  */
1113 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1114 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1115 
1116 /* Async-atomic event notifier used for forwarding
1117  * evetns from the event queue into the to mlx5 events dispatcher,
1118  * eswitch, clock and others.
1119  */
1120 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1121 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1122 
1123 /* Blocking event notifier used to forward SW events, used for slow path */
1124 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1125 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1126 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1127 				      void *data);
1128 
1129 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1130 
1131 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1132 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1133 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1134 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1135 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1136 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1137 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1138 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1139 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1140 			   struct net_device *slave);
1141 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1142 				 u64 *values,
1143 				 int num_counters,
1144 				 size_t *offsets);
1145 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1146 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1147 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1148 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1149 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1150 			 u64 length, u32 log_alignment, u16 uid,
1151 			 phys_addr_t *addr, u32 *obj_id);
1152 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1153 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1154 
1155 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1156 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1157 
1158 #ifdef CONFIG_MLX5_CORE_IPOIB
1159 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1160 					  struct ib_device *ibdev,
1161 					  const char *name,
1162 					  void (*setup)(struct net_device *));
1163 #endif /* CONFIG_MLX5_CORE_IPOIB */
1164 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1165 			    struct ib_device *device,
1166 			    struct rdma_netdev_alloc_params *params);
1167 
1168 enum {
1169 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1170 };
1171 
1172 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1173 {
1174 	return dev->coredev_type == MLX5_COREDEV_PF;
1175 }
1176 
1177 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1178 {
1179 	return dev->coredev_type == MLX5_COREDEV_VF;
1180 }
1181 
1182 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1183 {
1184 	return dev->caps.embedded_cpu;
1185 }
1186 
1187 static inline bool
1188 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1189 {
1190 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1191 }
1192 
1193 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1194 {
1195 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1196 }
1197 
1198 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1199 {
1200 	return dev->priv.sriov.max_vfs;
1201 }
1202 
1203 static inline int mlx5_get_gid_table_len(u16 param)
1204 {
1205 	if (param > 4) {
1206 		pr_warn("gid table length is zero\n");
1207 		return 0;
1208 	}
1209 
1210 	return 8 * (1 << param);
1211 }
1212 
1213 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1214 {
1215 	return !!(dev->priv.rl_table.max_size);
1216 }
1217 
1218 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1219 {
1220 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1221 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1222 }
1223 
1224 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1225 {
1226 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1227 }
1228 
1229 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1230 {
1231 	return mlx5_core_is_mp_slave(dev) ||
1232 	       mlx5_core_is_mp_master(dev);
1233 }
1234 
1235 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1236 {
1237 	if (!mlx5_core_mp_enabled(dev))
1238 		return 1;
1239 
1240 	return MLX5_CAP_GEN(dev, native_port_num);
1241 }
1242 
1243 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1244 {
1245 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1246 
1247 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1248 		return idx - 1;
1249 	else
1250 		return PCI_FUNC(dev->pdev->devfn);
1251 }
1252 
1253 enum {
1254 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1255 };
1256 
1257 static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
1258 {
1259 	struct devlink *devlink = priv_to_devlink(dev);
1260 	union devlink_param_value val;
1261 	int err;
1262 
1263 	err = devlink_param_driverinit_value_get(devlink,
1264 						 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1265 						 &val);
1266 	return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;
1267 }
1268 
1269 #endif /* MLX5_DRIVER_H */
1270