xref: /linux-6.15/include/linux/mlx5/driver.h (revision 83a37b32) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
44 #include <linux/workqueue.h>
45 #include <linux/mempool.h>
46 #include <linux/interrupt.h>
47 #include <linux/idr.h>
48 
49 #include <linux/mlx5/device.h>
50 #include <linux/mlx5/doorbell.h>
51 #include <linux/mlx5/srq.h>
52 #include <linux/timecounter.h>
53 #include <linux/ptp_clock_kernel.h>
54 
55 enum {
56 	MLX5_BOARD_ID_LEN = 64,
57 	MLX5_MAX_NAME_LEN = 16,
58 };
59 
60 enum {
61 	/* one minute for the sake of bringup. Generally, commands must always
62 	 * complete and we may need to increase this timeout value
63 	 */
64 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
65 	MLX5_CMD_WQ_MAX_NAME	= 32,
66 };
67 
68 enum {
69 	CMD_OWNER_SW		= 0x0,
70 	CMD_OWNER_HW		= 0x1,
71 	CMD_STATUS_SUCCESS	= 0,
72 };
73 
74 enum mlx5_sqp_t {
75 	MLX5_SQP_SMI		= 0,
76 	MLX5_SQP_GSI		= 1,
77 	MLX5_SQP_IEEE_1588	= 2,
78 	MLX5_SQP_SNIFFER	= 3,
79 	MLX5_SQP_SYNC_UMR	= 4,
80 };
81 
82 enum {
83 	MLX5_MAX_PORTS	= 2,
84 };
85 
86 enum {
87 	MLX5_EQ_VEC_PAGES	 = 0,
88 	MLX5_EQ_VEC_CMD		 = 1,
89 	MLX5_EQ_VEC_ASYNC	 = 2,
90 	MLX5_EQ_VEC_PFAULT	 = 3,
91 	MLX5_EQ_VEC_COMP_BASE,
92 };
93 
94 enum {
95 	MLX5_MAX_IRQ_NAME	= 32
96 };
97 
98 enum {
99 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << 16,
100 	MLX5_ATOMIC_MODE_CX		= 2 << 16,
101 	MLX5_ATOMIC_MODE_8B		= 3 << 16,
102 	MLX5_ATOMIC_MODE_16B		= 4 << 16,
103 	MLX5_ATOMIC_MODE_32B		= 5 << 16,
104 	MLX5_ATOMIC_MODE_64B		= 6 << 16,
105 	MLX5_ATOMIC_MODE_128B		= 7 << 16,
106 	MLX5_ATOMIC_MODE_256B		= 8 << 16,
107 };
108 
109 enum {
110 	MLX5_REG_QETCR		 = 0x4005,
111 	MLX5_REG_QTCT		 = 0x400a,
112 	MLX5_REG_DCBX_PARAM      = 0x4020,
113 	MLX5_REG_DCBX_APP        = 0x4021,
114 	MLX5_REG_FPGA_CAP	 = 0x4022,
115 	MLX5_REG_FPGA_CTRL	 = 0x4023,
116 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
117 	MLX5_REG_PCAP		 = 0x5001,
118 	MLX5_REG_PMTU		 = 0x5003,
119 	MLX5_REG_PTYS		 = 0x5004,
120 	MLX5_REG_PAOS		 = 0x5006,
121 	MLX5_REG_PFCC            = 0x5007,
122 	MLX5_REG_PPCNT		 = 0x5008,
123 	MLX5_REG_PMAOS		 = 0x5012,
124 	MLX5_REG_PUDE		 = 0x5009,
125 	MLX5_REG_PMPE		 = 0x5010,
126 	MLX5_REG_PELC		 = 0x500e,
127 	MLX5_REG_PVLC		 = 0x500f,
128 	MLX5_REG_PCMR		 = 0x5041,
129 	MLX5_REG_PMLP		 = 0x5002,
130 	MLX5_REG_PCAM		 = 0x507f,
131 	MLX5_REG_NODE_DESC	 = 0x6001,
132 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
133 	MLX5_REG_MCIA		 = 0x9014,
134 	MLX5_REG_MLCR		 = 0x902b,
135 	MLX5_REG_MPCNT		 = 0x9051,
136 	MLX5_REG_MTPPS		 = 0x9053,
137 	MLX5_REG_MTPPSE		 = 0x9054,
138 	MLX5_REG_MCQI		 = 0x9061,
139 	MLX5_REG_MCC		 = 0x9062,
140 	MLX5_REG_MCDA		 = 0x9063,
141 	MLX5_REG_MCAM		 = 0x907f,
142 };
143 
144 enum mlx5_dcbx_oper_mode {
145 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
146 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
147 };
148 
149 enum {
150 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
151 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
152 };
153 
154 enum mlx5_page_fault_resume_flags {
155 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
156 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
157 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
158 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
159 };
160 
161 enum dbg_rsc_type {
162 	MLX5_DBG_RSC_QP,
163 	MLX5_DBG_RSC_EQ,
164 	MLX5_DBG_RSC_CQ,
165 };
166 
167 enum port_state_policy {
168 	MLX5_POLICY_DOWN	= 0,
169 	MLX5_POLICY_UP		= 1,
170 	MLX5_POLICY_FOLLOW	= 2,
171 	MLX5_POLICY_INVALID	= 0xffffffff
172 };
173 
174 struct mlx5_field_desc {
175 	struct dentry	       *dent;
176 	int			i;
177 };
178 
179 struct mlx5_rsc_debug {
180 	struct mlx5_core_dev   *dev;
181 	void		       *object;
182 	enum dbg_rsc_type	type;
183 	struct dentry	       *root;
184 	struct mlx5_field_desc	fields[0];
185 };
186 
187 enum mlx5_dev_event {
188 	MLX5_DEV_EVENT_SYS_ERROR,
189 	MLX5_DEV_EVENT_PORT_UP,
190 	MLX5_DEV_EVENT_PORT_DOWN,
191 	MLX5_DEV_EVENT_PORT_INITIALIZED,
192 	MLX5_DEV_EVENT_LID_CHANGE,
193 	MLX5_DEV_EVENT_PKEY_CHANGE,
194 	MLX5_DEV_EVENT_GUID_CHANGE,
195 	MLX5_DEV_EVENT_CLIENT_REREG,
196 	MLX5_DEV_EVENT_PPS,
197 	MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
198 };
199 
200 enum mlx5_port_status {
201 	MLX5_PORT_UP        = 1,
202 	MLX5_PORT_DOWN      = 2,
203 };
204 
205 enum mlx5_eq_type {
206 	MLX5_EQ_TYPE_COMP,
207 	MLX5_EQ_TYPE_ASYNC,
208 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
209 	MLX5_EQ_TYPE_PF,
210 #endif
211 };
212 
213 struct mlx5_bfreg_info {
214 	u32		       *sys_pages;
215 	int			num_low_latency_bfregs;
216 	unsigned int	       *count;
217 
218 	/*
219 	 * protect bfreg allocation data structs
220 	 */
221 	struct mutex		lock;
222 	u32			ver;
223 	bool			lib_uar_4k;
224 	u32			num_sys_pages;
225 };
226 
227 struct mlx5_cmd_first {
228 	__be32		data[4];
229 };
230 
231 struct mlx5_cmd_msg {
232 	struct list_head		list;
233 	struct cmd_msg_cache	       *parent;
234 	u32				len;
235 	struct mlx5_cmd_first		first;
236 	struct mlx5_cmd_mailbox	       *next;
237 };
238 
239 struct mlx5_cmd_debug {
240 	struct dentry	       *dbg_root;
241 	struct dentry	       *dbg_in;
242 	struct dentry	       *dbg_out;
243 	struct dentry	       *dbg_outlen;
244 	struct dentry	       *dbg_status;
245 	struct dentry	       *dbg_run;
246 	void		       *in_msg;
247 	void		       *out_msg;
248 	u8			status;
249 	u16			inlen;
250 	u16			outlen;
251 };
252 
253 struct cmd_msg_cache {
254 	/* protect block chain allocations
255 	 */
256 	spinlock_t		lock;
257 	struct list_head	head;
258 	unsigned int		max_inbox_size;
259 	unsigned int		num_ent;
260 };
261 
262 enum {
263 	MLX5_NUM_COMMAND_CACHES = 5,
264 };
265 
266 struct mlx5_cmd_stats {
267 	u64		sum;
268 	u64		n;
269 	struct dentry  *root;
270 	struct dentry  *avg;
271 	struct dentry  *count;
272 	/* protect command average calculations */
273 	spinlock_t	lock;
274 };
275 
276 struct mlx5_cmd {
277 	void	       *cmd_alloc_buf;
278 	dma_addr_t	alloc_dma;
279 	int		alloc_size;
280 	void	       *cmd_buf;
281 	dma_addr_t	dma;
282 	u16		cmdif_rev;
283 	u8		log_sz;
284 	u8		log_stride;
285 	int		max_reg_cmds;
286 	int		events;
287 	u32 __iomem    *vector;
288 
289 	/* protect command queue allocations
290 	 */
291 	spinlock_t	alloc_lock;
292 
293 	/* protect token allocations
294 	 */
295 	spinlock_t	token_lock;
296 	u8		token;
297 	unsigned long	bitmask;
298 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
299 	struct workqueue_struct *wq;
300 	struct semaphore sem;
301 	struct semaphore pages_sem;
302 	int	mode;
303 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
304 	struct dma_pool *pool;
305 	struct mlx5_cmd_debug dbg;
306 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
307 	int checksum_disabled;
308 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
309 };
310 
311 struct mlx5_port_caps {
312 	int	gid_table_len;
313 	int	pkey_table_len;
314 	u8	ext_port_cap;
315 	bool	has_smi;
316 };
317 
318 struct mlx5_cmd_mailbox {
319 	void	       *buf;
320 	dma_addr_t	dma;
321 	struct mlx5_cmd_mailbox *next;
322 };
323 
324 struct mlx5_buf_list {
325 	void		       *buf;
326 	dma_addr_t		map;
327 };
328 
329 struct mlx5_buf {
330 	struct mlx5_buf_list	direct;
331 	int			npages;
332 	int			size;
333 	u8			page_shift;
334 };
335 
336 struct mlx5_frag_buf {
337 	struct mlx5_buf_list	*frags;
338 	int			npages;
339 	int			size;
340 	u8			page_shift;
341 };
342 
343 struct mlx5_eq_tasklet {
344 	struct list_head list;
345 	struct list_head process_list;
346 	struct tasklet_struct task;
347 	/* lock on completion tasklet list */
348 	spinlock_t lock;
349 };
350 
351 struct mlx5_eq_pagefault {
352 	struct work_struct       work;
353 	/* Pagefaults lock */
354 	spinlock_t		 lock;
355 	struct workqueue_struct *wq;
356 	mempool_t		*pool;
357 };
358 
359 struct mlx5_eq {
360 	struct mlx5_core_dev   *dev;
361 	__be32 __iomem	       *doorbell;
362 	u32			cons_index;
363 	struct mlx5_buf		buf;
364 	int			size;
365 	unsigned int		irqn;
366 	u8			eqn;
367 	int			nent;
368 	u64			mask;
369 	struct list_head	list;
370 	int			index;
371 	struct mlx5_rsc_debug	*dbg;
372 	enum mlx5_eq_type	type;
373 	union {
374 		struct mlx5_eq_tasklet   tasklet_ctx;
375 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
376 		struct mlx5_eq_pagefault pf_ctx;
377 #endif
378 	};
379 };
380 
381 struct mlx5_core_psv {
382 	u32	psv_idx;
383 	struct psv_layout {
384 		u32	pd;
385 		u16	syndrome;
386 		u16	reserved;
387 		u16	bg;
388 		u16	app_tag;
389 		u32	ref_tag;
390 	} psv;
391 };
392 
393 struct mlx5_core_sig_ctx {
394 	struct mlx5_core_psv	psv_memory;
395 	struct mlx5_core_psv	psv_wire;
396 	struct ib_sig_err       err_item;
397 	bool			sig_status_checked;
398 	bool			sig_err_exists;
399 	u32			sigerr_count;
400 };
401 
402 enum {
403 	MLX5_MKEY_MR = 1,
404 	MLX5_MKEY_MW,
405 };
406 
407 struct mlx5_core_mkey {
408 	u64			iova;
409 	u64			size;
410 	u32			key;
411 	u32			pd;
412 	u32			type;
413 };
414 
415 #define MLX5_24BIT_MASK		((1 << 24) - 1)
416 
417 enum mlx5_res_type {
418 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
419 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
420 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
421 	MLX5_RES_SRQ	= 3,
422 	MLX5_RES_XSRQ	= 4,
423 	MLX5_RES_XRQ	= 5,
424 };
425 
426 struct mlx5_core_rsc_common {
427 	enum mlx5_res_type	res;
428 	atomic_t		refcount;
429 	struct completion	free;
430 };
431 
432 struct mlx5_core_srq {
433 	struct mlx5_core_rsc_common	common; /* must be first */
434 	u32		srqn;
435 	int		max;
436 	int		max_gs;
437 	int		max_avail_gather;
438 	int		wqe_shift;
439 	void (*event)	(struct mlx5_core_srq *, enum mlx5_event);
440 
441 	atomic_t		refcount;
442 	struct completion	free;
443 };
444 
445 struct mlx5_eq_table {
446 	void __iomem	       *update_ci;
447 	void __iomem	       *update_arm_ci;
448 	struct list_head	comp_eqs_list;
449 	struct mlx5_eq		pages_eq;
450 	struct mlx5_eq		async_eq;
451 	struct mlx5_eq		cmd_eq;
452 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
453 	struct mlx5_eq		pfault_eq;
454 #endif
455 	int			num_comp_vectors;
456 	/* protect EQs list
457 	 */
458 	spinlock_t		lock;
459 };
460 
461 struct mlx5_uars_page {
462 	void __iomem	       *map;
463 	bool			wc;
464 	u32			index;
465 	struct list_head	list;
466 	unsigned int		bfregs;
467 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
468 	unsigned long	       *fp_bitmap;
469 	unsigned int		reg_avail;
470 	unsigned int		fp_avail;
471 	struct kref		ref_count;
472 	struct mlx5_core_dev   *mdev;
473 };
474 
475 struct mlx5_bfreg_head {
476 	/* protect blue flame registers allocations */
477 	struct mutex		lock;
478 	struct list_head	list;
479 };
480 
481 struct mlx5_bfreg_data {
482 	struct mlx5_bfreg_head	reg_head;
483 	struct mlx5_bfreg_head	wc_head;
484 };
485 
486 struct mlx5_sq_bfreg {
487 	void __iomem	       *map;
488 	struct mlx5_uars_page  *up;
489 	bool			wc;
490 	u32			index;
491 	unsigned int		offset;
492 };
493 
494 struct mlx5_core_health {
495 	struct health_buffer __iomem   *health;
496 	__be32 __iomem		       *health_counter;
497 	struct timer_list		timer;
498 	u32				prev;
499 	int				miss_counter;
500 	bool				sick;
501 	/* wq spinlock to synchronize draining */
502 	spinlock_t			wq_lock;
503 	struct workqueue_struct	       *wq;
504 	unsigned long			flags;
505 	struct work_struct		work;
506 	struct delayed_work		recover_work;
507 };
508 
509 struct mlx5_cq_table {
510 	/* protect radix tree
511 	 */
512 	spinlock_t		lock;
513 	struct radix_tree_root	tree;
514 };
515 
516 struct mlx5_qp_table {
517 	/* protect radix tree
518 	 */
519 	spinlock_t		lock;
520 	struct radix_tree_root	tree;
521 };
522 
523 struct mlx5_srq_table {
524 	/* protect radix tree
525 	 */
526 	spinlock_t		lock;
527 	struct radix_tree_root	tree;
528 };
529 
530 struct mlx5_mkey_table {
531 	/* protect radix tree
532 	 */
533 	rwlock_t		lock;
534 	struct radix_tree_root	tree;
535 };
536 
537 struct mlx5_vf_context {
538 	int	enabled;
539 	u64	port_guid;
540 	u64	node_guid;
541 	enum port_state_policy	policy;
542 };
543 
544 struct mlx5_core_sriov {
545 	struct mlx5_vf_context	*vfs_ctx;
546 	int			num_vfs;
547 	int			enabled_vfs;
548 };
549 
550 struct mlx5_irq_info {
551 	char name[MLX5_MAX_IRQ_NAME];
552 };
553 
554 struct mlx5_fc_stats {
555 	struct rb_root counters;
556 	struct list_head addlist;
557 	/* protect addlist add/splice operations */
558 	spinlock_t addlist_lock;
559 
560 	struct workqueue_struct *wq;
561 	struct delayed_work work;
562 	unsigned long next_query;
563 	unsigned long sampling_interval; /* jiffies */
564 };
565 
566 struct mlx5_mpfs;
567 struct mlx5_eswitch;
568 struct mlx5_lag;
569 struct mlx5_pagefault;
570 
571 struct mlx5_rl_entry {
572 	u32                     rate;
573 	u16                     index;
574 	u16                     refcount;
575 };
576 
577 struct mlx5_rl_table {
578 	/* protect rate limit table */
579 	struct mutex            rl_lock;
580 	u16                     max_size;
581 	u32                     max_rate;
582 	u32                     min_rate;
583 	struct mlx5_rl_entry   *rl_entry;
584 };
585 
586 enum port_module_event_status_type {
587 	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
588 	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
589 	MLX5_MODULE_STATUS_ERROR     = 0x3,
590 	MLX5_MODULE_STATUS_NUM       = 0x3,
591 };
592 
593 enum  port_module_event_error_type {
594 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
595 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
596 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
597 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
598 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
599 	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
600 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
601 	MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
602 	MLX5_MODULE_EVENT_ERROR_UNKNOWN,
603 	MLX5_MODULE_EVENT_ERROR_NUM,
604 };
605 
606 struct mlx5_port_module_event_stats {
607 	u64 status_counters[MLX5_MODULE_STATUS_NUM];
608 	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
609 };
610 
611 struct mlx5_priv {
612 	char			name[MLX5_MAX_NAME_LEN];
613 	struct mlx5_eq_table	eq_table;
614 	struct mlx5_irq_info	*irq_info;
615 
616 	/* pages stuff */
617 	struct workqueue_struct *pg_wq;
618 	struct rb_root		page_root;
619 	int			fw_pages;
620 	atomic_t		reg_pages;
621 	struct list_head	free_list;
622 	int			vfs_pages;
623 
624 	struct mlx5_core_health health;
625 
626 	struct mlx5_srq_table	srq_table;
627 
628 	/* start: qp staff */
629 	struct mlx5_qp_table	qp_table;
630 	struct dentry	       *qp_debugfs;
631 	struct dentry	       *eq_debugfs;
632 	struct dentry	       *cq_debugfs;
633 	struct dentry	       *cmdif_debugfs;
634 	/* end: qp staff */
635 
636 	/* start: cq staff */
637 	struct mlx5_cq_table	cq_table;
638 	/* end: cq staff */
639 
640 	/* start: mkey staff */
641 	struct mlx5_mkey_table	mkey_table;
642 	/* end: mkey staff */
643 
644 	/* start: alloc staff */
645 	/* protect buffer alocation according to numa node */
646 	struct mutex            alloc_mutex;
647 	int                     numa_node;
648 
649 	struct mutex            pgdir_mutex;
650 	struct list_head        pgdir_list;
651 	/* end: alloc staff */
652 	struct dentry	       *dbg_root;
653 
654 	/* protect mkey key part */
655 	spinlock_t		mkey_lock;
656 	u8			mkey_key;
657 
658 	struct list_head        dev_list;
659 	struct list_head        ctx_list;
660 	spinlock_t              ctx_lock;
661 
662 	struct list_head	waiting_events_list;
663 	bool			is_accum_events;
664 
665 	struct mlx5_flow_steering *steering;
666 	struct mlx5_mpfs        *mpfs;
667 	struct mlx5_eswitch     *eswitch;
668 	struct mlx5_core_sriov	sriov;
669 	struct mlx5_lag		*lag;
670 	unsigned long		pci_dev_data;
671 	struct mlx5_fc_stats		fc_stats;
672 	struct mlx5_rl_table            rl_table;
673 
674 	struct mlx5_port_module_event_stats  pme_stats;
675 
676 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
677 	void		      (*pfault)(struct mlx5_core_dev *dev,
678 					void *context,
679 					struct mlx5_pagefault *pfault);
680 	void		       *pfault_ctx;
681 	struct srcu_struct      pfault_srcu;
682 #endif
683 	struct mlx5_bfreg_data		bfregs;
684 	struct mlx5_uars_page	       *uar;
685 };
686 
687 enum mlx5_device_state {
688 	MLX5_DEVICE_STATE_UP,
689 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
690 };
691 
692 enum mlx5_interface_state {
693 	MLX5_INTERFACE_STATE_UP = BIT(0),
694 };
695 
696 enum mlx5_pci_status {
697 	MLX5_PCI_STATUS_DISABLED,
698 	MLX5_PCI_STATUS_ENABLED,
699 };
700 
701 enum mlx5_pagefault_type_flags {
702 	MLX5_PFAULT_REQUESTOR = 1 << 0,
703 	MLX5_PFAULT_WRITE     = 1 << 1,
704 	MLX5_PFAULT_RDMA      = 1 << 2,
705 };
706 
707 /* Contains the details of a pagefault. */
708 struct mlx5_pagefault {
709 	u32			bytes_committed;
710 	u32			token;
711 	u8			event_subtype;
712 	u8			type;
713 	union {
714 		/* Initiator or send message responder pagefault details. */
715 		struct {
716 			/* Received packet size, only valid for responders. */
717 			u32	packet_size;
718 			/*
719 			 * Number of resource holding WQE, depends on type.
720 			 */
721 			u32	wq_num;
722 			/*
723 			 * WQE index. Refers to either the send queue or
724 			 * receive queue, according to event_subtype.
725 			 */
726 			u16	wqe_index;
727 		} wqe;
728 		/* RDMA responder pagefault details */
729 		struct {
730 			u32	r_key;
731 			/*
732 			 * Received packet size, minimal size page fault
733 			 * resolution required for forward progress.
734 			 */
735 			u32	packet_size;
736 			u32	rdma_op_len;
737 			u64	rdma_va;
738 		} rdma;
739 	};
740 
741 	struct mlx5_eq	       *eq;
742 	struct work_struct	work;
743 };
744 
745 struct mlx5_td {
746 	struct list_head tirs_list;
747 	u32              tdn;
748 };
749 
750 struct mlx5e_resources {
751 	u32                        pdn;
752 	struct mlx5_td             td;
753 	struct mlx5_core_mkey      mkey;
754 	struct mlx5_sq_bfreg       bfreg;
755 };
756 
757 #define MLX5_MAX_RESERVED_GIDS 8
758 
759 struct mlx5_rsvd_gids {
760 	unsigned int start;
761 	unsigned int count;
762 	struct ida ida;
763 };
764 
765 #define MAX_PIN_NUM	8
766 struct mlx5_pps {
767 	u8                         pin_caps[MAX_PIN_NUM];
768 	struct work_struct         out_work;
769 	u64                        start[MAX_PIN_NUM];
770 	u8                         enabled;
771 };
772 
773 struct mlx5_clock {
774 	rwlock_t                   lock;
775 	struct cyclecounter        cycles;
776 	struct timecounter         tc;
777 	struct hwtstamp_config     hwtstamp_config;
778 	u32                        nominal_c_mult;
779 	unsigned long              overflow_period;
780 	struct delayed_work        overflow_work;
781 	struct ptp_clock          *ptp;
782 	struct ptp_clock_info      ptp_info;
783 	struct mlx5_pps            pps_info;
784 };
785 
786 struct mlx5_core_dev {
787 	struct pci_dev	       *pdev;
788 	/* sync pci state */
789 	struct mutex		pci_status_mutex;
790 	enum mlx5_pci_status	pci_status;
791 	u8			rev_id;
792 	char			board_id[MLX5_BOARD_ID_LEN];
793 	struct mlx5_cmd		cmd;
794 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
795 	struct {
796 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
797 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
798 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
799 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
800 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
801 	} caps;
802 	phys_addr_t		iseg_base;
803 	struct mlx5_init_seg __iomem *iseg;
804 	enum mlx5_device_state	state;
805 	/* sync interface state */
806 	struct mutex		intf_state_mutex;
807 	unsigned long		intf_state;
808 	void			(*event) (struct mlx5_core_dev *dev,
809 					  enum mlx5_dev_event event,
810 					  unsigned long param);
811 	struct mlx5_priv	priv;
812 	struct mlx5_profile	*profile;
813 	atomic_t		num_qps;
814 	u32			issi;
815 	struct mlx5e_resources  mlx5e_res;
816 	struct {
817 		struct mlx5_rsvd_gids	reserved_gids;
818 		atomic_t                roce_en;
819 	} roce;
820 #ifdef CONFIG_MLX5_FPGA
821 	struct mlx5_fpga_device *fpga;
822 #endif
823 #ifdef CONFIG_RFS_ACCEL
824 	struct cpu_rmap         *rmap;
825 #endif
826 	struct mlx5_clock        clock;
827 };
828 
829 struct mlx5_db {
830 	__be32			*db;
831 	union {
832 		struct mlx5_db_pgdir		*pgdir;
833 		struct mlx5_ib_user_db_page	*user_page;
834 	}			u;
835 	dma_addr_t		dma;
836 	int			index;
837 };
838 
839 enum {
840 	MLX5_COMP_EQ_SIZE = 1024,
841 };
842 
843 enum {
844 	MLX5_PTYS_IB = 1 << 0,
845 	MLX5_PTYS_EN = 1 << 2,
846 };
847 
848 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
849 
850 enum {
851 	MLX5_CMD_ENT_STATE_PENDING_COMP,
852 };
853 
854 struct mlx5_cmd_work_ent {
855 	unsigned long		state;
856 	struct mlx5_cmd_msg    *in;
857 	struct mlx5_cmd_msg    *out;
858 	void		       *uout;
859 	int			uout_size;
860 	mlx5_cmd_cbk_t		callback;
861 	struct delayed_work	cb_timeout_work;
862 	void		       *context;
863 	int			idx;
864 	struct completion	done;
865 	struct mlx5_cmd        *cmd;
866 	struct work_struct	work;
867 	struct mlx5_cmd_layout *lay;
868 	int			ret;
869 	int			page_queue;
870 	u8			status;
871 	u8			token;
872 	u64			ts1;
873 	u64			ts2;
874 	u16			op;
875 	bool			polling;
876 };
877 
878 struct mlx5_pas {
879 	u64	pa;
880 	u8	log_sz;
881 };
882 
883 enum phy_port_state {
884 	MLX5_AAA_111
885 };
886 
887 struct mlx5_hca_vport_context {
888 	u32			field_select;
889 	bool			sm_virt_aware;
890 	bool			has_smi;
891 	bool			has_raw;
892 	enum port_state_policy	policy;
893 	enum phy_port_state	phys_state;
894 	enum ib_port_state	vport_state;
895 	u8			port_physical_state;
896 	u64			sys_image_guid;
897 	u64			port_guid;
898 	u64			node_guid;
899 	u32			cap_mask1;
900 	u32			cap_mask1_perm;
901 	u32			cap_mask2;
902 	u32			cap_mask2_perm;
903 	u16			lid;
904 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
905 	u8			lmc;
906 	u8			subnet_timeout;
907 	u16			sm_lid;
908 	u8			sm_sl;
909 	u16			qkey_violation_counter;
910 	u16			pkey_violation_counter;
911 	bool			grh_required;
912 };
913 
914 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
915 {
916 		return buf->direct.buf + offset;
917 }
918 
919 #define STRUCT_FIELD(header, field) \
920 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
921 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
922 
923 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
924 {
925 	return pci_get_drvdata(pdev);
926 }
927 
928 extern struct dentry *mlx5_debugfs_root;
929 
930 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
931 {
932 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
933 }
934 
935 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
936 {
937 	return ioread32be(&dev->iseg->fw_rev) >> 16;
938 }
939 
940 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
941 {
942 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
943 }
944 
945 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
946 {
947 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
948 }
949 
950 static inline u32 mlx5_base_mkey(const u32 key)
951 {
952 	return key & 0xffffff00u;
953 }
954 
955 int mlx5_cmd_init(struct mlx5_core_dev *dev);
956 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
957 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
958 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
959 
960 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
961 		  int out_size);
962 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
963 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
964 		     void *context);
965 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
966 			  void *out, int out_size);
967 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
968 
969 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
970 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
971 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
972 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
973 int mlx5_health_init(struct mlx5_core_dev *dev);
974 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
975 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
976 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
977 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
978 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
979 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
980 			struct mlx5_buf *buf, int node);
981 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
982 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
983 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
984 			     struct mlx5_frag_buf *buf, int node);
985 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
986 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
987 						      gfp_t flags, int npages);
988 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
989 				 struct mlx5_cmd_mailbox *head);
990 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
991 			 struct mlx5_srq_attr *in);
992 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
993 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
994 			struct mlx5_srq_attr *out);
995 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
996 		      u16 lwm, int is_srq);
997 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
998 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
999 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1000 			     struct mlx5_core_mkey *mkey,
1001 			     u32 *in, int inlen,
1002 			     u32 *out, int outlen,
1003 			     mlx5_cmd_cbk_t callback, void *context);
1004 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1005 			  struct mlx5_core_mkey *mkey,
1006 			  u32 *in, int inlen);
1007 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1008 			   struct mlx5_core_mkey *mkey);
1009 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1010 			 u32 *out, int outlen);
1011 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
1012 			     u32 *mkey);
1013 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1014 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1015 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1016 		      u16 opmod, u8 port);
1017 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1018 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1019 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1020 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1021 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1022 				 s32 npages);
1023 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1024 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1025 void mlx5_register_debugfs(void);
1026 void mlx5_unregister_debugfs(void);
1027 int mlx5_eq_init(struct mlx5_core_dev *dev);
1028 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1029 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1030 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1031 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1032 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1033 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1034 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1035 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
1036 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1037 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1038 		       int nent, u64 mask, const char *name,
1039 		       enum mlx5_eq_type type);
1040 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1041 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1042 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1043 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1044 		    unsigned int *irqn);
1045 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1046 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1047 
1048 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1049 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1050 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1051 			 int size_in, void *data_out, int size_out,
1052 			 u16 reg_num, int arg, int write);
1053 
1054 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1055 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1056 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1057 		       u32 *out, int outlen);
1058 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1059 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1060 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1061 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1062 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1063 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1064 		       int node);
1065 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1066 
1067 const char *mlx5_command_str(int command);
1068 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1069 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1070 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1071 			 int npsvs, u32 *sig_index);
1072 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1073 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1074 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1075 			struct mlx5_odp_caps *odp_caps);
1076 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1077 			     u8 port_num, void *out, size_t sz);
1078 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1079 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1080 				u32 wq_num, u8 type, int error);
1081 #endif
1082 
1083 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1084 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1085 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1086 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1087 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1088 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1089 		     bool map_wc, bool fast_path);
1090 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1091 
1092 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1093 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1094 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1095 			   const u8 *mac, bool vlan, u16 vlan_id);
1096 
1097 static inline int fw_initializing(struct mlx5_core_dev *dev)
1098 {
1099 	return ioread32be(&dev->iseg->initializing) >> 31;
1100 }
1101 
1102 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1103 {
1104 	return mkey >> 8;
1105 }
1106 
1107 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1108 {
1109 	return mkey_idx << 8;
1110 }
1111 
1112 static inline u8 mlx5_mkey_variant(u32 mkey)
1113 {
1114 	return mkey & 0xff;
1115 }
1116 
1117 enum {
1118 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1119 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1120 };
1121 
1122 enum {
1123 	MR_CACHE_LAST_STD_ENTRY = 20,
1124 	MLX5_IMR_MTT_CACHE_ENTRY,
1125 	MLX5_IMR_KSM_CACHE_ENTRY,
1126 	MAX_MR_CACHE_ENTRIES
1127 };
1128 
1129 enum {
1130 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1131 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1132 };
1133 
1134 struct mlx5_interface {
1135 	void *			(*add)(struct mlx5_core_dev *dev);
1136 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1137 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1138 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1139 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1140 					 enum mlx5_dev_event event, unsigned long param);
1141 	void			(*pfault)(struct mlx5_core_dev *dev,
1142 					  void *context,
1143 					  struct mlx5_pagefault *pfault);
1144 	void *                  (*get_dev)(void *context);
1145 	int			protocol;
1146 	struct list_head	list;
1147 };
1148 
1149 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1150 int mlx5_register_interface(struct mlx5_interface *intf);
1151 void mlx5_unregister_interface(struct mlx5_interface *intf);
1152 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1153 
1154 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1155 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1156 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1157 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1158 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1159 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1160 
1161 #ifndef CONFIG_MLX5_CORE_IPOIB
1162 static inline
1163 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1164 					  struct ib_device *ibdev,
1165 					  const char *name,
1166 					  void (*setup)(struct net_device *))
1167 {
1168 	return ERR_PTR(-EOPNOTSUPP);
1169 }
1170 
1171 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1172 #else
1173 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1174 					  struct ib_device *ibdev,
1175 					  const char *name,
1176 					  void (*setup)(struct net_device *));
1177 void mlx5_rdma_netdev_free(struct net_device *netdev);
1178 #endif /* CONFIG_MLX5_CORE_IPOIB */
1179 
1180 struct mlx5_profile {
1181 	u64	mask;
1182 	u8	log_max_qp;
1183 	struct {
1184 		int	size;
1185 		int	limit;
1186 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1187 };
1188 
1189 enum {
1190 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1191 };
1192 
1193 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1194 {
1195 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1196 }
1197 
1198 static inline int mlx5_get_gid_table_len(u16 param)
1199 {
1200 	if (param > 4) {
1201 		pr_warn("gid table length is zero\n");
1202 		return 0;
1203 	}
1204 
1205 	return 8 * (1 << param);
1206 }
1207 
1208 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1209 {
1210 	return !!(dev->priv.rl_table.max_size);
1211 }
1212 
1213 enum {
1214 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1215 };
1216 
1217 static inline const struct cpumask *
1218 mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
1219 {
1220 	return pci_irq_get_affinity(dev->pdev, MLX5_EQ_VEC_COMP_BASE + vector);
1221 }
1222 
1223 #endif /* MLX5_DRIVER_H */
1224