1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/xarray.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 #include <linux/notifier.h> 50 #include <linux/refcount.h> 51 52 #include <linux/mlx5/device.h> 53 #include <linux/mlx5/doorbell.h> 54 #include <linux/mlx5/eq.h> 55 #include <linux/timecounter.h> 56 #include <linux/ptp_clock_kernel.h> 57 #include <net/devlink.h> 58 59 enum { 60 MLX5_BOARD_ID_LEN = 64, 61 }; 62 63 enum { 64 /* one minute for the sake of bringup. Generally, commands must always 65 * complete and we may need to increase this timeout value 66 */ 67 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 68 MLX5_CMD_WQ_MAX_NAME = 32, 69 }; 70 71 enum { 72 CMD_OWNER_SW = 0x0, 73 CMD_OWNER_HW = 0x1, 74 CMD_STATUS_SUCCESS = 0, 75 }; 76 77 enum mlx5_sqp_t { 78 MLX5_SQP_SMI = 0, 79 MLX5_SQP_GSI = 1, 80 MLX5_SQP_IEEE_1588 = 2, 81 MLX5_SQP_SNIFFER = 3, 82 MLX5_SQP_SYNC_UMR = 4, 83 }; 84 85 enum { 86 MLX5_MAX_PORTS = 2, 87 }; 88 89 enum { 90 MLX5_ATOMIC_MODE_OFFSET = 16, 91 MLX5_ATOMIC_MODE_IB_COMP = 1, 92 MLX5_ATOMIC_MODE_CX = 2, 93 MLX5_ATOMIC_MODE_8B = 3, 94 MLX5_ATOMIC_MODE_16B = 4, 95 MLX5_ATOMIC_MODE_32B = 5, 96 MLX5_ATOMIC_MODE_64B = 6, 97 MLX5_ATOMIC_MODE_128B = 7, 98 MLX5_ATOMIC_MODE_256B = 8, 99 }; 100 101 enum { 102 MLX5_REG_QPTS = 0x4002, 103 MLX5_REG_QETCR = 0x4005, 104 MLX5_REG_QTCT = 0x400a, 105 MLX5_REG_QPDPM = 0x4013, 106 MLX5_REG_QCAM = 0x4019, 107 MLX5_REG_DCBX_PARAM = 0x4020, 108 MLX5_REG_DCBX_APP = 0x4021, 109 MLX5_REG_FPGA_CAP = 0x4022, 110 MLX5_REG_FPGA_CTRL = 0x4023, 111 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 112 MLX5_REG_CORE_DUMP = 0x402e, 113 MLX5_REG_PCAP = 0x5001, 114 MLX5_REG_PMTU = 0x5003, 115 MLX5_REG_PTYS = 0x5004, 116 MLX5_REG_PAOS = 0x5006, 117 MLX5_REG_PFCC = 0x5007, 118 MLX5_REG_PPCNT = 0x5008, 119 MLX5_REG_PPTB = 0x500b, 120 MLX5_REG_PBMC = 0x500c, 121 MLX5_REG_PMAOS = 0x5012, 122 MLX5_REG_PUDE = 0x5009, 123 MLX5_REG_PMPE = 0x5010, 124 MLX5_REG_PELC = 0x500e, 125 MLX5_REG_PVLC = 0x500f, 126 MLX5_REG_PCMR = 0x5041, 127 MLX5_REG_PMLP = 0x5002, 128 MLX5_REG_PPLM = 0x5023, 129 MLX5_REG_PCAM = 0x507f, 130 MLX5_REG_NODE_DESC = 0x6001, 131 MLX5_REG_HOST_ENDIANNESS = 0x7004, 132 MLX5_REG_MCIA = 0x9014, 133 MLX5_REG_MLCR = 0x902b, 134 MLX5_REG_MTRC_CAP = 0x9040, 135 MLX5_REG_MTRC_CONF = 0x9041, 136 MLX5_REG_MTRC_STDB = 0x9042, 137 MLX5_REG_MTRC_CTRL = 0x9043, 138 MLX5_REG_MPEIN = 0x9050, 139 MLX5_REG_MPCNT = 0x9051, 140 MLX5_REG_MTPPS = 0x9053, 141 MLX5_REG_MTPPSE = 0x9054, 142 MLX5_REG_MPEGC = 0x9056, 143 MLX5_REG_MCQS = 0x9060, 144 MLX5_REG_MCQI = 0x9061, 145 MLX5_REG_MCC = 0x9062, 146 MLX5_REG_MCDA = 0x9063, 147 MLX5_REG_MCAM = 0x907f, 148 MLX5_REG_MIRC = 0x9162, 149 MLX5_REG_RESOURCE_DUMP = 0xC000, 150 }; 151 152 enum mlx5_qpts_trust_state { 153 MLX5_QPTS_TRUST_PCP = 1, 154 MLX5_QPTS_TRUST_DSCP = 2, 155 }; 156 157 enum mlx5_dcbx_oper_mode { 158 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 159 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 160 }; 161 162 enum { 163 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 164 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 165 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, 166 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, 167 }; 168 169 enum mlx5_page_fault_resume_flags { 170 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 171 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 172 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 173 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 174 }; 175 176 enum dbg_rsc_type { 177 MLX5_DBG_RSC_QP, 178 MLX5_DBG_RSC_EQ, 179 MLX5_DBG_RSC_CQ, 180 }; 181 182 enum port_state_policy { 183 MLX5_POLICY_DOWN = 0, 184 MLX5_POLICY_UP = 1, 185 MLX5_POLICY_FOLLOW = 2, 186 MLX5_POLICY_INVALID = 0xffffffff 187 }; 188 189 enum mlx5_coredev_type { 190 MLX5_COREDEV_PF, 191 MLX5_COREDEV_VF 192 }; 193 194 struct mlx5_field_desc { 195 int i; 196 }; 197 198 struct mlx5_rsc_debug { 199 struct mlx5_core_dev *dev; 200 void *object; 201 enum dbg_rsc_type type; 202 struct dentry *root; 203 struct mlx5_field_desc fields[0]; 204 }; 205 206 enum mlx5_dev_event { 207 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ 208 MLX5_DEV_EVENT_PORT_AFFINITY = 129, 209 }; 210 211 enum mlx5_port_status { 212 MLX5_PORT_UP = 1, 213 MLX5_PORT_DOWN = 2, 214 }; 215 216 struct mlx5_cmd_first { 217 __be32 data[4]; 218 }; 219 220 struct mlx5_cmd_msg { 221 struct list_head list; 222 struct cmd_msg_cache *parent; 223 u32 len; 224 struct mlx5_cmd_first first; 225 struct mlx5_cmd_mailbox *next; 226 }; 227 228 struct mlx5_cmd_debug { 229 struct dentry *dbg_root; 230 void *in_msg; 231 void *out_msg; 232 u8 status; 233 u16 inlen; 234 u16 outlen; 235 }; 236 237 struct cmd_msg_cache { 238 /* protect block chain allocations 239 */ 240 spinlock_t lock; 241 struct list_head head; 242 unsigned int max_inbox_size; 243 unsigned int num_ent; 244 }; 245 246 enum { 247 MLX5_NUM_COMMAND_CACHES = 5, 248 }; 249 250 struct mlx5_cmd_stats { 251 u64 sum; 252 u64 n; 253 struct dentry *root; 254 /* protect command average calculations */ 255 spinlock_t lock; 256 }; 257 258 struct mlx5_cmd { 259 struct mlx5_nb nb; 260 261 void *cmd_alloc_buf; 262 dma_addr_t alloc_dma; 263 int alloc_size; 264 void *cmd_buf; 265 dma_addr_t dma; 266 u16 cmdif_rev; 267 u8 log_sz; 268 u8 log_stride; 269 int max_reg_cmds; 270 int events; 271 u32 __iomem *vector; 272 273 /* protect command queue allocations 274 */ 275 spinlock_t alloc_lock; 276 277 /* protect token allocations 278 */ 279 spinlock_t token_lock; 280 u8 token; 281 unsigned long bitmask; 282 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 283 struct workqueue_struct *wq; 284 struct semaphore sem; 285 struct semaphore pages_sem; 286 int mode; 287 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 288 struct dma_pool *pool; 289 struct mlx5_cmd_debug dbg; 290 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 291 int checksum_disabled; 292 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 293 }; 294 295 struct mlx5_port_caps { 296 int gid_table_len; 297 int pkey_table_len; 298 u8 ext_port_cap; 299 bool has_smi; 300 }; 301 302 struct mlx5_cmd_mailbox { 303 void *buf; 304 dma_addr_t dma; 305 struct mlx5_cmd_mailbox *next; 306 }; 307 308 struct mlx5_buf_list { 309 void *buf; 310 dma_addr_t map; 311 }; 312 313 struct mlx5_frag_buf { 314 struct mlx5_buf_list *frags; 315 int npages; 316 int size; 317 u8 page_shift; 318 }; 319 320 struct mlx5_frag_buf_ctrl { 321 struct mlx5_buf_list *frags; 322 u32 sz_m1; 323 u16 frag_sz_m1; 324 u16 strides_offset; 325 u8 log_sz; 326 u8 log_stride; 327 u8 log_frag_strides; 328 }; 329 330 struct mlx5_core_psv { 331 u32 psv_idx; 332 struct psv_layout { 333 u32 pd; 334 u16 syndrome; 335 u16 reserved; 336 u16 bg; 337 u16 app_tag; 338 u32 ref_tag; 339 } psv; 340 }; 341 342 struct mlx5_core_sig_ctx { 343 struct mlx5_core_psv psv_memory; 344 struct mlx5_core_psv psv_wire; 345 struct ib_sig_err err_item; 346 bool sig_status_checked; 347 bool sig_err_exists; 348 u32 sigerr_count; 349 }; 350 351 enum { 352 MLX5_MKEY_MR = 1, 353 MLX5_MKEY_MW, 354 MLX5_MKEY_INDIRECT_DEVX, 355 }; 356 357 struct mlx5_core_mkey { 358 u64 iova; 359 u64 size; 360 u32 key; 361 u32 pd; 362 u32 type; 363 }; 364 365 #define MLX5_24BIT_MASK ((1 << 24) - 1) 366 367 enum mlx5_res_type { 368 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 369 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 370 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 371 MLX5_RES_SRQ = 3, 372 MLX5_RES_XSRQ = 4, 373 MLX5_RES_XRQ = 5, 374 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 375 }; 376 377 struct mlx5_core_rsc_common { 378 enum mlx5_res_type res; 379 refcount_t refcount; 380 struct completion free; 381 }; 382 383 struct mlx5_uars_page { 384 void __iomem *map; 385 bool wc; 386 u32 index; 387 struct list_head list; 388 unsigned int bfregs; 389 unsigned long *reg_bitmap; /* for non fast path bf regs */ 390 unsigned long *fp_bitmap; 391 unsigned int reg_avail; 392 unsigned int fp_avail; 393 struct kref ref_count; 394 struct mlx5_core_dev *mdev; 395 }; 396 397 struct mlx5_bfreg_head { 398 /* protect blue flame registers allocations */ 399 struct mutex lock; 400 struct list_head list; 401 }; 402 403 struct mlx5_bfreg_data { 404 struct mlx5_bfreg_head reg_head; 405 struct mlx5_bfreg_head wc_head; 406 }; 407 408 struct mlx5_sq_bfreg { 409 void __iomem *map; 410 struct mlx5_uars_page *up; 411 bool wc; 412 u32 index; 413 unsigned int offset; 414 }; 415 416 struct mlx5_core_health { 417 struct health_buffer __iomem *health; 418 __be32 __iomem *health_counter; 419 struct timer_list timer; 420 u32 prev; 421 int miss_counter; 422 u8 synd; 423 u32 fatal_error; 424 u32 crdump_size; 425 /* wq spinlock to synchronize draining */ 426 spinlock_t wq_lock; 427 struct workqueue_struct *wq; 428 unsigned long flags; 429 struct work_struct fatal_report_work; 430 struct work_struct report_work; 431 struct delayed_work recover_work; 432 struct devlink_health_reporter *fw_reporter; 433 struct devlink_health_reporter *fw_fatal_reporter; 434 }; 435 436 struct mlx5_qp_table { 437 struct notifier_block nb; 438 439 /* protect radix tree 440 */ 441 spinlock_t lock; 442 struct radix_tree_root tree; 443 }; 444 445 struct mlx5_vf_context { 446 int enabled; 447 u64 port_guid; 448 u64 node_guid; 449 /* Valid bits are used to validate administrative guid only. 450 * Enabled after ndo_set_vf_guid 451 */ 452 u8 port_guid_valid:1; 453 u8 node_guid_valid:1; 454 enum port_state_policy policy; 455 }; 456 457 struct mlx5_core_sriov { 458 struct mlx5_vf_context *vfs_ctx; 459 int num_vfs; 460 u16 max_vfs; 461 }; 462 463 struct mlx5_fc_pool { 464 struct mlx5_core_dev *dev; 465 struct mutex pool_lock; /* protects pool lists */ 466 struct list_head fully_used; 467 struct list_head partially_used; 468 struct list_head unused; 469 int available_fcs; 470 int used_fcs; 471 int threshold; 472 }; 473 474 struct mlx5_fc_stats { 475 spinlock_t counters_idr_lock; /* protects counters_idr */ 476 struct idr counters_idr; 477 struct list_head counters; 478 struct llist_head addlist; 479 struct llist_head dellist; 480 481 struct workqueue_struct *wq; 482 struct delayed_work work; 483 unsigned long next_query; 484 unsigned long sampling_interval; /* jiffies */ 485 u32 *bulk_query_out; 486 struct mlx5_fc_pool fc_pool; 487 }; 488 489 struct mlx5_events; 490 struct mlx5_mpfs; 491 struct mlx5_eswitch; 492 struct mlx5_lag; 493 struct mlx5_devcom; 494 struct mlx5_eq_table; 495 struct mlx5_irq_table; 496 497 struct mlx5_rate_limit { 498 u32 rate; 499 u32 max_burst_sz; 500 u16 typical_pkt_sz; 501 }; 502 503 struct mlx5_rl_entry { 504 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; 505 u16 index; 506 u64 refcount; 507 u16 uid; 508 u8 dedicated : 1; 509 }; 510 511 struct mlx5_rl_table { 512 /* protect rate limit table */ 513 struct mutex rl_lock; 514 u16 max_size; 515 u32 max_rate; 516 u32 min_rate; 517 struct mlx5_rl_entry *rl_entry; 518 }; 519 520 struct mlx5_core_roce { 521 struct mlx5_flow_table *ft; 522 struct mlx5_flow_group *fg; 523 struct mlx5_flow_handle *allow_rule; 524 }; 525 526 struct mlx5_priv { 527 /* IRQ table valid only for real pci devices PF or VF */ 528 struct mlx5_irq_table *irq_table; 529 struct mlx5_eq_table *eq_table; 530 531 /* pages stuff */ 532 struct mlx5_nb pg_nb; 533 struct workqueue_struct *pg_wq; 534 struct rb_root page_root; 535 int fw_pages; 536 atomic_t reg_pages; 537 struct list_head free_list; 538 int vfs_pages; 539 int peer_pf_pages; 540 541 struct mlx5_core_health health; 542 543 /* start: qp staff */ 544 struct mlx5_qp_table qp_table; 545 struct dentry *qp_debugfs; 546 struct dentry *eq_debugfs; 547 struct dentry *cq_debugfs; 548 struct dentry *cmdif_debugfs; 549 /* end: qp staff */ 550 551 /* start: alloc staff */ 552 /* protect buffer alocation according to numa node */ 553 struct mutex alloc_mutex; 554 int numa_node; 555 556 struct mutex pgdir_mutex; 557 struct list_head pgdir_list; 558 /* end: alloc staff */ 559 struct dentry *dbg_root; 560 561 struct list_head dev_list; 562 struct list_head ctx_list; 563 spinlock_t ctx_lock; 564 struct mlx5_events *events; 565 566 struct mlx5_flow_steering *steering; 567 struct mlx5_mpfs *mpfs; 568 struct mlx5_eswitch *eswitch; 569 struct mlx5_core_sriov sriov; 570 struct mlx5_lag *lag; 571 struct mlx5_devcom *devcom; 572 struct mlx5_core_roce roce; 573 struct mlx5_fc_stats fc_stats; 574 struct mlx5_rl_table rl_table; 575 576 struct mlx5_bfreg_data bfregs; 577 struct mlx5_uars_page *uar; 578 }; 579 580 enum mlx5_device_state { 581 MLX5_DEVICE_STATE_UNINITIALIZED, 582 MLX5_DEVICE_STATE_UP, 583 MLX5_DEVICE_STATE_INTERNAL_ERROR, 584 }; 585 586 enum mlx5_interface_state { 587 MLX5_INTERFACE_STATE_UP = BIT(0), 588 }; 589 590 enum mlx5_pci_status { 591 MLX5_PCI_STATUS_DISABLED, 592 MLX5_PCI_STATUS_ENABLED, 593 }; 594 595 enum mlx5_pagefault_type_flags { 596 MLX5_PFAULT_REQUESTOR = 1 << 0, 597 MLX5_PFAULT_WRITE = 1 << 1, 598 MLX5_PFAULT_RDMA = 1 << 2, 599 }; 600 601 struct mlx5_td { 602 /* protects tirs list changes while tirs refresh */ 603 struct mutex list_lock; 604 struct list_head tirs_list; 605 u32 tdn; 606 }; 607 608 struct mlx5e_resources { 609 u32 pdn; 610 struct mlx5_td td; 611 struct mlx5_core_mkey mkey; 612 struct mlx5_sq_bfreg bfreg; 613 }; 614 615 enum mlx5_sw_icm_type { 616 MLX5_SW_ICM_TYPE_STEERING, 617 MLX5_SW_ICM_TYPE_HEADER_MODIFY, 618 }; 619 620 #define MLX5_MAX_RESERVED_GIDS 8 621 622 struct mlx5_rsvd_gids { 623 unsigned int start; 624 unsigned int count; 625 struct ida ida; 626 }; 627 628 #define MAX_PIN_NUM 8 629 struct mlx5_pps { 630 u8 pin_caps[MAX_PIN_NUM]; 631 struct work_struct out_work; 632 u64 start[MAX_PIN_NUM]; 633 u8 enabled; 634 }; 635 636 struct mlx5_clock { 637 struct mlx5_core_dev *mdev; 638 struct mlx5_nb pps_nb; 639 seqlock_t lock; 640 struct cyclecounter cycles; 641 struct timecounter tc; 642 struct hwtstamp_config hwtstamp_config; 643 u32 nominal_c_mult; 644 unsigned long overflow_period; 645 struct delayed_work overflow_work; 646 struct ptp_clock *ptp; 647 struct ptp_clock_info ptp_info; 648 struct mlx5_pps pps_info; 649 }; 650 651 struct mlx5_dm; 652 struct mlx5_fw_tracer; 653 struct mlx5_vxlan; 654 struct mlx5_geneve; 655 struct mlx5_hv_vhca; 656 657 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) 658 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) 659 660 struct mlx5_core_dev { 661 struct device *device; 662 enum mlx5_coredev_type coredev_type; 663 struct pci_dev *pdev; 664 /* sync pci state */ 665 struct mutex pci_status_mutex; 666 enum mlx5_pci_status pci_status; 667 u8 rev_id; 668 char board_id[MLX5_BOARD_ID_LEN]; 669 struct mlx5_cmd cmd; 670 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 671 struct { 672 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 673 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 674 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 675 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; 676 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 677 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 678 u8 embedded_cpu; 679 } caps; 680 u64 sys_image_guid; 681 phys_addr_t iseg_base; 682 struct mlx5_init_seg __iomem *iseg; 683 phys_addr_t bar_addr; 684 enum mlx5_device_state state; 685 /* sync interface state */ 686 struct mutex intf_state_mutex; 687 unsigned long intf_state; 688 struct mlx5_priv priv; 689 struct mlx5_profile *profile; 690 atomic_t num_qps; 691 u32 issi; 692 struct mlx5e_resources mlx5e_res; 693 struct mlx5_dm *dm; 694 struct mlx5_vxlan *vxlan; 695 struct mlx5_geneve *geneve; 696 struct { 697 struct mlx5_rsvd_gids reserved_gids; 698 u32 roce_en; 699 } roce; 700 #ifdef CONFIG_MLX5_FPGA 701 struct mlx5_fpga_device *fpga; 702 #endif 703 struct mlx5_clock clock; 704 struct mlx5_ib_clock_info *clock_info; 705 struct mlx5_fw_tracer *tracer; 706 struct mlx5_rsc_dump *rsc_dump; 707 u32 vsc_addr; 708 struct mlx5_hv_vhca *hv_vhca; 709 }; 710 711 struct mlx5_db { 712 __be32 *db; 713 union { 714 struct mlx5_db_pgdir *pgdir; 715 struct mlx5_ib_user_db_page *user_page; 716 } u; 717 dma_addr_t dma; 718 int index; 719 }; 720 721 enum { 722 MLX5_COMP_EQ_SIZE = 1024, 723 }; 724 725 enum { 726 MLX5_PTYS_IB = 1 << 0, 727 MLX5_PTYS_EN = 1 << 2, 728 }; 729 730 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 731 732 enum { 733 MLX5_CMD_ENT_STATE_PENDING_COMP, 734 }; 735 736 struct mlx5_cmd_work_ent { 737 unsigned long state; 738 struct mlx5_cmd_msg *in; 739 struct mlx5_cmd_msg *out; 740 void *uout; 741 int uout_size; 742 mlx5_cmd_cbk_t callback; 743 struct delayed_work cb_timeout_work; 744 void *context; 745 int idx; 746 struct completion done; 747 struct mlx5_cmd *cmd; 748 struct work_struct work; 749 struct mlx5_cmd_layout *lay; 750 int ret; 751 int page_queue; 752 u8 status; 753 u8 token; 754 u64 ts1; 755 u64 ts2; 756 u16 op; 757 bool polling; 758 }; 759 760 struct mlx5_pas { 761 u64 pa; 762 u8 log_sz; 763 }; 764 765 enum phy_port_state { 766 MLX5_AAA_111 767 }; 768 769 struct mlx5_hca_vport_context { 770 u32 field_select; 771 bool sm_virt_aware; 772 bool has_smi; 773 bool has_raw; 774 enum port_state_policy policy; 775 enum phy_port_state phys_state; 776 enum ib_port_state vport_state; 777 u8 port_physical_state; 778 u64 sys_image_guid; 779 u64 port_guid; 780 u64 node_guid; 781 u32 cap_mask1; 782 u32 cap_mask1_perm; 783 u16 cap_mask2; 784 u16 cap_mask2_perm; 785 u16 lid; 786 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 787 u8 lmc; 788 u8 subnet_timeout; 789 u16 sm_lid; 790 u8 sm_sl; 791 u16 qkey_violation_counter; 792 u16 pkey_violation_counter; 793 bool grh_required; 794 }; 795 796 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 797 { 798 return buf->frags->buf + offset; 799 } 800 801 #define STRUCT_FIELD(header, field) \ 802 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 803 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 804 805 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 806 { 807 return pci_get_drvdata(pdev); 808 } 809 810 extern struct dentry *mlx5_debugfs_root; 811 812 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 813 { 814 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 815 } 816 817 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 818 { 819 return ioread32be(&dev->iseg->fw_rev) >> 16; 820 } 821 822 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 823 { 824 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 825 } 826 827 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 828 { 829 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 830 } 831 832 static inline u32 mlx5_base_mkey(const u32 key) 833 { 834 return key & 0xffffff00u; 835 } 836 837 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 838 u8 log_stride, u8 log_sz, 839 u16 strides_offset, 840 struct mlx5_frag_buf_ctrl *fbc) 841 { 842 fbc->frags = frags; 843 fbc->log_stride = log_stride; 844 fbc->log_sz = log_sz; 845 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 846 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 847 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 848 fbc->strides_offset = strides_offset; 849 } 850 851 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 852 u8 log_stride, u8 log_sz, 853 struct mlx5_frag_buf_ctrl *fbc) 854 { 855 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 856 } 857 858 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 859 u32 ix) 860 { 861 unsigned int frag; 862 863 ix += fbc->strides_offset; 864 frag = ix >> fbc->log_frag_strides; 865 866 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 867 } 868 869 static inline u32 870 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 871 { 872 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 873 874 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 875 } 876 877 int mlx5_cmd_init(struct mlx5_core_dev *dev); 878 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 879 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 880 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 881 882 struct mlx5_async_ctx { 883 struct mlx5_core_dev *dev; 884 atomic_t num_inflight; 885 struct wait_queue_head wait; 886 }; 887 888 struct mlx5_async_work; 889 890 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 891 892 struct mlx5_async_work { 893 struct mlx5_async_ctx *ctx; 894 mlx5_async_cbk_t user_callback; 895 }; 896 897 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 898 struct mlx5_async_ctx *ctx); 899 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 900 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 901 void *out, int out_size, mlx5_async_cbk_t callback, 902 struct mlx5_async_work *work); 903 904 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 905 int out_size); 906 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 907 void *out, int out_size); 908 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 909 910 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 911 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 912 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 913 void mlx5_health_flush(struct mlx5_core_dev *dev); 914 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 915 int mlx5_health_init(struct mlx5_core_dev *dev); 916 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 917 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 918 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 919 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 920 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 921 int size, struct mlx5_frag_buf *buf); 922 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 923 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 924 struct mlx5_frag_buf *buf, int node); 925 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 926 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 927 gfp_t flags, int npages); 928 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 929 struct mlx5_cmd_mailbox *head); 930 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 931 struct mlx5_core_mkey *mkey, 932 u32 *in, int inlen); 933 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 934 struct mlx5_core_mkey *mkey); 935 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 936 u32 *out, int outlen); 937 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 938 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 939 int mlx5_pagealloc_init(struct mlx5_core_dev *dev); 940 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 941 void mlx5_pagealloc_start(struct mlx5_core_dev *dev); 942 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 943 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 944 s32 npages, bool ec_function); 945 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 946 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 947 void mlx5_register_debugfs(void); 948 void mlx5_unregister_debugfs(void); 949 950 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 951 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 952 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 953 unsigned int *irqn); 954 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 955 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 956 957 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 958 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 959 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 960 int size_in, void *data_out, int size_out, 961 u16 reg_num, int arg, int write); 962 963 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 964 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 965 int node); 966 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 967 968 const char *mlx5_command_str(int command); 969 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 970 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 971 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 972 int npsvs, u32 *sig_index); 973 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 974 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 975 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 976 struct mlx5_odp_caps *odp_caps); 977 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 978 u8 port_num, void *out, size_t sz); 979 980 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 981 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 982 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 983 struct mlx5_rate_limit *rl); 984 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 985 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 986 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, 987 bool dedicated_entry, u16 *index); 988 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); 989 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 990 struct mlx5_rate_limit *rl_1); 991 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 992 bool map_wc, bool fast_path); 993 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 994 995 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); 996 struct cpumask * 997 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); 998 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 999 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1000 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1001 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 1002 1003 static inline int fw_initializing(struct mlx5_core_dev *dev) 1004 { 1005 return ioread32be(&dev->iseg->initializing) >> 31; 1006 } 1007 1008 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1009 { 1010 return mkey >> 8; 1011 } 1012 1013 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1014 { 1015 return mkey_idx << 8; 1016 } 1017 1018 static inline u8 mlx5_mkey_variant(u32 mkey) 1019 { 1020 return mkey & 0xff; 1021 } 1022 1023 enum { 1024 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1025 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1026 }; 1027 1028 enum { 1029 MR_CACHE_LAST_STD_ENTRY = 20, 1030 MLX5_IMR_MTT_CACHE_ENTRY, 1031 MLX5_IMR_KSM_CACHE_ENTRY, 1032 MAX_MR_CACHE_ENTRIES 1033 }; 1034 1035 enum { 1036 MLX5_INTERFACE_PROTOCOL_IB = 0, 1037 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1038 }; 1039 1040 struct mlx5_interface { 1041 void * (*add)(struct mlx5_core_dev *dev); 1042 void (*remove)(struct mlx5_core_dev *dev, void *context); 1043 int (*attach)(struct mlx5_core_dev *dev, void *context); 1044 void (*detach)(struct mlx5_core_dev *dev, void *context); 1045 int protocol; 1046 struct list_head list; 1047 }; 1048 1049 int mlx5_register_interface(struct mlx5_interface *intf); 1050 void mlx5_unregister_interface(struct mlx5_interface *intf); 1051 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); 1052 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); 1053 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); 1054 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); 1055 1056 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1057 1058 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1059 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1060 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); 1061 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); 1062 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); 1063 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1064 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1065 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1066 u64 *values, 1067 int num_counters, 1068 size_t *offsets); 1069 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1070 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1071 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, 1072 u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id); 1073 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, 1074 u64 length, u16 uid, phys_addr_t addr, u32 obj_id); 1075 1076 #ifdef CONFIG_MLX5_CORE_IPOIB 1077 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1078 struct ib_device *ibdev, 1079 const char *name, 1080 void (*setup)(struct net_device *)); 1081 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1082 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1083 struct ib_device *device, 1084 struct rdma_netdev_alloc_params *params); 1085 1086 struct mlx5_profile { 1087 u64 mask; 1088 u8 log_max_qp; 1089 struct { 1090 int size; 1091 int limit; 1092 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1093 }; 1094 1095 enum { 1096 MLX5_PCI_DEV_IS_VF = 1 << 0, 1097 }; 1098 1099 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) 1100 { 1101 return dev->coredev_type == MLX5_COREDEV_PF; 1102 } 1103 1104 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) 1105 { 1106 return dev->coredev_type == MLX5_COREDEV_VF; 1107 } 1108 1109 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) 1110 { 1111 return dev->caps.embedded_cpu; 1112 } 1113 1114 static inline bool 1115 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) 1116 { 1117 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); 1118 } 1119 1120 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) 1121 { 1122 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); 1123 } 1124 1125 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) 1126 { 1127 return dev->priv.sriov.max_vfs; 1128 } 1129 1130 static inline int mlx5_get_gid_table_len(u16 param) 1131 { 1132 if (param > 4) { 1133 pr_warn("gid table length is zero\n"); 1134 return 0; 1135 } 1136 1137 return 8 * (1 << param); 1138 } 1139 1140 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1141 { 1142 return !!(dev->priv.rl_table.max_size); 1143 } 1144 1145 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1146 { 1147 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1148 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1149 } 1150 1151 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1152 { 1153 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1154 } 1155 1156 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1157 { 1158 return mlx5_core_is_mp_slave(dev) || 1159 mlx5_core_is_mp_master(dev); 1160 } 1161 1162 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1163 { 1164 if (!mlx5_core_mp_enabled(dev)) 1165 return 1; 1166 1167 return MLX5_CAP_GEN(dev, native_port_num); 1168 } 1169 1170 enum { 1171 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1172 }; 1173 1174 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev) 1175 { 1176 struct devlink *devlink = priv_to_devlink(dev); 1177 union devlink_param_value val; 1178 1179 devlink_param_driverinit_value_get(devlink, 1180 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, 1181 &val); 1182 return val.vbool; 1183 } 1184 1185 #endif /* MLX5_DRIVER_H */ 1186