1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/irq.h> 40 #include <linux/spinlock_types.h> 41 #include <linux/semaphore.h> 42 #include <linux/slab.h> 43 #include <linux/vmalloc.h> 44 #include <linux/radix-tree.h> 45 #include <linux/workqueue.h> 46 #include <linux/mempool.h> 47 #include <linux/interrupt.h> 48 #include <linux/idr.h> 49 50 #include <linux/mlx5/device.h> 51 #include <linux/mlx5/doorbell.h> 52 #include <linux/mlx5/srq.h> 53 #include <linux/timecounter.h> 54 #include <linux/ptp_clock_kernel.h> 55 56 enum { 57 MLX5_BOARD_ID_LEN = 64, 58 MLX5_MAX_NAME_LEN = 16, 59 }; 60 61 enum { 62 /* one minute for the sake of bringup. Generally, commands must always 63 * complete and we may need to increase this timeout value 64 */ 65 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 66 MLX5_CMD_WQ_MAX_NAME = 32, 67 }; 68 69 enum { 70 CMD_OWNER_SW = 0x0, 71 CMD_OWNER_HW = 0x1, 72 CMD_STATUS_SUCCESS = 0, 73 }; 74 75 enum mlx5_sqp_t { 76 MLX5_SQP_SMI = 0, 77 MLX5_SQP_GSI = 1, 78 MLX5_SQP_IEEE_1588 = 2, 79 MLX5_SQP_SNIFFER = 3, 80 MLX5_SQP_SYNC_UMR = 4, 81 }; 82 83 enum { 84 MLX5_MAX_PORTS = 2, 85 }; 86 87 enum { 88 MLX5_EQ_VEC_PAGES = 0, 89 MLX5_EQ_VEC_CMD = 1, 90 MLX5_EQ_VEC_ASYNC = 2, 91 MLX5_EQ_VEC_PFAULT = 3, 92 MLX5_EQ_VEC_COMP_BASE, 93 }; 94 95 enum { 96 MLX5_MAX_IRQ_NAME = 32 97 }; 98 99 enum { 100 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 101 MLX5_ATOMIC_MODE_CX = 2 << 16, 102 MLX5_ATOMIC_MODE_8B = 3 << 16, 103 MLX5_ATOMIC_MODE_16B = 4 << 16, 104 MLX5_ATOMIC_MODE_32B = 5 << 16, 105 MLX5_ATOMIC_MODE_64B = 6 << 16, 106 MLX5_ATOMIC_MODE_128B = 7 << 16, 107 MLX5_ATOMIC_MODE_256B = 8 << 16, 108 }; 109 110 enum { 111 MLX5_REG_QPTS = 0x4002, 112 MLX5_REG_QETCR = 0x4005, 113 MLX5_REG_QTCT = 0x400a, 114 MLX5_REG_QPDPM = 0x4013, 115 MLX5_REG_QCAM = 0x4019, 116 MLX5_REG_DCBX_PARAM = 0x4020, 117 MLX5_REG_DCBX_APP = 0x4021, 118 MLX5_REG_FPGA_CAP = 0x4022, 119 MLX5_REG_FPGA_CTRL = 0x4023, 120 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 121 MLX5_REG_PCAP = 0x5001, 122 MLX5_REG_PMTU = 0x5003, 123 MLX5_REG_PTYS = 0x5004, 124 MLX5_REG_PAOS = 0x5006, 125 MLX5_REG_PFCC = 0x5007, 126 MLX5_REG_PPCNT = 0x5008, 127 MLX5_REG_PPTB = 0x500b, 128 MLX5_REG_PBMC = 0x500c, 129 MLX5_REG_PMAOS = 0x5012, 130 MLX5_REG_PUDE = 0x5009, 131 MLX5_REG_PMPE = 0x5010, 132 MLX5_REG_PELC = 0x500e, 133 MLX5_REG_PVLC = 0x500f, 134 MLX5_REG_PCMR = 0x5041, 135 MLX5_REG_PMLP = 0x5002, 136 MLX5_REG_PPLM = 0x5023, 137 MLX5_REG_PCAM = 0x507f, 138 MLX5_REG_NODE_DESC = 0x6001, 139 MLX5_REG_HOST_ENDIANNESS = 0x7004, 140 MLX5_REG_MCIA = 0x9014, 141 MLX5_REG_MLCR = 0x902b, 142 MLX5_REG_MTRC_CAP = 0x9040, 143 MLX5_REG_MTRC_CONF = 0x9041, 144 MLX5_REG_MTRC_STDB = 0x9042, 145 MLX5_REG_MTRC_CTRL = 0x9043, 146 MLX5_REG_MPCNT = 0x9051, 147 MLX5_REG_MTPPS = 0x9053, 148 MLX5_REG_MTPPSE = 0x9054, 149 MLX5_REG_MPEGC = 0x9056, 150 MLX5_REG_MCQI = 0x9061, 151 MLX5_REG_MCC = 0x9062, 152 MLX5_REG_MCDA = 0x9063, 153 MLX5_REG_MCAM = 0x907f, 154 }; 155 156 enum mlx5_qpts_trust_state { 157 MLX5_QPTS_TRUST_PCP = 1, 158 MLX5_QPTS_TRUST_DSCP = 2, 159 }; 160 161 enum mlx5_dcbx_oper_mode { 162 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 163 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 164 }; 165 166 enum mlx5_dct_atomic_mode { 167 MLX5_ATOMIC_MODE_DCT_CX = 2, 168 }; 169 170 enum { 171 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 172 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 173 }; 174 175 enum mlx5_page_fault_resume_flags { 176 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 177 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 178 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 179 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 180 }; 181 182 enum dbg_rsc_type { 183 MLX5_DBG_RSC_QP, 184 MLX5_DBG_RSC_EQ, 185 MLX5_DBG_RSC_CQ, 186 }; 187 188 enum port_state_policy { 189 MLX5_POLICY_DOWN = 0, 190 MLX5_POLICY_UP = 1, 191 MLX5_POLICY_FOLLOW = 2, 192 MLX5_POLICY_INVALID = 0xffffffff 193 }; 194 195 struct mlx5_field_desc { 196 struct dentry *dent; 197 int i; 198 }; 199 200 struct mlx5_rsc_debug { 201 struct mlx5_core_dev *dev; 202 void *object; 203 enum dbg_rsc_type type; 204 struct dentry *root; 205 struct mlx5_field_desc fields[0]; 206 }; 207 208 enum mlx5_dev_event { 209 MLX5_DEV_EVENT_SYS_ERROR, 210 MLX5_DEV_EVENT_PORT_UP, 211 MLX5_DEV_EVENT_PORT_DOWN, 212 MLX5_DEV_EVENT_PORT_INITIALIZED, 213 MLX5_DEV_EVENT_LID_CHANGE, 214 MLX5_DEV_EVENT_PKEY_CHANGE, 215 MLX5_DEV_EVENT_GUID_CHANGE, 216 MLX5_DEV_EVENT_CLIENT_REREG, 217 MLX5_DEV_EVENT_PPS, 218 MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 219 }; 220 221 enum mlx5_port_status { 222 MLX5_PORT_UP = 1, 223 MLX5_PORT_DOWN = 2, 224 }; 225 226 enum mlx5_eq_type { 227 MLX5_EQ_TYPE_COMP, 228 MLX5_EQ_TYPE_ASYNC, 229 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 230 MLX5_EQ_TYPE_PF, 231 #endif 232 }; 233 234 struct mlx5_bfreg_info { 235 u32 *sys_pages; 236 int num_low_latency_bfregs; 237 unsigned int *count; 238 239 /* 240 * protect bfreg allocation data structs 241 */ 242 struct mutex lock; 243 u32 ver; 244 bool lib_uar_4k; 245 u32 num_sys_pages; 246 u32 num_static_sys_pages; 247 u32 total_num_bfregs; 248 u32 num_dyn_bfregs; 249 }; 250 251 struct mlx5_cmd_first { 252 __be32 data[4]; 253 }; 254 255 struct mlx5_cmd_msg { 256 struct list_head list; 257 struct cmd_msg_cache *parent; 258 u32 len; 259 struct mlx5_cmd_first first; 260 struct mlx5_cmd_mailbox *next; 261 }; 262 263 struct mlx5_cmd_debug { 264 struct dentry *dbg_root; 265 struct dentry *dbg_in; 266 struct dentry *dbg_out; 267 struct dentry *dbg_outlen; 268 struct dentry *dbg_status; 269 struct dentry *dbg_run; 270 void *in_msg; 271 void *out_msg; 272 u8 status; 273 u16 inlen; 274 u16 outlen; 275 }; 276 277 struct cmd_msg_cache { 278 /* protect block chain allocations 279 */ 280 spinlock_t lock; 281 struct list_head head; 282 unsigned int max_inbox_size; 283 unsigned int num_ent; 284 }; 285 286 enum { 287 MLX5_NUM_COMMAND_CACHES = 5, 288 }; 289 290 struct mlx5_cmd_stats { 291 u64 sum; 292 u64 n; 293 struct dentry *root; 294 struct dentry *avg; 295 struct dentry *count; 296 /* protect command average calculations */ 297 spinlock_t lock; 298 }; 299 300 struct mlx5_cmd { 301 void *cmd_alloc_buf; 302 dma_addr_t alloc_dma; 303 int alloc_size; 304 void *cmd_buf; 305 dma_addr_t dma; 306 u16 cmdif_rev; 307 u8 log_sz; 308 u8 log_stride; 309 int max_reg_cmds; 310 int events; 311 u32 __iomem *vector; 312 313 /* protect command queue allocations 314 */ 315 spinlock_t alloc_lock; 316 317 /* protect token allocations 318 */ 319 spinlock_t token_lock; 320 u8 token; 321 unsigned long bitmask; 322 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 323 struct workqueue_struct *wq; 324 struct semaphore sem; 325 struct semaphore pages_sem; 326 int mode; 327 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 328 struct dma_pool *pool; 329 struct mlx5_cmd_debug dbg; 330 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 331 int checksum_disabled; 332 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 333 }; 334 335 struct mlx5_port_caps { 336 int gid_table_len; 337 int pkey_table_len; 338 u8 ext_port_cap; 339 bool has_smi; 340 }; 341 342 struct mlx5_cmd_mailbox { 343 void *buf; 344 dma_addr_t dma; 345 struct mlx5_cmd_mailbox *next; 346 }; 347 348 struct mlx5_buf_list { 349 void *buf; 350 dma_addr_t map; 351 }; 352 353 struct mlx5_frag_buf { 354 struct mlx5_buf_list *frags; 355 int npages; 356 int size; 357 u8 page_shift; 358 }; 359 360 struct mlx5_frag_buf_ctrl { 361 struct mlx5_buf_list *frags; 362 u32 sz_m1; 363 u16 frag_sz_m1; 364 u16 strides_offset; 365 u8 log_sz; 366 u8 log_stride; 367 u8 log_frag_strides; 368 }; 369 370 struct mlx5_eq_tasklet { 371 struct list_head list; 372 struct list_head process_list; 373 struct tasklet_struct task; 374 /* lock on completion tasklet list */ 375 spinlock_t lock; 376 }; 377 378 struct mlx5_eq_pagefault { 379 struct work_struct work; 380 /* Pagefaults lock */ 381 spinlock_t lock; 382 struct workqueue_struct *wq; 383 mempool_t *pool; 384 }; 385 386 struct mlx5_cq_table { 387 /* protect radix tree */ 388 spinlock_t lock; 389 struct radix_tree_root tree; 390 }; 391 392 struct mlx5_eq { 393 struct mlx5_core_dev *dev; 394 struct mlx5_cq_table cq_table; 395 __be32 __iomem *doorbell; 396 u32 cons_index; 397 struct mlx5_frag_buf buf; 398 int size; 399 unsigned int irqn; 400 u8 eqn; 401 int nent; 402 u64 mask; 403 struct list_head list; 404 int index; 405 struct mlx5_rsc_debug *dbg; 406 enum mlx5_eq_type type; 407 union { 408 struct mlx5_eq_tasklet tasklet_ctx; 409 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 410 struct mlx5_eq_pagefault pf_ctx; 411 #endif 412 }; 413 }; 414 415 struct mlx5_core_psv { 416 u32 psv_idx; 417 struct psv_layout { 418 u32 pd; 419 u16 syndrome; 420 u16 reserved; 421 u16 bg; 422 u16 app_tag; 423 u32 ref_tag; 424 } psv; 425 }; 426 427 struct mlx5_core_sig_ctx { 428 struct mlx5_core_psv psv_memory; 429 struct mlx5_core_psv psv_wire; 430 struct ib_sig_err err_item; 431 bool sig_status_checked; 432 bool sig_err_exists; 433 u32 sigerr_count; 434 }; 435 436 enum { 437 MLX5_MKEY_MR = 1, 438 MLX5_MKEY_MW, 439 }; 440 441 struct mlx5_core_mkey { 442 u64 iova; 443 u64 size; 444 u32 key; 445 u32 pd; 446 u32 type; 447 }; 448 449 #define MLX5_24BIT_MASK ((1 << 24) - 1) 450 451 enum mlx5_res_type { 452 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 453 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 454 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 455 MLX5_RES_SRQ = 3, 456 MLX5_RES_XSRQ = 4, 457 MLX5_RES_XRQ = 5, 458 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 459 }; 460 461 struct mlx5_core_rsc_common { 462 enum mlx5_res_type res; 463 atomic_t refcount; 464 struct completion free; 465 }; 466 467 struct mlx5_core_srq { 468 struct mlx5_core_rsc_common common; /* must be first */ 469 u32 srqn; 470 int max; 471 size_t max_gs; 472 size_t max_avail_gather; 473 int wqe_shift; 474 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 475 476 atomic_t refcount; 477 struct completion free; 478 u16 uid; 479 }; 480 481 struct mlx5_eq_table { 482 void __iomem *update_ci; 483 void __iomem *update_arm_ci; 484 struct list_head comp_eqs_list; 485 struct mlx5_eq pages_eq; 486 struct mlx5_eq async_eq; 487 struct mlx5_eq cmd_eq; 488 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 489 struct mlx5_eq pfault_eq; 490 #endif 491 int num_comp_vectors; 492 /* protect EQs list 493 */ 494 spinlock_t lock; 495 }; 496 497 struct mlx5_uars_page { 498 void __iomem *map; 499 bool wc; 500 u32 index; 501 struct list_head list; 502 unsigned int bfregs; 503 unsigned long *reg_bitmap; /* for non fast path bf regs */ 504 unsigned long *fp_bitmap; 505 unsigned int reg_avail; 506 unsigned int fp_avail; 507 struct kref ref_count; 508 struct mlx5_core_dev *mdev; 509 }; 510 511 struct mlx5_bfreg_head { 512 /* protect blue flame registers allocations */ 513 struct mutex lock; 514 struct list_head list; 515 }; 516 517 struct mlx5_bfreg_data { 518 struct mlx5_bfreg_head reg_head; 519 struct mlx5_bfreg_head wc_head; 520 }; 521 522 struct mlx5_sq_bfreg { 523 void __iomem *map; 524 struct mlx5_uars_page *up; 525 bool wc; 526 u32 index; 527 unsigned int offset; 528 }; 529 530 struct mlx5_core_health { 531 struct health_buffer __iomem *health; 532 __be32 __iomem *health_counter; 533 struct timer_list timer; 534 u32 prev; 535 int miss_counter; 536 bool sick; 537 /* wq spinlock to synchronize draining */ 538 spinlock_t wq_lock; 539 struct workqueue_struct *wq; 540 unsigned long flags; 541 struct work_struct work; 542 struct delayed_work recover_work; 543 }; 544 545 struct mlx5_qp_table { 546 /* protect radix tree 547 */ 548 spinlock_t lock; 549 struct radix_tree_root tree; 550 }; 551 552 struct mlx5_srq_table { 553 /* protect radix tree 554 */ 555 spinlock_t lock; 556 struct radix_tree_root tree; 557 }; 558 559 struct mlx5_mkey_table { 560 /* protect radix tree 561 */ 562 rwlock_t lock; 563 struct radix_tree_root tree; 564 }; 565 566 struct mlx5_vf_context { 567 int enabled; 568 u64 port_guid; 569 u64 node_guid; 570 enum port_state_policy policy; 571 }; 572 573 struct mlx5_core_sriov { 574 struct mlx5_vf_context *vfs_ctx; 575 int num_vfs; 576 int enabled_vfs; 577 }; 578 579 struct mlx5_irq_info { 580 cpumask_var_t mask; 581 char name[MLX5_MAX_IRQ_NAME]; 582 }; 583 584 struct mlx5_fc_stats { 585 spinlock_t counters_idr_lock; /* protects counters_idr */ 586 struct idr counters_idr; 587 struct list_head counters; 588 struct llist_head addlist; 589 struct llist_head dellist; 590 591 struct workqueue_struct *wq; 592 struct delayed_work work; 593 unsigned long next_query; 594 unsigned long sampling_interval; /* jiffies */ 595 }; 596 597 struct mlx5_mpfs; 598 struct mlx5_eswitch; 599 struct mlx5_lag; 600 struct mlx5_pagefault; 601 602 struct mlx5_rate_limit { 603 u32 rate; 604 u32 max_burst_sz; 605 u16 typical_pkt_sz; 606 }; 607 608 struct mlx5_rl_entry { 609 struct mlx5_rate_limit rl; 610 u16 index; 611 u16 refcount; 612 }; 613 614 struct mlx5_rl_table { 615 /* protect rate limit table */ 616 struct mutex rl_lock; 617 u16 max_size; 618 u32 max_rate; 619 u32 min_rate; 620 struct mlx5_rl_entry *rl_entry; 621 }; 622 623 enum port_module_event_status_type { 624 MLX5_MODULE_STATUS_PLUGGED = 0x1, 625 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 626 MLX5_MODULE_STATUS_ERROR = 0x3, 627 MLX5_MODULE_STATUS_NUM = 0x3, 628 }; 629 630 enum port_module_event_error_type { 631 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, 632 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, 633 MLX5_MODULE_EVENT_ERROR_BUS_STUCK, 634 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, 635 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, 636 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, 637 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, 638 MLX5_MODULE_EVENT_ERROR_BAD_CABLE, 639 MLX5_MODULE_EVENT_ERROR_UNKNOWN, 640 MLX5_MODULE_EVENT_ERROR_NUM, 641 }; 642 643 struct mlx5_port_module_event_stats { 644 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 645 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 646 }; 647 648 struct mlx5_priv { 649 char name[MLX5_MAX_NAME_LEN]; 650 struct mlx5_eq_table eq_table; 651 struct mlx5_irq_info *irq_info; 652 653 /* pages stuff */ 654 struct workqueue_struct *pg_wq; 655 struct rb_root page_root; 656 int fw_pages; 657 atomic_t reg_pages; 658 struct list_head free_list; 659 int vfs_pages; 660 661 struct mlx5_core_health health; 662 663 struct mlx5_srq_table srq_table; 664 665 /* start: qp staff */ 666 struct mlx5_qp_table qp_table; 667 struct dentry *qp_debugfs; 668 struct dentry *eq_debugfs; 669 struct dentry *cq_debugfs; 670 struct dentry *cmdif_debugfs; 671 /* end: qp staff */ 672 673 /* start: mkey staff */ 674 struct mlx5_mkey_table mkey_table; 675 /* end: mkey staff */ 676 677 /* start: alloc staff */ 678 /* protect buffer alocation according to numa node */ 679 struct mutex alloc_mutex; 680 int numa_node; 681 682 struct mutex pgdir_mutex; 683 struct list_head pgdir_list; 684 /* end: alloc staff */ 685 struct dentry *dbg_root; 686 687 /* protect mkey key part */ 688 spinlock_t mkey_lock; 689 u8 mkey_key; 690 691 struct list_head dev_list; 692 struct list_head ctx_list; 693 spinlock_t ctx_lock; 694 695 struct list_head waiting_events_list; 696 bool is_accum_events; 697 698 struct mlx5_flow_steering *steering; 699 struct mlx5_mpfs *mpfs; 700 struct mlx5_eswitch *eswitch; 701 struct mlx5_core_sriov sriov; 702 struct mlx5_lag *lag; 703 unsigned long pci_dev_data; 704 struct mlx5_fc_stats fc_stats; 705 struct mlx5_rl_table rl_table; 706 707 struct mlx5_port_module_event_stats pme_stats; 708 709 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 710 void (*pfault)(struct mlx5_core_dev *dev, 711 void *context, 712 struct mlx5_pagefault *pfault); 713 void *pfault_ctx; 714 struct srcu_struct pfault_srcu; 715 #endif 716 struct mlx5_bfreg_data bfregs; 717 struct mlx5_uars_page *uar; 718 }; 719 720 enum mlx5_device_state { 721 MLX5_DEVICE_STATE_UP, 722 MLX5_DEVICE_STATE_INTERNAL_ERROR, 723 }; 724 725 enum mlx5_interface_state { 726 MLX5_INTERFACE_STATE_UP = BIT(0), 727 }; 728 729 enum mlx5_pci_status { 730 MLX5_PCI_STATUS_DISABLED, 731 MLX5_PCI_STATUS_ENABLED, 732 }; 733 734 enum mlx5_pagefault_type_flags { 735 MLX5_PFAULT_REQUESTOR = 1 << 0, 736 MLX5_PFAULT_WRITE = 1 << 1, 737 MLX5_PFAULT_RDMA = 1 << 2, 738 }; 739 740 /* Contains the details of a pagefault. */ 741 struct mlx5_pagefault { 742 u32 bytes_committed; 743 u32 token; 744 u8 event_subtype; 745 u8 type; 746 union { 747 /* Initiator or send message responder pagefault details. */ 748 struct { 749 /* Received packet size, only valid for responders. */ 750 u32 packet_size; 751 /* 752 * Number of resource holding WQE, depends on type. 753 */ 754 u32 wq_num; 755 /* 756 * WQE index. Refers to either the send queue or 757 * receive queue, according to event_subtype. 758 */ 759 u16 wqe_index; 760 } wqe; 761 /* RDMA responder pagefault details */ 762 struct { 763 u32 r_key; 764 /* 765 * Received packet size, minimal size page fault 766 * resolution required for forward progress. 767 */ 768 u32 packet_size; 769 u32 rdma_op_len; 770 u64 rdma_va; 771 } rdma; 772 }; 773 774 struct mlx5_eq *eq; 775 struct work_struct work; 776 }; 777 778 struct mlx5_td { 779 struct list_head tirs_list; 780 u32 tdn; 781 }; 782 783 struct mlx5e_resources { 784 u32 pdn; 785 struct mlx5_td td; 786 struct mlx5_core_mkey mkey; 787 struct mlx5_sq_bfreg bfreg; 788 }; 789 790 #define MLX5_MAX_RESERVED_GIDS 8 791 792 struct mlx5_rsvd_gids { 793 unsigned int start; 794 unsigned int count; 795 struct ida ida; 796 }; 797 798 #define MAX_PIN_NUM 8 799 struct mlx5_pps { 800 u8 pin_caps[MAX_PIN_NUM]; 801 struct work_struct out_work; 802 u64 start[MAX_PIN_NUM]; 803 u8 enabled; 804 }; 805 806 struct mlx5_clock { 807 seqlock_t lock; 808 struct cyclecounter cycles; 809 struct timecounter tc; 810 struct hwtstamp_config hwtstamp_config; 811 u32 nominal_c_mult; 812 unsigned long overflow_period; 813 struct delayed_work overflow_work; 814 struct mlx5_core_dev *mdev; 815 struct ptp_clock *ptp; 816 struct ptp_clock_info ptp_info; 817 struct mlx5_pps pps_info; 818 }; 819 820 struct mlx5_fw_tracer; 821 struct mlx5_vxlan; 822 823 struct mlx5_core_dev { 824 struct pci_dev *pdev; 825 /* sync pci state */ 826 struct mutex pci_status_mutex; 827 enum mlx5_pci_status pci_status; 828 u8 rev_id; 829 char board_id[MLX5_BOARD_ID_LEN]; 830 struct mlx5_cmd cmd; 831 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 832 struct { 833 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 834 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 835 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 836 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 837 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 838 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 839 } caps; 840 u64 sys_image_guid; 841 phys_addr_t iseg_base; 842 struct mlx5_init_seg __iomem *iseg; 843 enum mlx5_device_state state; 844 /* sync interface state */ 845 struct mutex intf_state_mutex; 846 unsigned long intf_state; 847 void (*event) (struct mlx5_core_dev *dev, 848 enum mlx5_dev_event event, 849 unsigned long param); 850 struct mlx5_priv priv; 851 struct mlx5_profile *profile; 852 atomic_t num_qps; 853 u32 issi; 854 struct mlx5e_resources mlx5e_res; 855 struct mlx5_vxlan *vxlan; 856 struct { 857 struct mlx5_rsvd_gids reserved_gids; 858 u32 roce_en; 859 } roce; 860 #ifdef CONFIG_MLX5_FPGA 861 struct mlx5_fpga_device *fpga; 862 #endif 863 #ifdef CONFIG_RFS_ACCEL 864 struct cpu_rmap *rmap; 865 #endif 866 struct mlx5_clock clock; 867 struct mlx5_ib_clock_info *clock_info; 868 struct page *clock_info_page; 869 struct mlx5_fw_tracer *tracer; 870 }; 871 872 struct mlx5_db { 873 __be32 *db; 874 union { 875 struct mlx5_db_pgdir *pgdir; 876 struct mlx5_ib_user_db_page *user_page; 877 } u; 878 dma_addr_t dma; 879 int index; 880 }; 881 882 enum { 883 MLX5_COMP_EQ_SIZE = 1024, 884 }; 885 886 enum { 887 MLX5_PTYS_IB = 1 << 0, 888 MLX5_PTYS_EN = 1 << 2, 889 }; 890 891 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 892 893 enum { 894 MLX5_CMD_ENT_STATE_PENDING_COMP, 895 }; 896 897 struct mlx5_cmd_work_ent { 898 unsigned long state; 899 struct mlx5_cmd_msg *in; 900 struct mlx5_cmd_msg *out; 901 void *uout; 902 int uout_size; 903 mlx5_cmd_cbk_t callback; 904 struct delayed_work cb_timeout_work; 905 void *context; 906 int idx; 907 struct completion done; 908 struct mlx5_cmd *cmd; 909 struct work_struct work; 910 struct mlx5_cmd_layout *lay; 911 int ret; 912 int page_queue; 913 u8 status; 914 u8 token; 915 u64 ts1; 916 u64 ts2; 917 u16 op; 918 bool polling; 919 }; 920 921 struct mlx5_pas { 922 u64 pa; 923 u8 log_sz; 924 }; 925 926 enum phy_port_state { 927 MLX5_AAA_111 928 }; 929 930 struct mlx5_hca_vport_context { 931 u32 field_select; 932 bool sm_virt_aware; 933 bool has_smi; 934 bool has_raw; 935 enum port_state_policy policy; 936 enum phy_port_state phys_state; 937 enum ib_port_state vport_state; 938 u8 port_physical_state; 939 u64 sys_image_guid; 940 u64 port_guid; 941 u64 node_guid; 942 u32 cap_mask1; 943 u32 cap_mask1_perm; 944 u32 cap_mask2; 945 u32 cap_mask2_perm; 946 u16 lid; 947 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 948 u8 lmc; 949 u8 subnet_timeout; 950 u16 sm_lid; 951 u8 sm_sl; 952 u16 qkey_violation_counter; 953 u16 pkey_violation_counter; 954 bool grh_required; 955 }; 956 957 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) 958 { 959 return buf->frags->buf + offset; 960 } 961 962 #define STRUCT_FIELD(header, field) \ 963 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 964 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 965 966 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 967 { 968 return pci_get_drvdata(pdev); 969 } 970 971 extern struct dentry *mlx5_debugfs_root; 972 973 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 974 { 975 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 976 } 977 978 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 979 { 980 return ioread32be(&dev->iseg->fw_rev) >> 16; 981 } 982 983 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 984 { 985 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 986 } 987 988 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 989 { 990 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 991 } 992 993 static inline u32 mlx5_base_mkey(const u32 key) 994 { 995 return key & 0xffffff00u; 996 } 997 998 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, 999 u8 log_stride, u8 log_sz, 1000 u16 strides_offset, 1001 struct mlx5_frag_buf_ctrl *fbc) 1002 { 1003 fbc->frags = frags; 1004 fbc->log_stride = log_stride; 1005 fbc->log_sz = log_sz; 1006 fbc->sz_m1 = (1 << fbc->log_sz) - 1; 1007 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; 1008 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; 1009 fbc->strides_offset = strides_offset; 1010 } 1011 1012 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, 1013 u8 log_stride, u8 log_sz, 1014 struct mlx5_frag_buf_ctrl *fbc) 1015 { 1016 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); 1017 } 1018 1019 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, 1020 u32 ix) 1021 { 1022 unsigned int frag; 1023 1024 ix += fbc->strides_offset; 1025 frag = ix >> fbc->log_frag_strides; 1026 1027 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); 1028 } 1029 1030 static inline u32 1031 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) 1032 { 1033 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; 1034 1035 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); 1036 } 1037 1038 int mlx5_cmd_init(struct mlx5_core_dev *dev); 1039 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 1040 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 1041 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 1042 1043 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1044 int out_size); 1045 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 1046 void *out, int out_size, mlx5_cmd_cbk_t callback, 1047 void *context); 1048 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 1049 void *out, int out_size); 1050 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 1051 1052 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 1053 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 1054 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 1055 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 1056 int mlx5_health_init(struct mlx5_core_dev *dev); 1057 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 1058 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 1059 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 1060 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 1061 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 1062 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 1063 struct mlx5_frag_buf *buf, int node); 1064 int mlx5_buf_alloc(struct mlx5_core_dev *dev, 1065 int size, struct mlx5_frag_buf *buf); 1066 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 1067 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 1068 struct mlx5_frag_buf *buf, int node); 1069 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 1070 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 1071 gfp_t flags, int npages); 1072 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 1073 struct mlx5_cmd_mailbox *head); 1074 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1075 struct mlx5_srq_attr *in); 1076 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 1077 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1078 struct mlx5_srq_attr *out); 1079 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 1080 u16 lwm, int is_srq); 1081 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 1082 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 1083 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 1084 struct mlx5_core_mkey *mkey, 1085 u32 *in, int inlen, 1086 u32 *out, int outlen, 1087 mlx5_cmd_cbk_t callback, void *context); 1088 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 1089 struct mlx5_core_mkey *mkey, 1090 u32 *in, int inlen); 1091 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 1092 struct mlx5_core_mkey *mkey); 1093 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 1094 u32 *out, int outlen); 1095 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 1096 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 1097 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 1098 u16 opmod, u8 port); 1099 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 1100 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 1101 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 1102 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 1103 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 1104 s32 npages); 1105 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 1106 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 1107 void mlx5_register_debugfs(void); 1108 void mlx5_unregister_debugfs(void); 1109 1110 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); 1111 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 1112 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1113 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1114 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1115 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 1116 unsigned int *irqn); 1117 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1118 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1119 1120 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1121 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1122 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1123 int size_in, void *data_out, int size_out, 1124 u16 reg_num, int arg, int write); 1125 1126 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1127 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1128 int node); 1129 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1130 1131 const char *mlx5_command_str(int command); 1132 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1133 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1134 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1135 int npsvs, u32 *sig_index); 1136 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1137 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1138 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 1139 struct mlx5_odp_caps *odp_caps); 1140 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 1141 u8 port_num, void *out, size_t sz); 1142 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1143 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, 1144 u32 wq_num, u8 type, int error); 1145 #endif 1146 1147 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1148 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1149 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, 1150 struct mlx5_rate_limit *rl); 1151 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); 1152 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 1153 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, 1154 struct mlx5_rate_limit *rl_1); 1155 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 1156 bool map_wc, bool fast_path); 1157 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 1158 1159 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1160 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1161 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1162 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); 1163 1164 static inline int fw_initializing(struct mlx5_core_dev *dev) 1165 { 1166 return ioread32be(&dev->iseg->initializing) >> 31; 1167 } 1168 1169 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1170 { 1171 return mkey >> 8; 1172 } 1173 1174 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1175 { 1176 return mkey_idx << 8; 1177 } 1178 1179 static inline u8 mlx5_mkey_variant(u32 mkey) 1180 { 1181 return mkey & 0xff; 1182 } 1183 1184 enum { 1185 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1186 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1187 }; 1188 1189 enum { 1190 MR_CACHE_LAST_STD_ENTRY = 20, 1191 MLX5_IMR_MTT_CACHE_ENTRY, 1192 MLX5_IMR_KSM_CACHE_ENTRY, 1193 MAX_MR_CACHE_ENTRIES 1194 }; 1195 1196 enum { 1197 MLX5_INTERFACE_PROTOCOL_IB = 0, 1198 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1199 }; 1200 1201 struct mlx5_interface { 1202 void * (*add)(struct mlx5_core_dev *dev); 1203 void (*remove)(struct mlx5_core_dev *dev, void *context); 1204 int (*attach)(struct mlx5_core_dev *dev, void *context); 1205 void (*detach)(struct mlx5_core_dev *dev, void *context); 1206 void (*event)(struct mlx5_core_dev *dev, void *context, 1207 enum mlx5_dev_event event, unsigned long param); 1208 void (*pfault)(struct mlx5_core_dev *dev, 1209 void *context, 1210 struct mlx5_pagefault *pfault); 1211 void * (*get_dev)(void *context); 1212 int protocol; 1213 struct list_head list; 1214 }; 1215 1216 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1217 int mlx5_register_interface(struct mlx5_interface *intf); 1218 void mlx5_unregister_interface(struct mlx5_interface *intf); 1219 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1220 1221 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1222 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1223 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1224 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1225 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, 1226 u64 *values, 1227 int num_counters, 1228 size_t *offsets); 1229 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1230 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1231 1232 #ifdef CONFIG_MLX5_CORE_IPOIB 1233 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, 1234 struct ib_device *ibdev, 1235 const char *name, 1236 void (*setup)(struct net_device *)); 1237 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1238 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, 1239 struct ib_device *device, 1240 struct rdma_netdev_alloc_params *params); 1241 1242 struct mlx5_profile { 1243 u64 mask; 1244 u8 log_max_qp; 1245 struct { 1246 int size; 1247 int limit; 1248 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1249 }; 1250 1251 enum { 1252 MLX5_PCI_DEV_IS_VF = 1 << 0, 1253 }; 1254 1255 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1256 { 1257 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1258 } 1259 1260 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev)) 1261 #define MLX5_VPORT_MANAGER(mdev) \ 1262 (MLX5_CAP_GEN(mdev, vport_group_manager) && \ 1263 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \ 1264 mlx5_core_is_pf(mdev)) 1265 1266 static inline int mlx5_get_gid_table_len(u16 param) 1267 { 1268 if (param > 4) { 1269 pr_warn("gid table length is zero\n"); 1270 return 0; 1271 } 1272 1273 return 8 * (1 << param); 1274 } 1275 1276 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1277 { 1278 return !!(dev->priv.rl_table.max_size); 1279 } 1280 1281 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) 1282 { 1283 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && 1284 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; 1285 } 1286 1287 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) 1288 { 1289 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; 1290 } 1291 1292 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) 1293 { 1294 return mlx5_core_is_mp_slave(dev) || 1295 mlx5_core_is_mp_master(dev); 1296 } 1297 1298 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) 1299 { 1300 if (!mlx5_core_mp_enabled(dev)) 1301 return 1; 1302 1303 return MLX5_CAP_GEN(dev, native_port_num); 1304 } 1305 1306 enum { 1307 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1308 }; 1309 1310 static inline const struct cpumask * 1311 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector) 1312 { 1313 return dev->priv.irq_info[vector].mask; 1314 } 1315 1316 #endif /* MLX5_DRIVER_H */ 1317