xref: /linux-6.15/include/linux/mlx5/driver.h (revision 80c170d7) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53 
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <linux/ptp_clock_kernel.h>
59 #include <net/devlink.h>
60 
61 #define MLX5_ADEV_NAME "mlx5_core"
62 
63 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
64 
65 enum {
66 	MLX5_BOARD_ID_LEN = 64,
67 };
68 
69 enum {
70 	MLX5_CMD_WQ_MAX_NAME	= 32,
71 };
72 
73 enum {
74 	CMD_OWNER_SW		= 0x0,
75 	CMD_OWNER_HW		= 0x1,
76 	CMD_STATUS_SUCCESS	= 0,
77 };
78 
79 enum mlx5_sqp_t {
80 	MLX5_SQP_SMI		= 0,
81 	MLX5_SQP_GSI		= 1,
82 	MLX5_SQP_IEEE_1588	= 2,
83 	MLX5_SQP_SNIFFER	= 3,
84 	MLX5_SQP_SYNC_UMR	= 4,
85 };
86 
87 enum {
88 	MLX5_MAX_PORTS	= 4,
89 };
90 
91 enum {
92 	MLX5_ATOMIC_MODE_OFFSET = 16,
93 	MLX5_ATOMIC_MODE_IB_COMP = 1,
94 	MLX5_ATOMIC_MODE_CX = 2,
95 	MLX5_ATOMIC_MODE_8B = 3,
96 	MLX5_ATOMIC_MODE_16B = 4,
97 	MLX5_ATOMIC_MODE_32B = 5,
98 	MLX5_ATOMIC_MODE_64B = 6,
99 	MLX5_ATOMIC_MODE_128B = 7,
100 	MLX5_ATOMIC_MODE_256B = 8,
101 };
102 
103 enum {
104 	MLX5_REG_SBPR            = 0xb001,
105 	MLX5_REG_SBCM            = 0xb002,
106 	MLX5_REG_QPTS            = 0x4002,
107 	MLX5_REG_QETCR		 = 0x4005,
108 	MLX5_REG_QTCT		 = 0x400a,
109 	MLX5_REG_QPDPM           = 0x4013,
110 	MLX5_REG_QCAM            = 0x4019,
111 	MLX5_REG_DCBX_PARAM      = 0x4020,
112 	MLX5_REG_DCBX_APP        = 0x4021,
113 	MLX5_REG_FPGA_CAP	 = 0x4022,
114 	MLX5_REG_FPGA_CTRL	 = 0x4023,
115 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
116 	MLX5_REG_CORE_DUMP	 = 0x402e,
117 	MLX5_REG_PCAP		 = 0x5001,
118 	MLX5_REG_PMTU		 = 0x5003,
119 	MLX5_REG_PTYS		 = 0x5004,
120 	MLX5_REG_PAOS		 = 0x5006,
121 	MLX5_REG_PFCC            = 0x5007,
122 	MLX5_REG_PPCNT		 = 0x5008,
123 	MLX5_REG_PPTB            = 0x500b,
124 	MLX5_REG_PBMC            = 0x500c,
125 	MLX5_REG_PMAOS		 = 0x5012,
126 	MLX5_REG_PUDE		 = 0x5009,
127 	MLX5_REG_PMPE		 = 0x5010,
128 	MLX5_REG_PELC		 = 0x500e,
129 	MLX5_REG_PVLC		 = 0x500f,
130 	MLX5_REG_PCMR		 = 0x5041,
131 	MLX5_REG_PDDR		 = 0x5031,
132 	MLX5_REG_PMLP		 = 0x5002,
133 	MLX5_REG_PPLM		 = 0x5023,
134 	MLX5_REG_PCAM		 = 0x507f,
135 	MLX5_REG_NODE_DESC	 = 0x6001,
136 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 	MLX5_REG_MCIA		 = 0x9014,
138 	MLX5_REG_MFRL		 = 0x9028,
139 	MLX5_REG_MLCR		 = 0x902b,
140 	MLX5_REG_MRTC		 = 0x902d,
141 	MLX5_REG_MTRC_CAP	 = 0x9040,
142 	MLX5_REG_MTRC_CONF	 = 0x9041,
143 	MLX5_REG_MTRC_STDB	 = 0x9042,
144 	MLX5_REG_MTRC_CTRL	 = 0x9043,
145 	MLX5_REG_MPEIN		 = 0x9050,
146 	MLX5_REG_MPCNT		 = 0x9051,
147 	MLX5_REG_MTPPS		 = 0x9053,
148 	MLX5_REG_MTPPSE		 = 0x9054,
149 	MLX5_REG_MTUTC		 = 0x9055,
150 	MLX5_REG_MPEGC		 = 0x9056,
151 	MLX5_REG_MCQS		 = 0x9060,
152 	MLX5_REG_MCQI		 = 0x9061,
153 	MLX5_REG_MCC		 = 0x9062,
154 	MLX5_REG_MCDA		 = 0x9063,
155 	MLX5_REG_MCAM		 = 0x907f,
156 	MLX5_REG_MIRC		 = 0x9162,
157 	MLX5_REG_SBCAM		 = 0xB01F,
158 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
159 	MLX5_REG_DTOR            = 0xC00E,
160 };
161 
162 enum mlx5_qpts_trust_state {
163 	MLX5_QPTS_TRUST_PCP  = 1,
164 	MLX5_QPTS_TRUST_DSCP = 2,
165 };
166 
167 enum mlx5_dcbx_oper_mode {
168 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
169 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
170 };
171 
172 enum {
173 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
174 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
175 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
176 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
177 };
178 
179 enum mlx5_page_fault_resume_flags {
180 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
181 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
182 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
183 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
184 };
185 
186 enum dbg_rsc_type {
187 	MLX5_DBG_RSC_QP,
188 	MLX5_DBG_RSC_EQ,
189 	MLX5_DBG_RSC_CQ,
190 };
191 
192 enum port_state_policy {
193 	MLX5_POLICY_DOWN	= 0,
194 	MLX5_POLICY_UP		= 1,
195 	MLX5_POLICY_FOLLOW	= 2,
196 	MLX5_POLICY_INVALID	= 0xffffffff
197 };
198 
199 enum mlx5_coredev_type {
200 	MLX5_COREDEV_PF,
201 	MLX5_COREDEV_VF,
202 	MLX5_COREDEV_SF,
203 };
204 
205 struct mlx5_field_desc {
206 	int			i;
207 };
208 
209 struct mlx5_rsc_debug {
210 	struct mlx5_core_dev   *dev;
211 	void		       *object;
212 	enum dbg_rsc_type	type;
213 	struct dentry	       *root;
214 	struct mlx5_field_desc	fields[];
215 };
216 
217 enum mlx5_dev_event {
218 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
219 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
220 	MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
221 };
222 
223 enum mlx5_port_status {
224 	MLX5_PORT_UP        = 1,
225 	MLX5_PORT_DOWN      = 2,
226 };
227 
228 enum mlx5_cmdif_state {
229 	MLX5_CMDIF_STATE_UNINITIALIZED,
230 	MLX5_CMDIF_STATE_UP,
231 	MLX5_CMDIF_STATE_DOWN,
232 };
233 
234 struct mlx5_cmd_first {
235 	__be32		data[4];
236 };
237 
238 struct mlx5_cmd_msg {
239 	struct list_head		list;
240 	struct cmd_msg_cache	       *parent;
241 	u32				len;
242 	struct mlx5_cmd_first		first;
243 	struct mlx5_cmd_mailbox	       *next;
244 };
245 
246 struct mlx5_cmd_debug {
247 	struct dentry	       *dbg_root;
248 	void		       *in_msg;
249 	void		       *out_msg;
250 	u8			status;
251 	u16			inlen;
252 	u16			outlen;
253 };
254 
255 struct cmd_msg_cache {
256 	/* protect block chain allocations
257 	 */
258 	spinlock_t		lock;
259 	struct list_head	head;
260 	unsigned int		max_inbox_size;
261 	unsigned int		num_ent;
262 };
263 
264 enum {
265 	MLX5_NUM_COMMAND_CACHES = 5,
266 };
267 
268 struct mlx5_cmd_stats {
269 	u64		sum;
270 	u64		n;
271 	/* number of times command failed */
272 	u64		failed;
273 	/* number of times command failed on bad status returned by FW */
274 	u64		failed_mbox_status;
275 	/* last command failed returned errno */
276 	u32		last_failed_errno;
277 	/* last bad status returned by FW */
278 	u8		last_failed_mbox_status;
279 	/* last command failed syndrome returned by FW */
280 	u32		last_failed_syndrome;
281 	struct dentry  *root;
282 	/* protect command average calculations */
283 	spinlock_t	lock;
284 };
285 
286 struct mlx5_cmd {
287 	struct mlx5_nb    nb;
288 
289 	enum mlx5_cmdif_state	state;
290 	void	       *cmd_alloc_buf;
291 	dma_addr_t	alloc_dma;
292 	int		alloc_size;
293 	void	       *cmd_buf;
294 	dma_addr_t	dma;
295 	u16		cmdif_rev;
296 	u8		log_sz;
297 	u8		log_stride;
298 	int		max_reg_cmds;
299 	int		events;
300 	u32 __iomem    *vector;
301 
302 	/* protect command queue allocations
303 	 */
304 	spinlock_t	alloc_lock;
305 
306 	/* protect token allocations
307 	 */
308 	spinlock_t	token_lock;
309 	u8		token;
310 	unsigned long	bitmask;
311 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
312 	struct workqueue_struct *wq;
313 	struct semaphore sem;
314 	struct semaphore pages_sem;
315 	struct semaphore throttle_sem;
316 	int	mode;
317 	u16     allowed_opcode;
318 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
319 	struct dma_pool *pool;
320 	struct mlx5_cmd_debug dbg;
321 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
322 	int checksum_disabled;
323 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
324 };
325 
326 struct mlx5_cmd_mailbox {
327 	void	       *buf;
328 	dma_addr_t	dma;
329 	struct mlx5_cmd_mailbox *next;
330 };
331 
332 struct mlx5_buf_list {
333 	void		       *buf;
334 	dma_addr_t		map;
335 };
336 
337 struct mlx5_frag_buf {
338 	struct mlx5_buf_list	*frags;
339 	int			npages;
340 	int			size;
341 	u8			page_shift;
342 };
343 
344 struct mlx5_frag_buf_ctrl {
345 	struct mlx5_buf_list   *frags;
346 	u32			sz_m1;
347 	u16			frag_sz_m1;
348 	u16			strides_offset;
349 	u8			log_sz;
350 	u8			log_stride;
351 	u8			log_frag_strides;
352 };
353 
354 struct mlx5_core_psv {
355 	u32	psv_idx;
356 	struct psv_layout {
357 		u32	pd;
358 		u16	syndrome;
359 		u16	reserved;
360 		u16	bg;
361 		u16	app_tag;
362 		u32	ref_tag;
363 	} psv;
364 };
365 
366 struct mlx5_core_sig_ctx {
367 	struct mlx5_core_psv	psv_memory;
368 	struct mlx5_core_psv	psv_wire;
369 	struct ib_sig_err       err_item;
370 	bool			sig_status_checked;
371 	bool			sig_err_exists;
372 	u32			sigerr_count;
373 };
374 
375 #define MLX5_24BIT_MASK		((1 << 24) - 1)
376 
377 enum mlx5_res_type {
378 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
379 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
380 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
381 	MLX5_RES_SRQ	= 3,
382 	MLX5_RES_XSRQ	= 4,
383 	MLX5_RES_XRQ	= 5,
384 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
385 };
386 
387 struct mlx5_core_rsc_common {
388 	enum mlx5_res_type	res;
389 	refcount_t		refcount;
390 	struct completion	free;
391 };
392 
393 struct mlx5_uars_page {
394 	void __iomem	       *map;
395 	bool			wc;
396 	u32			index;
397 	struct list_head	list;
398 	unsigned int		bfregs;
399 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
400 	unsigned long	       *fp_bitmap;
401 	unsigned int		reg_avail;
402 	unsigned int		fp_avail;
403 	struct kref		ref_count;
404 	struct mlx5_core_dev   *mdev;
405 };
406 
407 struct mlx5_bfreg_head {
408 	/* protect blue flame registers allocations */
409 	struct mutex		lock;
410 	struct list_head	list;
411 };
412 
413 struct mlx5_bfreg_data {
414 	struct mlx5_bfreg_head	reg_head;
415 	struct mlx5_bfreg_head	wc_head;
416 };
417 
418 struct mlx5_sq_bfreg {
419 	void __iomem	       *map;
420 	struct mlx5_uars_page  *up;
421 	bool			wc;
422 	u32			index;
423 	unsigned int		offset;
424 };
425 
426 struct mlx5_core_health {
427 	struct health_buffer __iomem   *health;
428 	__be32 __iomem		       *health_counter;
429 	struct timer_list		timer;
430 	u32				prev;
431 	int				miss_counter;
432 	u8				synd;
433 	u32				fatal_error;
434 	u32				crdump_size;
435 	struct workqueue_struct	       *wq;
436 	unsigned long			flags;
437 	struct work_struct		fatal_report_work;
438 	struct work_struct		report_work;
439 	struct devlink_health_reporter *fw_reporter;
440 	struct devlink_health_reporter *fw_fatal_reporter;
441 	struct delayed_work		update_fw_log_ts_work;
442 };
443 
444 struct mlx5_qp_table {
445 	struct notifier_block   nb;
446 
447 	/* protect radix tree
448 	 */
449 	spinlock_t		lock;
450 	struct radix_tree_root	tree;
451 };
452 
453 enum {
454 	MLX5_PF_NOTIFY_DISABLE_VF,
455 	MLX5_PF_NOTIFY_ENABLE_VF,
456 };
457 
458 struct mlx5_vf_context {
459 	int	enabled;
460 	u64	port_guid;
461 	u64	node_guid;
462 	/* Valid bits are used to validate administrative guid only.
463 	 * Enabled after ndo_set_vf_guid
464 	 */
465 	u8	port_guid_valid:1;
466 	u8	node_guid_valid:1;
467 	enum port_state_policy	policy;
468 	struct blocking_notifier_head notifier;
469 };
470 
471 struct mlx5_core_sriov {
472 	struct mlx5_vf_context	*vfs_ctx;
473 	int			num_vfs;
474 	u16			max_vfs;
475 };
476 
477 struct mlx5_fc_pool {
478 	struct mlx5_core_dev *dev;
479 	struct mutex pool_lock; /* protects pool lists */
480 	struct list_head fully_used;
481 	struct list_head partially_used;
482 	struct list_head unused;
483 	int available_fcs;
484 	int used_fcs;
485 	int threshold;
486 };
487 
488 struct mlx5_fc_stats {
489 	spinlock_t counters_idr_lock; /* protects counters_idr */
490 	struct idr counters_idr;
491 	struct list_head counters;
492 	struct llist_head addlist;
493 	struct llist_head dellist;
494 
495 	struct workqueue_struct *wq;
496 	struct delayed_work work;
497 	unsigned long next_query;
498 	unsigned long sampling_interval; /* jiffies */
499 	u32 *bulk_query_out;
500 	int bulk_query_len;
501 	size_t num_counters;
502 	bool bulk_query_alloc_failed;
503 	unsigned long next_bulk_query_alloc;
504 	struct mlx5_fc_pool fc_pool;
505 };
506 
507 struct mlx5_events;
508 struct mlx5_mpfs;
509 struct mlx5_eswitch;
510 struct mlx5_lag;
511 struct mlx5_devcom;
512 struct mlx5_fw_reset;
513 struct mlx5_eq_table;
514 struct mlx5_irq_table;
515 struct mlx5_vhca_state_notifier;
516 struct mlx5_sf_dev_table;
517 struct mlx5_sf_hw_table;
518 struct mlx5_sf_table;
519 struct mlx5_crypto_dek_priv;
520 
521 struct mlx5_rate_limit {
522 	u32			rate;
523 	u32			max_burst_sz;
524 	u16			typical_pkt_sz;
525 };
526 
527 struct mlx5_rl_entry {
528 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
529 	u64 refcount;
530 	u16 index;
531 	u16 uid;
532 	u8 dedicated : 1;
533 };
534 
535 struct mlx5_rl_table {
536 	/* protect rate limit table */
537 	struct mutex            rl_lock;
538 	u16                     max_size;
539 	u32                     max_rate;
540 	u32                     min_rate;
541 	struct mlx5_rl_entry   *rl_entry;
542 	u64 refcount;
543 };
544 
545 struct mlx5_core_roce {
546 	struct mlx5_flow_table *ft;
547 	struct mlx5_flow_group *fg;
548 	struct mlx5_flow_handle *allow_rule;
549 };
550 
551 enum {
552 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
553 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
554 	/* Set during device detach to block any further devices
555 	 * creation/deletion on drivers rescan. Unset during device attach.
556 	 */
557 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
558 };
559 
560 struct mlx5_adev {
561 	struct auxiliary_device adev;
562 	struct mlx5_core_dev *mdev;
563 	int idx;
564 };
565 
566 struct mlx5_debugfs_entries {
567 	struct dentry *dbg_root;
568 	struct dentry *qp_debugfs;
569 	struct dentry *eq_debugfs;
570 	struct dentry *cq_debugfs;
571 	struct dentry *cmdif_debugfs;
572 	struct dentry *pages_debugfs;
573 	struct dentry *lag_debugfs;
574 };
575 
576 enum mlx5_func_type {
577 	MLX5_PF,
578 	MLX5_VF,
579 	MLX5_SF,
580 	MLX5_HOST_PF,
581 	MLX5_FUNC_TYPE_NUM,
582 };
583 
584 struct mlx5_ft_pool;
585 struct mlx5_priv {
586 	/* IRQ table valid only for real pci devices PF or VF */
587 	struct mlx5_irq_table   *irq_table;
588 	struct mlx5_eq_table	*eq_table;
589 
590 	/* pages stuff */
591 	struct mlx5_nb          pg_nb;
592 	struct workqueue_struct *pg_wq;
593 	struct xarray           page_root_xa;
594 	atomic_t		reg_pages;
595 	struct list_head	free_list;
596 	u32			fw_pages;
597 	u32			page_counters[MLX5_FUNC_TYPE_NUM];
598 	u32			fw_pages_alloc_failed;
599 	u32			give_pages_dropped;
600 	u32			reclaim_pages_discard;
601 
602 	struct mlx5_core_health health;
603 	struct list_head	traps;
604 
605 	struct mlx5_debugfs_entries dbg;
606 
607 	/* start: alloc staff */
608 	/* protect buffer allocation according to numa node */
609 	struct mutex            alloc_mutex;
610 	int                     numa_node;
611 
612 	struct mutex            pgdir_mutex;
613 	struct list_head        pgdir_list;
614 	/* end: alloc staff */
615 
616 	struct mlx5_adev       **adev;
617 	int			adev_idx;
618 	int			sw_vhca_id;
619 	struct mlx5_events      *events;
620 
621 	struct mlx5_flow_steering *steering;
622 	struct mlx5_mpfs        *mpfs;
623 	struct mlx5_eswitch     *eswitch;
624 	struct mlx5_core_sriov	sriov;
625 	struct mlx5_lag		*lag;
626 	u32			flags;
627 	struct mlx5_devcom	*devcom;
628 	struct mlx5_fw_reset	*fw_reset;
629 	struct mlx5_core_roce	roce;
630 	struct mlx5_fc_stats		fc_stats;
631 	struct mlx5_rl_table            rl_table;
632 	struct mlx5_ft_pool		*ft_pool;
633 
634 	struct mlx5_bfreg_data		bfregs;
635 	struct mlx5_uars_page	       *uar;
636 #ifdef CONFIG_MLX5_SF
637 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
638 	struct mlx5_sf_dev_table *sf_dev_table;
639 	struct mlx5_core_dev *parent_mdev;
640 #endif
641 #ifdef CONFIG_MLX5_SF_MANAGER
642 	struct mlx5_sf_hw_table *sf_hw_table;
643 	struct mlx5_sf_table *sf_table;
644 #endif
645 };
646 
647 enum mlx5_device_state {
648 	MLX5_DEVICE_STATE_UP = 1,
649 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
650 };
651 
652 enum mlx5_interface_state {
653 	MLX5_INTERFACE_STATE_UP = BIT(0),
654 	MLX5_BREAK_FW_WAIT = BIT(1),
655 };
656 
657 enum mlx5_pci_status {
658 	MLX5_PCI_STATUS_DISABLED,
659 	MLX5_PCI_STATUS_ENABLED,
660 };
661 
662 enum mlx5_pagefault_type_flags {
663 	MLX5_PFAULT_REQUESTOR = 1 << 0,
664 	MLX5_PFAULT_WRITE     = 1 << 1,
665 	MLX5_PFAULT_RDMA      = 1 << 2,
666 };
667 
668 struct mlx5_td {
669 	/* protects tirs list changes while tirs refresh */
670 	struct mutex     list_lock;
671 	struct list_head tirs_list;
672 	u32              tdn;
673 };
674 
675 struct mlx5e_resources {
676 	struct mlx5e_hw_objs {
677 		u32                        pdn;
678 		struct mlx5_td             td;
679 		u32			   mkey;
680 		struct mlx5_sq_bfreg       bfreg;
681 	} hw_objs;
682 	struct net_device *uplink_netdev;
683 	struct mutex uplink_netdev_lock;
684 	struct mlx5_crypto_dek_priv *dek_priv;
685 };
686 
687 enum mlx5_sw_icm_type {
688 	MLX5_SW_ICM_TYPE_STEERING,
689 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
690 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
691 };
692 
693 #define MLX5_MAX_RESERVED_GIDS 8
694 
695 struct mlx5_rsvd_gids {
696 	unsigned int start;
697 	unsigned int count;
698 	struct ida ida;
699 };
700 
701 #define MAX_PIN_NUM	8
702 struct mlx5_pps {
703 	u8                         pin_caps[MAX_PIN_NUM];
704 	struct work_struct         out_work;
705 	u64                        start[MAX_PIN_NUM];
706 	u8                         enabled;
707 	u64                        min_npps_period;
708 	u64                        min_out_pulse_duration_ns;
709 };
710 
711 struct mlx5_timer {
712 	struct cyclecounter        cycles;
713 	struct timecounter         tc;
714 	u32                        nominal_c_mult;
715 	unsigned long              overflow_period;
716 	struct delayed_work        overflow_work;
717 };
718 
719 struct mlx5_clock {
720 	struct mlx5_nb             pps_nb;
721 	seqlock_t                  lock;
722 	struct hwtstamp_config     hwtstamp_config;
723 	struct ptp_clock          *ptp;
724 	struct ptp_clock_info      ptp_info;
725 	struct mlx5_pps            pps_info;
726 	struct mlx5_timer          timer;
727 };
728 
729 struct mlx5_dm;
730 struct mlx5_fw_tracer;
731 struct mlx5_vxlan;
732 struct mlx5_geneve;
733 struct mlx5_hv_vhca;
734 
735 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
736 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
737 
738 enum {
739 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
740 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
741 };
742 
743 enum {
744 	MKEY_CACHE_LAST_STD_ENTRY = 20,
745 	MLX5_IMR_KSM_CACHE_ENTRY,
746 	MAX_MKEY_CACHE_ENTRIES
747 };
748 
749 struct mlx5_profile {
750 	u64	mask;
751 	u8	log_max_qp;
752 	struct {
753 		int	size;
754 		int	limit;
755 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
756 };
757 
758 struct mlx5_hca_cap {
759 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
760 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
761 };
762 
763 struct mlx5_core_dev {
764 	struct device *device;
765 	enum mlx5_coredev_type coredev_type;
766 	struct pci_dev	       *pdev;
767 	/* sync pci state */
768 	struct mutex		pci_status_mutex;
769 	enum mlx5_pci_status	pci_status;
770 	u8			rev_id;
771 	char			board_id[MLX5_BOARD_ID_LEN];
772 	struct mlx5_cmd		cmd;
773 	struct {
774 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
775 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
776 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
777 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
778 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
779 		u8  embedded_cpu;
780 	} caps;
781 	struct mlx5_timeouts	*timeouts;
782 	u64			sys_image_guid;
783 	phys_addr_t		iseg_base;
784 	struct mlx5_init_seg __iomem *iseg;
785 	phys_addr_t             bar_addr;
786 	enum mlx5_device_state	state;
787 	/* sync interface state */
788 	struct mutex		intf_state_mutex;
789 	struct lock_class_key	lock_key;
790 	unsigned long		intf_state;
791 	struct mlx5_priv	priv;
792 	struct mlx5_profile	profile;
793 	u32			issi;
794 	struct mlx5e_resources  mlx5e_res;
795 	struct mlx5_dm          *dm;
796 	struct mlx5_vxlan       *vxlan;
797 	struct mlx5_geneve      *geneve;
798 	struct {
799 		struct mlx5_rsvd_gids	reserved_gids;
800 		u32			roce_en;
801 	} roce;
802 #ifdef CONFIG_MLX5_FPGA
803 	struct mlx5_fpga_device *fpga;
804 #endif
805 	struct mlx5_clock        clock;
806 	struct mlx5_ib_clock_info  *clock_info;
807 	struct mlx5_fw_tracer   *tracer;
808 	struct mlx5_rsc_dump    *rsc_dump;
809 	u32                      vsc_addr;
810 	struct mlx5_hv_vhca	*hv_vhca;
811 };
812 
813 struct mlx5_db {
814 	__be32			*db;
815 	union {
816 		struct mlx5_db_pgdir		*pgdir;
817 		struct mlx5_ib_user_db_page	*user_page;
818 	}			u;
819 	dma_addr_t		dma;
820 	int			index;
821 };
822 
823 enum {
824 	MLX5_COMP_EQ_SIZE = 1024,
825 };
826 
827 enum {
828 	MLX5_PTYS_IB = 1 << 0,
829 	MLX5_PTYS_EN = 1 << 2,
830 };
831 
832 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
833 
834 enum {
835 	MLX5_CMD_ENT_STATE_PENDING_COMP,
836 };
837 
838 struct mlx5_cmd_work_ent {
839 	unsigned long		state;
840 	struct mlx5_cmd_msg    *in;
841 	struct mlx5_cmd_msg    *out;
842 	void		       *uout;
843 	int			uout_size;
844 	mlx5_cmd_cbk_t		callback;
845 	struct delayed_work	cb_timeout_work;
846 	void		       *context;
847 	int			idx;
848 	struct completion	handling;
849 	struct completion	done;
850 	struct mlx5_cmd        *cmd;
851 	struct work_struct	work;
852 	struct mlx5_cmd_layout *lay;
853 	int			ret;
854 	int			page_queue;
855 	u8			status;
856 	u8			token;
857 	u64			ts1;
858 	u64			ts2;
859 	u16			op;
860 	bool			polling;
861 	/* Track the max comp handlers */
862 	refcount_t              refcnt;
863 };
864 
865 enum phy_port_state {
866 	MLX5_AAA_111
867 };
868 
869 struct mlx5_hca_vport_context {
870 	u32			field_select;
871 	bool			sm_virt_aware;
872 	bool			has_smi;
873 	bool			has_raw;
874 	enum port_state_policy	policy;
875 	enum phy_port_state	phys_state;
876 	enum ib_port_state	vport_state;
877 	u8			port_physical_state;
878 	u64			sys_image_guid;
879 	u64			port_guid;
880 	u64			node_guid;
881 	u32			cap_mask1;
882 	u32			cap_mask1_perm;
883 	u16			cap_mask2;
884 	u16			cap_mask2_perm;
885 	u16			lid;
886 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
887 	u8			lmc;
888 	u8			subnet_timeout;
889 	u16			sm_lid;
890 	u8			sm_sl;
891 	u16			qkey_violation_counter;
892 	u16			pkey_violation_counter;
893 	bool			grh_required;
894 };
895 
896 #define STRUCT_FIELD(header, field) \
897 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
898 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
899 
900 extern struct dentry *mlx5_debugfs_root;
901 
902 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
903 {
904 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
905 }
906 
907 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
908 {
909 	return ioread32be(&dev->iseg->fw_rev) >> 16;
910 }
911 
912 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
913 {
914 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
915 }
916 
917 static inline u32 mlx5_base_mkey(const u32 key)
918 {
919 	return key & 0xffffff00u;
920 }
921 
922 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
923 {
924 	return ((u32)1 << log_sz) << log_stride;
925 }
926 
927 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
928 					u8 log_stride, u8 log_sz,
929 					u16 strides_offset,
930 					struct mlx5_frag_buf_ctrl *fbc)
931 {
932 	fbc->frags      = frags;
933 	fbc->log_stride = log_stride;
934 	fbc->log_sz     = log_sz;
935 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
936 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
937 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
938 	fbc->strides_offset = strides_offset;
939 }
940 
941 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
942 				 u8 log_stride, u8 log_sz,
943 				 struct mlx5_frag_buf_ctrl *fbc)
944 {
945 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
946 }
947 
948 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
949 					  u32 ix)
950 {
951 	unsigned int frag;
952 
953 	ix  += fbc->strides_offset;
954 	frag = ix >> fbc->log_frag_strides;
955 
956 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
957 }
958 
959 static inline u32
960 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
961 {
962 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
963 
964 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
965 }
966 
967 enum {
968 	CMD_ALLOWED_OPCODE_ALL,
969 };
970 
971 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
972 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
973 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
974 
975 struct mlx5_async_ctx {
976 	struct mlx5_core_dev *dev;
977 	atomic_t num_inflight;
978 	struct completion inflight_done;
979 };
980 
981 struct mlx5_async_work;
982 
983 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
984 
985 struct mlx5_async_work {
986 	struct mlx5_async_ctx *ctx;
987 	mlx5_async_cbk_t user_callback;
988 	u16 opcode; /* cmd opcode */
989 	u16 op_mod; /* cmd op_mod */
990 	void *out; /* pointer to the cmd output buffer */
991 };
992 
993 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
994 			     struct mlx5_async_ctx *ctx);
995 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
996 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
997 		     void *out, int out_size, mlx5_async_cbk_t callback,
998 		     struct mlx5_async_work *work);
999 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1000 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1001 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1002 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1003 		  int out_size);
1004 
1005 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1006 	({                                                                     \
1007 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1008 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1009 	})
1010 
1011 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1012 	({                                                                     \
1013 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1014 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1015 	})
1016 
1017 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1018 			  void *out, int out_size);
1019 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1020 
1021 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1022 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1023 
1024 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1025 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1026 int mlx5_health_init(struct mlx5_core_dev *dev);
1027 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1028 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1029 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1030 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1031 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1032 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1033 			     struct mlx5_frag_buf *buf, int node);
1034 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1035 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1036 						      gfp_t flags, int npages);
1037 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1038 				 struct mlx5_cmd_mailbox *head);
1039 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1040 			  int inlen);
1041 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1042 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1043 			 int outlen);
1044 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1045 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1046 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1047 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1048 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1049 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1050 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1051 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1052 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1053 				 s32 npages, bool ec_function);
1054 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1055 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1056 void mlx5_register_debugfs(void);
1057 void mlx5_unregister_debugfs(void);
1058 
1059 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1060 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1061 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1062 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1063 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1064 
1065 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1066 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1067 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1068 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1069 		    void *data_out, int size_out, u16 reg_id, int arg,
1070 		    int write, bool verbose);
1071 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1072 			 int size_in, void *data_out, int size_out,
1073 			 u16 reg_num, int arg, int write);
1074 
1075 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1076 		       int node);
1077 
1078 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1079 {
1080 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1081 }
1082 
1083 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1084 
1085 const char *mlx5_command_str(int command);
1086 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1087 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1088 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1089 			 int npsvs, u32 *sig_index);
1090 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1091 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1092 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1093 			struct mlx5_odp_caps *odp_caps);
1094 
1095 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1096 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1097 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1098 		     struct mlx5_rate_limit *rl);
1099 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1100 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1101 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1102 			 bool dedicated_entry, u16 *index);
1103 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1104 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1105 		       struct mlx5_rate_limit *rl_1);
1106 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1107 		     bool map_wc, bool fast_path);
1108 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1109 
1110 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1111 struct cpumask *
1112 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1113 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1114 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1115 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1116 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1117 
1118 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1119 {
1120 	return mkey >> 8;
1121 }
1122 
1123 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1124 {
1125 	return mkey_idx << 8;
1126 }
1127 
1128 static inline u8 mlx5_mkey_variant(u32 mkey)
1129 {
1130 	return mkey & 0xff;
1131 }
1132 
1133 /* Async-atomic event notifier used by mlx5 core to forward FW
1134  * evetns received from event queue to mlx5 consumers.
1135  * Optimise event queue dipatching.
1136  */
1137 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1138 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1139 
1140 /* Async-atomic event notifier used for forwarding
1141  * evetns from the event queue into the to mlx5 events dispatcher,
1142  * eswitch, clock and others.
1143  */
1144 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1145 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1146 
1147 /* Blocking event notifier used to forward SW events, used for slow path */
1148 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1149 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1150 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1151 				      void *data);
1152 
1153 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1154 
1155 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1156 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1157 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1158 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1159 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1160 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1161 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1162 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1163 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1164 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1165 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1166 			   struct net_device *slave);
1167 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1168 				 u64 *values,
1169 				 int num_counters,
1170 				 size_t *offsets);
1171 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1172 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1173 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1174 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1175 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1176 			 u64 length, u32 log_alignment, u16 uid,
1177 			 phys_addr_t *addr, u32 *obj_id);
1178 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1179 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1180 
1181 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1182 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1183 
1184 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1185 					  int vf_id,
1186 					  struct notifier_block *nb);
1187 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1188 					     int vf_id,
1189 					     struct notifier_block *nb);
1190 #ifdef CONFIG_MLX5_CORE_IPOIB
1191 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1192 					  struct ib_device *ibdev,
1193 					  const char *name,
1194 					  void (*setup)(struct net_device *));
1195 #endif /* CONFIG_MLX5_CORE_IPOIB */
1196 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1197 			    struct ib_device *device,
1198 			    struct rdma_netdev_alloc_params *params);
1199 
1200 enum {
1201 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1202 };
1203 
1204 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1205 {
1206 	return dev->coredev_type == MLX5_COREDEV_PF;
1207 }
1208 
1209 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1210 {
1211 	return dev->coredev_type == MLX5_COREDEV_VF;
1212 }
1213 
1214 static inline bool mlx5_core_is_management_pf(const struct mlx5_core_dev *dev)
1215 {
1216 	return MLX5_CAP_GEN(dev, num_ports) == 1 && !MLX5_CAP_GEN(dev, native_port_num);
1217 }
1218 
1219 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1220 {
1221 	return dev->caps.embedded_cpu;
1222 }
1223 
1224 static inline bool
1225 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1226 {
1227 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1228 }
1229 
1230 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1231 {
1232 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1233 }
1234 
1235 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1236 {
1237 	return dev->priv.sriov.max_vfs;
1238 }
1239 
1240 static inline int mlx5_get_gid_table_len(u16 param)
1241 {
1242 	if (param > 4) {
1243 		pr_warn("gid table length is zero\n");
1244 		return 0;
1245 	}
1246 
1247 	return 8 * (1 << param);
1248 }
1249 
1250 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1251 {
1252 	return !!(dev->priv.rl_table.max_size);
1253 }
1254 
1255 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1256 {
1257 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1258 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1259 }
1260 
1261 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1262 {
1263 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1264 }
1265 
1266 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1267 {
1268 	return mlx5_core_is_mp_slave(dev) ||
1269 	       mlx5_core_is_mp_master(dev);
1270 }
1271 
1272 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1273 {
1274 	if (!mlx5_core_mp_enabled(dev))
1275 		return 1;
1276 
1277 	return MLX5_CAP_GEN(dev, native_port_num);
1278 }
1279 
1280 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1281 {
1282 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1283 
1284 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1285 		return idx - 1;
1286 	else
1287 		return PCI_FUNC(dev->pdev->devfn);
1288 }
1289 
1290 enum {
1291 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1292 };
1293 
1294 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1295 
1296 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1297 {
1298 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1299 		return MLX5_CAP_GEN(dev, roce);
1300 
1301 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1302 	 * in order to support RoCE enable/disable feature
1303 	 */
1304 	return mlx5_is_roce_on(dev);
1305 }
1306 
1307 enum {
1308 	MLX5_OCTWORD = 16,
1309 };
1310 
1311 #endif /* MLX5_DRIVER_H */
1312