xref: /linux-6.15/include/linux/mlx5/driver.h (revision 6edf2e37) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
55 
56 enum {
57 	MLX5_BOARD_ID_LEN = 64,
58 	MLX5_MAX_NAME_LEN = 16,
59 };
60 
61 enum {
62 	/* one minute for the sake of bringup. Generally, commands must always
63 	 * complete and we may need to increase this timeout value
64 	 */
65 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
66 	MLX5_CMD_WQ_MAX_NAME	= 32,
67 };
68 
69 enum {
70 	CMD_OWNER_SW		= 0x0,
71 	CMD_OWNER_HW		= 0x1,
72 	CMD_STATUS_SUCCESS	= 0,
73 };
74 
75 enum mlx5_sqp_t {
76 	MLX5_SQP_SMI		= 0,
77 	MLX5_SQP_GSI		= 1,
78 	MLX5_SQP_IEEE_1588	= 2,
79 	MLX5_SQP_SNIFFER	= 3,
80 	MLX5_SQP_SYNC_UMR	= 4,
81 };
82 
83 enum {
84 	MLX5_MAX_PORTS	= 2,
85 };
86 
87 enum {
88 	MLX5_EQ_VEC_PAGES	 = 0,
89 	MLX5_EQ_VEC_CMD		 = 1,
90 	MLX5_EQ_VEC_ASYNC	 = 2,
91 	MLX5_EQ_VEC_PFAULT	 = 3,
92 	MLX5_EQ_VEC_COMP_BASE,
93 };
94 
95 enum {
96 	MLX5_MAX_IRQ_NAME	= 32
97 };
98 
99 enum {
100 	MLX5_ATOMIC_MODE_OFFSET = 16,
101 	MLX5_ATOMIC_MODE_IB_COMP = 1,
102 	MLX5_ATOMIC_MODE_CX = 2,
103 	MLX5_ATOMIC_MODE_8B = 3,
104 	MLX5_ATOMIC_MODE_16B = 4,
105 	MLX5_ATOMIC_MODE_32B = 5,
106 	MLX5_ATOMIC_MODE_64B = 6,
107 	MLX5_ATOMIC_MODE_128B = 7,
108 	MLX5_ATOMIC_MODE_256B = 8,
109 };
110 
111 enum {
112 	MLX5_REG_QPTS            = 0x4002,
113 	MLX5_REG_QETCR		 = 0x4005,
114 	MLX5_REG_QTCT		 = 0x400a,
115 	MLX5_REG_QPDPM           = 0x4013,
116 	MLX5_REG_QCAM            = 0x4019,
117 	MLX5_REG_DCBX_PARAM      = 0x4020,
118 	MLX5_REG_DCBX_APP        = 0x4021,
119 	MLX5_REG_FPGA_CAP	 = 0x4022,
120 	MLX5_REG_FPGA_CTRL	 = 0x4023,
121 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
122 	MLX5_REG_PCAP		 = 0x5001,
123 	MLX5_REG_PMTU		 = 0x5003,
124 	MLX5_REG_PTYS		 = 0x5004,
125 	MLX5_REG_PAOS		 = 0x5006,
126 	MLX5_REG_PFCC            = 0x5007,
127 	MLX5_REG_PPCNT		 = 0x5008,
128 	MLX5_REG_PPTB            = 0x500b,
129 	MLX5_REG_PBMC            = 0x500c,
130 	MLX5_REG_PMAOS		 = 0x5012,
131 	MLX5_REG_PUDE		 = 0x5009,
132 	MLX5_REG_PMPE		 = 0x5010,
133 	MLX5_REG_PELC		 = 0x500e,
134 	MLX5_REG_PVLC		 = 0x500f,
135 	MLX5_REG_PCMR		 = 0x5041,
136 	MLX5_REG_PMLP		 = 0x5002,
137 	MLX5_REG_PPLM		 = 0x5023,
138 	MLX5_REG_PCAM		 = 0x507f,
139 	MLX5_REG_NODE_DESC	 = 0x6001,
140 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
141 	MLX5_REG_MCIA		 = 0x9014,
142 	MLX5_REG_MLCR		 = 0x902b,
143 	MLX5_REG_MTRC_CAP	 = 0x9040,
144 	MLX5_REG_MTRC_CONF	 = 0x9041,
145 	MLX5_REG_MTRC_STDB	 = 0x9042,
146 	MLX5_REG_MTRC_CTRL	 = 0x9043,
147 	MLX5_REG_MPCNT		 = 0x9051,
148 	MLX5_REG_MTPPS		 = 0x9053,
149 	MLX5_REG_MTPPSE		 = 0x9054,
150 	MLX5_REG_MPEGC		 = 0x9056,
151 	MLX5_REG_MCQI		 = 0x9061,
152 	MLX5_REG_MCC		 = 0x9062,
153 	MLX5_REG_MCDA		 = 0x9063,
154 	MLX5_REG_MCAM		 = 0x907f,
155 };
156 
157 enum mlx5_qpts_trust_state {
158 	MLX5_QPTS_TRUST_PCP  = 1,
159 	MLX5_QPTS_TRUST_DSCP = 2,
160 };
161 
162 enum mlx5_dcbx_oper_mode {
163 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
164 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
165 };
166 
167 enum {
168 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
169 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
170 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
171 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
172 };
173 
174 enum mlx5_page_fault_resume_flags {
175 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
176 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
177 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
178 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
179 };
180 
181 enum dbg_rsc_type {
182 	MLX5_DBG_RSC_QP,
183 	MLX5_DBG_RSC_EQ,
184 	MLX5_DBG_RSC_CQ,
185 };
186 
187 enum port_state_policy {
188 	MLX5_POLICY_DOWN	= 0,
189 	MLX5_POLICY_UP		= 1,
190 	MLX5_POLICY_FOLLOW	= 2,
191 	MLX5_POLICY_INVALID	= 0xffffffff
192 };
193 
194 struct mlx5_field_desc {
195 	struct dentry	       *dent;
196 	int			i;
197 };
198 
199 struct mlx5_rsc_debug {
200 	struct mlx5_core_dev   *dev;
201 	void		       *object;
202 	enum dbg_rsc_type	type;
203 	struct dentry	       *root;
204 	struct mlx5_field_desc	fields[0];
205 };
206 
207 enum mlx5_dev_event {
208 	MLX5_DEV_EVENT_SYS_ERROR,
209 	MLX5_DEV_EVENT_PORT_UP,
210 	MLX5_DEV_EVENT_PORT_DOWN,
211 	MLX5_DEV_EVENT_PORT_INITIALIZED,
212 	MLX5_DEV_EVENT_LID_CHANGE,
213 	MLX5_DEV_EVENT_PKEY_CHANGE,
214 	MLX5_DEV_EVENT_GUID_CHANGE,
215 	MLX5_DEV_EVENT_CLIENT_REREG,
216 	MLX5_DEV_EVENT_PPS,
217 	MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
218 };
219 
220 enum mlx5_port_status {
221 	MLX5_PORT_UP        = 1,
222 	MLX5_PORT_DOWN      = 2,
223 };
224 
225 enum mlx5_eq_type {
226 	MLX5_EQ_TYPE_COMP,
227 	MLX5_EQ_TYPE_ASYNC,
228 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
229 	MLX5_EQ_TYPE_PF,
230 #endif
231 };
232 
233 struct mlx5_bfreg_info {
234 	u32		       *sys_pages;
235 	int			num_low_latency_bfregs;
236 	unsigned int	       *count;
237 
238 	/*
239 	 * protect bfreg allocation data structs
240 	 */
241 	struct mutex		lock;
242 	u32			ver;
243 	bool			lib_uar_4k;
244 	u32			num_sys_pages;
245 	u32			num_static_sys_pages;
246 	u32			total_num_bfregs;
247 	u32			num_dyn_bfregs;
248 };
249 
250 struct mlx5_cmd_first {
251 	__be32		data[4];
252 };
253 
254 struct mlx5_cmd_msg {
255 	struct list_head		list;
256 	struct cmd_msg_cache	       *parent;
257 	u32				len;
258 	struct mlx5_cmd_first		first;
259 	struct mlx5_cmd_mailbox	       *next;
260 };
261 
262 struct mlx5_cmd_debug {
263 	struct dentry	       *dbg_root;
264 	struct dentry	       *dbg_in;
265 	struct dentry	       *dbg_out;
266 	struct dentry	       *dbg_outlen;
267 	struct dentry	       *dbg_status;
268 	struct dentry	       *dbg_run;
269 	void		       *in_msg;
270 	void		       *out_msg;
271 	u8			status;
272 	u16			inlen;
273 	u16			outlen;
274 };
275 
276 struct cmd_msg_cache {
277 	/* protect block chain allocations
278 	 */
279 	spinlock_t		lock;
280 	struct list_head	head;
281 	unsigned int		max_inbox_size;
282 	unsigned int		num_ent;
283 };
284 
285 enum {
286 	MLX5_NUM_COMMAND_CACHES = 5,
287 };
288 
289 struct mlx5_cmd_stats {
290 	u64		sum;
291 	u64		n;
292 	struct dentry  *root;
293 	struct dentry  *avg;
294 	struct dentry  *count;
295 	/* protect command average calculations */
296 	spinlock_t	lock;
297 };
298 
299 struct mlx5_cmd {
300 	void	       *cmd_alloc_buf;
301 	dma_addr_t	alloc_dma;
302 	int		alloc_size;
303 	void	       *cmd_buf;
304 	dma_addr_t	dma;
305 	u16		cmdif_rev;
306 	u8		log_sz;
307 	u8		log_stride;
308 	int		max_reg_cmds;
309 	int		events;
310 	u32 __iomem    *vector;
311 
312 	/* protect command queue allocations
313 	 */
314 	spinlock_t	alloc_lock;
315 
316 	/* protect token allocations
317 	 */
318 	spinlock_t	token_lock;
319 	u8		token;
320 	unsigned long	bitmask;
321 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
322 	struct workqueue_struct *wq;
323 	struct semaphore sem;
324 	struct semaphore pages_sem;
325 	int	mode;
326 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
327 	struct dma_pool *pool;
328 	struct mlx5_cmd_debug dbg;
329 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
330 	int checksum_disabled;
331 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
332 };
333 
334 struct mlx5_port_caps {
335 	int	gid_table_len;
336 	int	pkey_table_len;
337 	u8	ext_port_cap;
338 	bool	has_smi;
339 };
340 
341 struct mlx5_cmd_mailbox {
342 	void	       *buf;
343 	dma_addr_t	dma;
344 	struct mlx5_cmd_mailbox *next;
345 };
346 
347 struct mlx5_buf_list {
348 	void		       *buf;
349 	dma_addr_t		map;
350 };
351 
352 struct mlx5_frag_buf {
353 	struct mlx5_buf_list	*frags;
354 	int			npages;
355 	int			size;
356 	u8			page_shift;
357 };
358 
359 struct mlx5_frag_buf_ctrl {
360 	struct mlx5_buf_list   *frags;
361 	u32			sz_m1;
362 	u16			frag_sz_m1;
363 	u16			strides_offset;
364 	u8			log_sz;
365 	u8			log_stride;
366 	u8			log_frag_strides;
367 };
368 
369 struct mlx5_eq_tasklet {
370 	struct list_head list;
371 	struct list_head process_list;
372 	struct tasklet_struct task;
373 	/* lock on completion tasklet list */
374 	spinlock_t lock;
375 };
376 
377 struct mlx5_eq_pagefault {
378 	struct work_struct       work;
379 	/* Pagefaults lock */
380 	spinlock_t		 lock;
381 	struct workqueue_struct *wq;
382 	mempool_t		*pool;
383 };
384 
385 struct mlx5_cq_table {
386 	/* protect radix tree */
387 	spinlock_t		lock;
388 	struct radix_tree_root	tree;
389 };
390 
391 struct mlx5_eq {
392 	struct mlx5_core_dev   *dev;
393 	struct mlx5_cq_table	cq_table;
394 	__be32 __iomem	       *doorbell;
395 	u32			cons_index;
396 	struct mlx5_frag_buf	buf;
397 	int			size;
398 	unsigned int		irqn;
399 	u8			eqn;
400 	int			nent;
401 	u64			mask;
402 	struct list_head	list;
403 	int			index;
404 	struct mlx5_rsc_debug	*dbg;
405 	enum mlx5_eq_type	type;
406 	union {
407 		struct mlx5_eq_tasklet   tasklet_ctx;
408 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
409 		struct mlx5_eq_pagefault pf_ctx;
410 #endif
411 	};
412 };
413 
414 struct mlx5_core_psv {
415 	u32	psv_idx;
416 	struct psv_layout {
417 		u32	pd;
418 		u16	syndrome;
419 		u16	reserved;
420 		u16	bg;
421 		u16	app_tag;
422 		u32	ref_tag;
423 	} psv;
424 };
425 
426 struct mlx5_core_sig_ctx {
427 	struct mlx5_core_psv	psv_memory;
428 	struct mlx5_core_psv	psv_wire;
429 	struct ib_sig_err       err_item;
430 	bool			sig_status_checked;
431 	bool			sig_err_exists;
432 	u32			sigerr_count;
433 };
434 
435 enum {
436 	MLX5_MKEY_MR = 1,
437 	MLX5_MKEY_MW,
438 };
439 
440 struct mlx5_core_mkey {
441 	u64			iova;
442 	u64			size;
443 	u32			key;
444 	u32			pd;
445 	u32			type;
446 };
447 
448 #define MLX5_24BIT_MASK		((1 << 24) - 1)
449 
450 enum mlx5_res_type {
451 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
452 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
453 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
454 	MLX5_RES_SRQ	= 3,
455 	MLX5_RES_XSRQ	= 4,
456 	MLX5_RES_XRQ	= 5,
457 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
458 };
459 
460 struct mlx5_core_rsc_common {
461 	enum mlx5_res_type	res;
462 	atomic_t		refcount;
463 	struct completion	free;
464 };
465 
466 struct mlx5_core_srq {
467 	struct mlx5_core_rsc_common	common; /* must be first */
468 	u32		srqn;
469 	int		max;
470 	size_t		max_gs;
471 	size_t		max_avail_gather;
472 	int		wqe_shift;
473 	void (*event)	(struct mlx5_core_srq *, enum mlx5_event);
474 
475 	atomic_t		refcount;
476 	struct completion	free;
477 	u16		uid;
478 };
479 
480 struct mlx5_eq_table {
481 	void __iomem	       *update_ci;
482 	void __iomem	       *update_arm_ci;
483 	struct list_head	comp_eqs_list;
484 	struct mlx5_eq		pages_eq;
485 	struct mlx5_eq		async_eq;
486 	struct mlx5_eq		cmd_eq;
487 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
488 	struct mlx5_eq		pfault_eq;
489 #endif
490 	int			num_comp_vectors;
491 	/* protect EQs list
492 	 */
493 	spinlock_t		lock;
494 };
495 
496 struct mlx5_uars_page {
497 	void __iomem	       *map;
498 	bool			wc;
499 	u32			index;
500 	struct list_head	list;
501 	unsigned int		bfregs;
502 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
503 	unsigned long	       *fp_bitmap;
504 	unsigned int		reg_avail;
505 	unsigned int		fp_avail;
506 	struct kref		ref_count;
507 	struct mlx5_core_dev   *mdev;
508 };
509 
510 struct mlx5_bfreg_head {
511 	/* protect blue flame registers allocations */
512 	struct mutex		lock;
513 	struct list_head	list;
514 };
515 
516 struct mlx5_bfreg_data {
517 	struct mlx5_bfreg_head	reg_head;
518 	struct mlx5_bfreg_head	wc_head;
519 };
520 
521 struct mlx5_sq_bfreg {
522 	void __iomem	       *map;
523 	struct mlx5_uars_page  *up;
524 	bool			wc;
525 	u32			index;
526 	unsigned int		offset;
527 };
528 
529 struct mlx5_core_health {
530 	struct health_buffer __iomem   *health;
531 	__be32 __iomem		       *health_counter;
532 	struct timer_list		timer;
533 	u32				prev;
534 	int				miss_counter;
535 	bool				sick;
536 	/* wq spinlock to synchronize draining */
537 	spinlock_t			wq_lock;
538 	struct workqueue_struct	       *wq;
539 	unsigned long			flags;
540 	struct work_struct		work;
541 	struct delayed_work		recover_work;
542 };
543 
544 struct mlx5_qp_table {
545 	/* protect radix tree
546 	 */
547 	spinlock_t		lock;
548 	struct radix_tree_root	tree;
549 };
550 
551 struct mlx5_srq_table {
552 	/* protect radix tree
553 	 */
554 	spinlock_t		lock;
555 	struct radix_tree_root	tree;
556 };
557 
558 struct mlx5_mkey_table {
559 	/* protect radix tree
560 	 */
561 	rwlock_t		lock;
562 	struct radix_tree_root	tree;
563 };
564 
565 struct mlx5_vf_context {
566 	int	enabled;
567 	u64	port_guid;
568 	u64	node_guid;
569 	enum port_state_policy	policy;
570 };
571 
572 struct mlx5_core_sriov {
573 	struct mlx5_vf_context	*vfs_ctx;
574 	int			num_vfs;
575 	int			enabled_vfs;
576 };
577 
578 struct mlx5_irq_info {
579 	cpumask_var_t mask;
580 	char name[MLX5_MAX_IRQ_NAME];
581 };
582 
583 struct mlx5_fc_stats {
584 	spinlock_t counters_idr_lock; /* protects counters_idr */
585 	struct idr counters_idr;
586 	struct list_head counters;
587 	struct llist_head addlist;
588 	struct llist_head dellist;
589 
590 	struct workqueue_struct *wq;
591 	struct delayed_work work;
592 	unsigned long next_query;
593 	unsigned long sampling_interval; /* jiffies */
594 };
595 
596 struct mlx5_mpfs;
597 struct mlx5_eswitch;
598 struct mlx5_lag;
599 struct mlx5_pagefault;
600 
601 struct mlx5_rate_limit {
602 	u32			rate;
603 	u32			max_burst_sz;
604 	u16			typical_pkt_sz;
605 };
606 
607 struct mlx5_rl_entry {
608 	struct mlx5_rate_limit	rl;
609 	u16                     index;
610 	u16                     refcount;
611 };
612 
613 struct mlx5_rl_table {
614 	/* protect rate limit table */
615 	struct mutex            rl_lock;
616 	u16                     max_size;
617 	u32                     max_rate;
618 	u32                     min_rate;
619 	struct mlx5_rl_entry   *rl_entry;
620 };
621 
622 enum port_module_event_status_type {
623 	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
624 	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
625 	MLX5_MODULE_STATUS_ERROR     = 0x3,
626 	MLX5_MODULE_STATUS_NUM       = 0x3,
627 };
628 
629 enum  port_module_event_error_type {
630 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
631 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
632 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
633 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
634 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
635 	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
636 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
637 	MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
638 	MLX5_MODULE_EVENT_ERROR_UNKNOWN,
639 	MLX5_MODULE_EVENT_ERROR_NUM,
640 };
641 
642 struct mlx5_port_module_event_stats {
643 	u64 status_counters[MLX5_MODULE_STATUS_NUM];
644 	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
645 };
646 
647 struct mlx5_priv {
648 	char			name[MLX5_MAX_NAME_LEN];
649 	struct mlx5_eq_table	eq_table;
650 	struct mlx5_irq_info	*irq_info;
651 
652 	/* pages stuff */
653 	struct workqueue_struct *pg_wq;
654 	struct rb_root		page_root;
655 	int			fw_pages;
656 	atomic_t		reg_pages;
657 	struct list_head	free_list;
658 	int			vfs_pages;
659 
660 	struct mlx5_core_health health;
661 
662 	struct mlx5_srq_table	srq_table;
663 
664 	/* start: qp staff */
665 	struct mlx5_qp_table	qp_table;
666 	struct dentry	       *qp_debugfs;
667 	struct dentry	       *eq_debugfs;
668 	struct dentry	       *cq_debugfs;
669 	struct dentry	       *cmdif_debugfs;
670 	/* end: qp staff */
671 
672 	/* start: mkey staff */
673 	struct mlx5_mkey_table	mkey_table;
674 	/* end: mkey staff */
675 
676 	/* start: alloc staff */
677 	/* protect buffer alocation according to numa node */
678 	struct mutex            alloc_mutex;
679 	int                     numa_node;
680 
681 	struct mutex            pgdir_mutex;
682 	struct list_head        pgdir_list;
683 	/* end: alloc staff */
684 	struct dentry	       *dbg_root;
685 
686 	/* protect mkey key part */
687 	spinlock_t		mkey_lock;
688 	u8			mkey_key;
689 
690 	struct list_head        dev_list;
691 	struct list_head        ctx_list;
692 	spinlock_t              ctx_lock;
693 
694 	struct list_head	waiting_events_list;
695 	bool			is_accum_events;
696 
697 	struct mlx5_flow_steering *steering;
698 	struct mlx5_mpfs        *mpfs;
699 	struct mlx5_eswitch     *eswitch;
700 	struct mlx5_core_sriov	sriov;
701 	struct mlx5_lag		*lag;
702 	unsigned long		pci_dev_data;
703 	struct mlx5_fc_stats		fc_stats;
704 	struct mlx5_rl_table            rl_table;
705 
706 	struct mlx5_port_module_event_stats  pme_stats;
707 
708 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
709 	void		      (*pfault)(struct mlx5_core_dev *dev,
710 					void *context,
711 					struct mlx5_pagefault *pfault);
712 	void		       *pfault_ctx;
713 	struct srcu_struct      pfault_srcu;
714 #endif
715 	struct mlx5_bfreg_data		bfregs;
716 	struct mlx5_uars_page	       *uar;
717 };
718 
719 enum mlx5_device_state {
720 	MLX5_DEVICE_STATE_UP,
721 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
722 };
723 
724 enum mlx5_interface_state {
725 	MLX5_INTERFACE_STATE_UP = BIT(0),
726 };
727 
728 enum mlx5_pci_status {
729 	MLX5_PCI_STATUS_DISABLED,
730 	MLX5_PCI_STATUS_ENABLED,
731 };
732 
733 enum mlx5_pagefault_type_flags {
734 	MLX5_PFAULT_REQUESTOR = 1 << 0,
735 	MLX5_PFAULT_WRITE     = 1 << 1,
736 	MLX5_PFAULT_RDMA      = 1 << 2,
737 };
738 
739 /* Contains the details of a pagefault. */
740 struct mlx5_pagefault {
741 	u32			bytes_committed;
742 	u32			token;
743 	u8			event_subtype;
744 	u8			type;
745 	union {
746 		/* Initiator or send message responder pagefault details. */
747 		struct {
748 			/* Received packet size, only valid for responders. */
749 			u32	packet_size;
750 			/*
751 			 * Number of resource holding WQE, depends on type.
752 			 */
753 			u32	wq_num;
754 			/*
755 			 * WQE index. Refers to either the send queue or
756 			 * receive queue, according to event_subtype.
757 			 */
758 			u16	wqe_index;
759 		} wqe;
760 		/* RDMA responder pagefault details */
761 		struct {
762 			u32	r_key;
763 			/*
764 			 * Received packet size, minimal size page fault
765 			 * resolution required for forward progress.
766 			 */
767 			u32	packet_size;
768 			u32	rdma_op_len;
769 			u64	rdma_va;
770 		} rdma;
771 	};
772 
773 	struct mlx5_eq	       *eq;
774 	struct work_struct	work;
775 };
776 
777 struct mlx5_td {
778 	struct list_head tirs_list;
779 	u32              tdn;
780 };
781 
782 struct mlx5e_resources {
783 	u32                        pdn;
784 	struct mlx5_td             td;
785 	struct mlx5_core_mkey      mkey;
786 	struct mlx5_sq_bfreg       bfreg;
787 };
788 
789 #define MLX5_MAX_RESERVED_GIDS 8
790 
791 struct mlx5_rsvd_gids {
792 	unsigned int start;
793 	unsigned int count;
794 	struct ida ida;
795 };
796 
797 #define MAX_PIN_NUM	8
798 struct mlx5_pps {
799 	u8                         pin_caps[MAX_PIN_NUM];
800 	struct work_struct         out_work;
801 	u64                        start[MAX_PIN_NUM];
802 	u8                         enabled;
803 };
804 
805 struct mlx5_clock {
806 	seqlock_t                  lock;
807 	struct cyclecounter        cycles;
808 	struct timecounter         tc;
809 	struct hwtstamp_config     hwtstamp_config;
810 	u32                        nominal_c_mult;
811 	unsigned long              overflow_period;
812 	struct delayed_work        overflow_work;
813 	struct mlx5_core_dev      *mdev;
814 	struct ptp_clock          *ptp;
815 	struct ptp_clock_info      ptp_info;
816 	struct mlx5_pps            pps_info;
817 };
818 
819 struct mlx5_fw_tracer;
820 struct mlx5_vxlan;
821 
822 struct mlx5_core_dev {
823 	struct pci_dev	       *pdev;
824 	/* sync pci state */
825 	struct mutex		pci_status_mutex;
826 	enum mlx5_pci_status	pci_status;
827 	u8			rev_id;
828 	char			board_id[MLX5_BOARD_ID_LEN];
829 	struct mlx5_cmd		cmd;
830 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
831 	struct {
832 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
833 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
834 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
835 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
836 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
837 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
838 	} caps;
839 	u64			sys_image_guid;
840 	phys_addr_t		iseg_base;
841 	struct mlx5_init_seg __iomem *iseg;
842 	enum mlx5_device_state	state;
843 	/* sync interface state */
844 	struct mutex		intf_state_mutex;
845 	unsigned long		intf_state;
846 	void			(*event) (struct mlx5_core_dev *dev,
847 					  enum mlx5_dev_event event,
848 					  unsigned long param);
849 	struct mlx5_priv	priv;
850 	struct mlx5_profile	*profile;
851 	atomic_t		num_qps;
852 	u32			issi;
853 	struct mlx5e_resources  mlx5e_res;
854 	struct mlx5_vxlan       *vxlan;
855 	struct {
856 		struct mlx5_rsvd_gids	reserved_gids;
857 		u32			roce_en;
858 	} roce;
859 #ifdef CONFIG_MLX5_FPGA
860 	struct mlx5_fpga_device *fpga;
861 #endif
862 #ifdef CONFIG_RFS_ACCEL
863 	struct cpu_rmap         *rmap;
864 #endif
865 	struct mlx5_clock        clock;
866 	struct mlx5_ib_clock_info  *clock_info;
867 	struct page             *clock_info_page;
868 	struct mlx5_fw_tracer   *tracer;
869 };
870 
871 struct mlx5_db {
872 	__be32			*db;
873 	union {
874 		struct mlx5_db_pgdir		*pgdir;
875 		struct mlx5_ib_user_db_page	*user_page;
876 	}			u;
877 	dma_addr_t		dma;
878 	int			index;
879 };
880 
881 enum {
882 	MLX5_COMP_EQ_SIZE = 1024,
883 };
884 
885 enum {
886 	MLX5_PTYS_IB = 1 << 0,
887 	MLX5_PTYS_EN = 1 << 2,
888 };
889 
890 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
891 
892 enum {
893 	MLX5_CMD_ENT_STATE_PENDING_COMP,
894 };
895 
896 struct mlx5_cmd_work_ent {
897 	unsigned long		state;
898 	struct mlx5_cmd_msg    *in;
899 	struct mlx5_cmd_msg    *out;
900 	void		       *uout;
901 	int			uout_size;
902 	mlx5_cmd_cbk_t		callback;
903 	struct delayed_work	cb_timeout_work;
904 	void		       *context;
905 	int			idx;
906 	struct completion	done;
907 	struct mlx5_cmd        *cmd;
908 	struct work_struct	work;
909 	struct mlx5_cmd_layout *lay;
910 	int			ret;
911 	int			page_queue;
912 	u8			status;
913 	u8			token;
914 	u64			ts1;
915 	u64			ts2;
916 	u16			op;
917 	bool			polling;
918 };
919 
920 struct mlx5_pas {
921 	u64	pa;
922 	u8	log_sz;
923 };
924 
925 enum phy_port_state {
926 	MLX5_AAA_111
927 };
928 
929 struct mlx5_hca_vport_context {
930 	u32			field_select;
931 	bool			sm_virt_aware;
932 	bool			has_smi;
933 	bool			has_raw;
934 	enum port_state_policy	policy;
935 	enum phy_port_state	phys_state;
936 	enum ib_port_state	vport_state;
937 	u8			port_physical_state;
938 	u64			sys_image_guid;
939 	u64			port_guid;
940 	u64			node_guid;
941 	u32			cap_mask1;
942 	u32			cap_mask1_perm;
943 	u32			cap_mask2;
944 	u32			cap_mask2_perm;
945 	u16			lid;
946 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
947 	u8			lmc;
948 	u8			subnet_timeout;
949 	u16			sm_lid;
950 	u8			sm_sl;
951 	u16			qkey_violation_counter;
952 	u16			pkey_violation_counter;
953 	bool			grh_required;
954 };
955 
956 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
957 {
958 		return buf->frags->buf + offset;
959 }
960 
961 #define STRUCT_FIELD(header, field) \
962 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
963 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
964 
965 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
966 {
967 	return pci_get_drvdata(pdev);
968 }
969 
970 extern struct dentry *mlx5_debugfs_root;
971 
972 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
973 {
974 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
975 }
976 
977 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
978 {
979 	return ioread32be(&dev->iseg->fw_rev) >> 16;
980 }
981 
982 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
983 {
984 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
985 }
986 
987 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
988 {
989 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
990 }
991 
992 static inline u32 mlx5_base_mkey(const u32 key)
993 {
994 	return key & 0xffffff00u;
995 }
996 
997 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
998 					u8 log_stride, u8 log_sz,
999 					u16 strides_offset,
1000 					struct mlx5_frag_buf_ctrl *fbc)
1001 {
1002 	fbc->frags      = frags;
1003 	fbc->log_stride = log_stride;
1004 	fbc->log_sz     = log_sz;
1005 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
1006 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
1007 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
1008 	fbc->strides_offset = strides_offset;
1009 }
1010 
1011 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
1012 				 u8 log_stride, u8 log_sz,
1013 				 struct mlx5_frag_buf_ctrl *fbc)
1014 {
1015 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
1016 }
1017 
1018 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
1019 					  u32 ix)
1020 {
1021 	unsigned int frag;
1022 
1023 	ix  += fbc->strides_offset;
1024 	frag = ix >> fbc->log_frag_strides;
1025 
1026 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
1027 }
1028 
1029 static inline u32
1030 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
1031 {
1032 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
1033 
1034 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
1035 }
1036 
1037 int mlx5_cmd_init(struct mlx5_core_dev *dev);
1038 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
1039 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
1040 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
1041 
1042 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1043 		  int out_size);
1044 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1045 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
1046 		     void *context);
1047 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1048 			  void *out, int out_size);
1049 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
1050 
1051 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1052 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1053 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1054 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1055 int mlx5_health_init(struct mlx5_core_dev *dev);
1056 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1057 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1058 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1059 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1060 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1061 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1062 			struct mlx5_frag_buf *buf, int node);
1063 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1064 		   int size, struct mlx5_frag_buf *buf);
1065 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1066 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1067 			     struct mlx5_frag_buf *buf, int node);
1068 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1069 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1070 						      gfp_t flags, int npages);
1071 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1072 				 struct mlx5_cmd_mailbox *head);
1073 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1074 			 struct mlx5_srq_attr *in);
1075 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1076 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1077 			struct mlx5_srq_attr *out);
1078 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1079 		      u16 lwm, int is_srq);
1080 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1081 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1082 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1083 			     struct mlx5_core_mkey *mkey,
1084 			     u32 *in, int inlen,
1085 			     u32 *out, int outlen,
1086 			     mlx5_cmd_cbk_t callback, void *context);
1087 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1088 			  struct mlx5_core_mkey *mkey,
1089 			  u32 *in, int inlen);
1090 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1091 			   struct mlx5_core_mkey *mkey);
1092 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1093 			 u32 *out, int outlen);
1094 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1095 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1096 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1097 		      u16 opmod, u8 port);
1098 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1099 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1100 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1101 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1102 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1103 				 s32 npages);
1104 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1105 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1106 void mlx5_register_debugfs(void);
1107 void mlx5_unregister_debugfs(void);
1108 
1109 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1110 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1111 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1112 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1113 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1114 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1115 		    unsigned int *irqn);
1116 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1117 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1118 
1119 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1120 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1121 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1122 			 int size_in, void *data_out, int size_out,
1123 			 u16 reg_num, int arg, int write);
1124 
1125 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1126 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1127 		       int node);
1128 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1129 
1130 const char *mlx5_command_str(int command);
1131 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1132 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1133 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1134 			 int npsvs, u32 *sig_index);
1135 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1136 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1137 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1138 			struct mlx5_odp_caps *odp_caps);
1139 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1140 			     u8 port_num, void *out, size_t sz);
1141 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1142 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1143 				u32 wq_num, u8 type, int error);
1144 #endif
1145 
1146 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1147 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1148 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1149 		     struct mlx5_rate_limit *rl);
1150 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1151 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1152 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1153 		       struct mlx5_rate_limit *rl_1);
1154 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1155 		     bool map_wc, bool fast_path);
1156 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1157 
1158 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1159 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1160 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1161 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1162 
1163 static inline int fw_initializing(struct mlx5_core_dev *dev)
1164 {
1165 	return ioread32be(&dev->iseg->initializing) >> 31;
1166 }
1167 
1168 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1169 {
1170 	return mkey >> 8;
1171 }
1172 
1173 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1174 {
1175 	return mkey_idx << 8;
1176 }
1177 
1178 static inline u8 mlx5_mkey_variant(u32 mkey)
1179 {
1180 	return mkey & 0xff;
1181 }
1182 
1183 enum {
1184 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1185 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1186 };
1187 
1188 enum {
1189 	MR_CACHE_LAST_STD_ENTRY = 20,
1190 	MLX5_IMR_MTT_CACHE_ENTRY,
1191 	MLX5_IMR_KSM_CACHE_ENTRY,
1192 	MAX_MR_CACHE_ENTRIES
1193 };
1194 
1195 enum {
1196 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1197 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1198 };
1199 
1200 struct mlx5_interface {
1201 	void *			(*add)(struct mlx5_core_dev *dev);
1202 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1203 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1204 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1205 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1206 					 enum mlx5_dev_event event, unsigned long param);
1207 	void			(*pfault)(struct mlx5_core_dev *dev,
1208 					  void *context,
1209 					  struct mlx5_pagefault *pfault);
1210 	void *                  (*get_dev)(void *context);
1211 	int			protocol;
1212 	struct list_head	list;
1213 };
1214 
1215 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1216 int mlx5_register_interface(struct mlx5_interface *intf);
1217 void mlx5_unregister_interface(struct mlx5_interface *intf);
1218 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1219 
1220 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1221 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1222 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1223 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1224 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1225 				 u64 *values,
1226 				 int num_counters,
1227 				 size_t *offsets);
1228 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1229 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1230 
1231 #ifdef CONFIG_MLX5_CORE_IPOIB
1232 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1233 					  struct ib_device *ibdev,
1234 					  const char *name,
1235 					  void (*setup)(struct net_device *));
1236 #endif /* CONFIG_MLX5_CORE_IPOIB */
1237 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1238 			    struct ib_device *device,
1239 			    struct rdma_netdev_alloc_params *params);
1240 
1241 struct mlx5_profile {
1242 	u64	mask;
1243 	u8	log_max_qp;
1244 	struct {
1245 		int	size;
1246 		int	limit;
1247 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1248 };
1249 
1250 enum {
1251 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1252 };
1253 
1254 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1255 {
1256 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1257 }
1258 
1259 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1260 #define MLX5_VPORT_MANAGER(mdev) \
1261 	(MLX5_CAP_GEN(mdev, vport_group_manager) && \
1262 	 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1263 	 mlx5_core_is_pf(mdev))
1264 
1265 static inline int mlx5_get_gid_table_len(u16 param)
1266 {
1267 	if (param > 4) {
1268 		pr_warn("gid table length is zero\n");
1269 		return 0;
1270 	}
1271 
1272 	return 8 * (1 << param);
1273 }
1274 
1275 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1276 {
1277 	return !!(dev->priv.rl_table.max_size);
1278 }
1279 
1280 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1281 {
1282 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1283 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1284 }
1285 
1286 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1287 {
1288 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1289 }
1290 
1291 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1292 {
1293 	return mlx5_core_is_mp_slave(dev) ||
1294 	       mlx5_core_is_mp_master(dev);
1295 }
1296 
1297 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1298 {
1299 	if (!mlx5_core_mp_enabled(dev))
1300 		return 1;
1301 
1302 	return MLX5_CAP_GEN(dev, native_port_num);
1303 }
1304 
1305 enum {
1306 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1307 };
1308 
1309 static inline const struct cpumask *
1310 mlx5_get_vector_affinity_hint(struct mlx5_core_dev *dev, int vector)
1311 {
1312 	return dev->priv.irq_info[vector].mask;
1313 }
1314 
1315 #endif /* MLX5_DRIVER_H */
1316