xref: /linux-6.15/include/linux/mlx5/driver.h (revision 5ecd9d40) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 
50 #include <linux/mlx5/device.h>
51 #include <linux/mlx5/doorbell.h>
52 #include <linux/mlx5/srq.h>
53 #include <linux/timecounter.h>
54 #include <linux/ptp_clock_kernel.h>
55 
56 enum {
57 	MLX5_BOARD_ID_LEN = 64,
58 	MLX5_MAX_NAME_LEN = 16,
59 };
60 
61 enum {
62 	/* one minute for the sake of bringup. Generally, commands must always
63 	 * complete and we may need to increase this timeout value
64 	 */
65 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
66 	MLX5_CMD_WQ_MAX_NAME	= 32,
67 };
68 
69 enum {
70 	CMD_OWNER_SW		= 0x0,
71 	CMD_OWNER_HW		= 0x1,
72 	CMD_STATUS_SUCCESS	= 0,
73 };
74 
75 enum mlx5_sqp_t {
76 	MLX5_SQP_SMI		= 0,
77 	MLX5_SQP_GSI		= 1,
78 	MLX5_SQP_IEEE_1588	= 2,
79 	MLX5_SQP_SNIFFER	= 3,
80 	MLX5_SQP_SYNC_UMR	= 4,
81 };
82 
83 enum {
84 	MLX5_MAX_PORTS	= 2,
85 };
86 
87 enum {
88 	MLX5_EQ_VEC_PAGES	 = 0,
89 	MLX5_EQ_VEC_CMD		 = 1,
90 	MLX5_EQ_VEC_ASYNC	 = 2,
91 	MLX5_EQ_VEC_PFAULT	 = 3,
92 	MLX5_EQ_VEC_COMP_BASE,
93 };
94 
95 enum {
96 	MLX5_MAX_IRQ_NAME	= 32
97 };
98 
99 enum {
100 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << 16,
101 	MLX5_ATOMIC_MODE_CX		= 2 << 16,
102 	MLX5_ATOMIC_MODE_8B		= 3 << 16,
103 	MLX5_ATOMIC_MODE_16B		= 4 << 16,
104 	MLX5_ATOMIC_MODE_32B		= 5 << 16,
105 	MLX5_ATOMIC_MODE_64B		= 6 << 16,
106 	MLX5_ATOMIC_MODE_128B		= 7 << 16,
107 	MLX5_ATOMIC_MODE_256B		= 8 << 16,
108 };
109 
110 enum {
111 	MLX5_REG_QPTS            = 0x4002,
112 	MLX5_REG_QETCR		 = 0x4005,
113 	MLX5_REG_QTCT		 = 0x400a,
114 	MLX5_REG_QPDPM           = 0x4013,
115 	MLX5_REG_QCAM            = 0x4019,
116 	MLX5_REG_DCBX_PARAM      = 0x4020,
117 	MLX5_REG_DCBX_APP        = 0x4021,
118 	MLX5_REG_FPGA_CAP	 = 0x4022,
119 	MLX5_REG_FPGA_CTRL	 = 0x4023,
120 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
121 	MLX5_REG_PCAP		 = 0x5001,
122 	MLX5_REG_PMTU		 = 0x5003,
123 	MLX5_REG_PTYS		 = 0x5004,
124 	MLX5_REG_PAOS		 = 0x5006,
125 	MLX5_REG_PFCC            = 0x5007,
126 	MLX5_REG_PPCNT		 = 0x5008,
127 	MLX5_REG_PMAOS		 = 0x5012,
128 	MLX5_REG_PUDE		 = 0x5009,
129 	MLX5_REG_PMPE		 = 0x5010,
130 	MLX5_REG_PELC		 = 0x500e,
131 	MLX5_REG_PVLC		 = 0x500f,
132 	MLX5_REG_PCMR		 = 0x5041,
133 	MLX5_REG_PMLP		 = 0x5002,
134 	MLX5_REG_PCAM		 = 0x507f,
135 	MLX5_REG_NODE_DESC	 = 0x6001,
136 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 	MLX5_REG_MCIA		 = 0x9014,
138 	MLX5_REG_MLCR		 = 0x902b,
139 	MLX5_REG_MPCNT		 = 0x9051,
140 	MLX5_REG_MTPPS		 = 0x9053,
141 	MLX5_REG_MTPPSE		 = 0x9054,
142 	MLX5_REG_MCQI		 = 0x9061,
143 	MLX5_REG_MCC		 = 0x9062,
144 	MLX5_REG_MCDA		 = 0x9063,
145 	MLX5_REG_MCAM		 = 0x907f,
146 };
147 
148 enum mlx5_qpts_trust_state {
149 	MLX5_QPTS_TRUST_PCP  = 1,
150 	MLX5_QPTS_TRUST_DSCP = 2,
151 };
152 
153 enum mlx5_dcbx_oper_mode {
154 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
155 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
156 };
157 
158 enum mlx5_dct_atomic_mode {
159 	MLX5_ATOMIC_MODE_DCT_OFF        = 20,
160 	MLX5_ATOMIC_MODE_DCT_NONE       = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
161 	MLX5_ATOMIC_MODE_DCT_IB_COMP    = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
162 	MLX5_ATOMIC_MODE_DCT_CX         = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
163 };
164 
165 enum {
166 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
167 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
168 };
169 
170 enum mlx5_page_fault_resume_flags {
171 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
172 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
173 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
174 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
175 };
176 
177 enum dbg_rsc_type {
178 	MLX5_DBG_RSC_QP,
179 	MLX5_DBG_RSC_EQ,
180 	MLX5_DBG_RSC_CQ,
181 };
182 
183 enum port_state_policy {
184 	MLX5_POLICY_DOWN	= 0,
185 	MLX5_POLICY_UP		= 1,
186 	MLX5_POLICY_FOLLOW	= 2,
187 	MLX5_POLICY_INVALID	= 0xffffffff
188 };
189 
190 struct mlx5_field_desc {
191 	struct dentry	       *dent;
192 	int			i;
193 };
194 
195 struct mlx5_rsc_debug {
196 	struct mlx5_core_dev   *dev;
197 	void		       *object;
198 	enum dbg_rsc_type	type;
199 	struct dentry	       *root;
200 	struct mlx5_field_desc	fields[0];
201 };
202 
203 enum mlx5_dev_event {
204 	MLX5_DEV_EVENT_SYS_ERROR,
205 	MLX5_DEV_EVENT_PORT_UP,
206 	MLX5_DEV_EVENT_PORT_DOWN,
207 	MLX5_DEV_EVENT_PORT_INITIALIZED,
208 	MLX5_DEV_EVENT_LID_CHANGE,
209 	MLX5_DEV_EVENT_PKEY_CHANGE,
210 	MLX5_DEV_EVENT_GUID_CHANGE,
211 	MLX5_DEV_EVENT_CLIENT_REREG,
212 	MLX5_DEV_EVENT_PPS,
213 	MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT,
214 };
215 
216 enum mlx5_port_status {
217 	MLX5_PORT_UP        = 1,
218 	MLX5_PORT_DOWN      = 2,
219 };
220 
221 enum mlx5_eq_type {
222 	MLX5_EQ_TYPE_COMP,
223 	MLX5_EQ_TYPE_ASYNC,
224 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
225 	MLX5_EQ_TYPE_PF,
226 #endif
227 };
228 
229 struct mlx5_bfreg_info {
230 	u32		       *sys_pages;
231 	int			num_low_latency_bfregs;
232 	unsigned int	       *count;
233 
234 	/*
235 	 * protect bfreg allocation data structs
236 	 */
237 	struct mutex		lock;
238 	u32			ver;
239 	bool			lib_uar_4k;
240 	u32			num_sys_pages;
241 	u32			num_static_sys_pages;
242 	u32			total_num_bfregs;
243 	u32			num_dyn_bfregs;
244 };
245 
246 struct mlx5_cmd_first {
247 	__be32		data[4];
248 };
249 
250 struct mlx5_cmd_msg {
251 	struct list_head		list;
252 	struct cmd_msg_cache	       *parent;
253 	u32				len;
254 	struct mlx5_cmd_first		first;
255 	struct mlx5_cmd_mailbox	       *next;
256 };
257 
258 struct mlx5_cmd_debug {
259 	struct dentry	       *dbg_root;
260 	struct dentry	       *dbg_in;
261 	struct dentry	       *dbg_out;
262 	struct dentry	       *dbg_outlen;
263 	struct dentry	       *dbg_status;
264 	struct dentry	       *dbg_run;
265 	void		       *in_msg;
266 	void		       *out_msg;
267 	u8			status;
268 	u16			inlen;
269 	u16			outlen;
270 };
271 
272 struct cmd_msg_cache {
273 	/* protect block chain allocations
274 	 */
275 	spinlock_t		lock;
276 	struct list_head	head;
277 	unsigned int		max_inbox_size;
278 	unsigned int		num_ent;
279 };
280 
281 enum {
282 	MLX5_NUM_COMMAND_CACHES = 5,
283 };
284 
285 struct mlx5_cmd_stats {
286 	u64		sum;
287 	u64		n;
288 	struct dentry  *root;
289 	struct dentry  *avg;
290 	struct dentry  *count;
291 	/* protect command average calculations */
292 	spinlock_t	lock;
293 };
294 
295 struct mlx5_cmd {
296 	void	       *cmd_alloc_buf;
297 	dma_addr_t	alloc_dma;
298 	int		alloc_size;
299 	void	       *cmd_buf;
300 	dma_addr_t	dma;
301 	u16		cmdif_rev;
302 	u8		log_sz;
303 	u8		log_stride;
304 	int		max_reg_cmds;
305 	int		events;
306 	u32 __iomem    *vector;
307 
308 	/* protect command queue allocations
309 	 */
310 	spinlock_t	alloc_lock;
311 
312 	/* protect token allocations
313 	 */
314 	spinlock_t	token_lock;
315 	u8		token;
316 	unsigned long	bitmask;
317 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
318 	struct workqueue_struct *wq;
319 	struct semaphore sem;
320 	struct semaphore pages_sem;
321 	int	mode;
322 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
323 	struct dma_pool *pool;
324 	struct mlx5_cmd_debug dbg;
325 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
326 	int checksum_disabled;
327 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
328 };
329 
330 struct mlx5_port_caps {
331 	int	gid_table_len;
332 	int	pkey_table_len;
333 	u8	ext_port_cap;
334 	bool	has_smi;
335 };
336 
337 struct mlx5_cmd_mailbox {
338 	void	       *buf;
339 	dma_addr_t	dma;
340 	struct mlx5_cmd_mailbox *next;
341 };
342 
343 struct mlx5_buf_list {
344 	void		       *buf;
345 	dma_addr_t		map;
346 };
347 
348 struct mlx5_frag_buf {
349 	struct mlx5_buf_list	*frags;
350 	int			npages;
351 	int			size;
352 	u8			page_shift;
353 };
354 
355 struct mlx5_frag_buf_ctrl {
356 	struct mlx5_frag_buf	frag_buf;
357 	u32			sz_m1;
358 	u32			frag_sz_m1;
359 	u8			log_sz;
360 	u8			log_stride;
361 	u8			log_frag_strides;
362 };
363 
364 struct mlx5_eq_tasklet {
365 	struct list_head list;
366 	struct list_head process_list;
367 	struct tasklet_struct task;
368 	/* lock on completion tasklet list */
369 	spinlock_t lock;
370 };
371 
372 struct mlx5_eq_pagefault {
373 	struct work_struct       work;
374 	/* Pagefaults lock */
375 	spinlock_t		 lock;
376 	struct workqueue_struct *wq;
377 	mempool_t		*pool;
378 };
379 
380 struct mlx5_cq_table {
381 	/* protect radix tree */
382 	spinlock_t		lock;
383 	struct radix_tree_root	tree;
384 };
385 
386 struct mlx5_eq {
387 	struct mlx5_core_dev   *dev;
388 	struct mlx5_cq_table	cq_table;
389 	__be32 __iomem	       *doorbell;
390 	u32			cons_index;
391 	struct mlx5_frag_buf	buf;
392 	int			size;
393 	unsigned int		irqn;
394 	u8			eqn;
395 	int			nent;
396 	u64			mask;
397 	struct list_head	list;
398 	int			index;
399 	struct mlx5_rsc_debug	*dbg;
400 	enum mlx5_eq_type	type;
401 	union {
402 		struct mlx5_eq_tasklet   tasklet_ctx;
403 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
404 		struct mlx5_eq_pagefault pf_ctx;
405 #endif
406 	};
407 };
408 
409 struct mlx5_core_psv {
410 	u32	psv_idx;
411 	struct psv_layout {
412 		u32	pd;
413 		u16	syndrome;
414 		u16	reserved;
415 		u16	bg;
416 		u16	app_tag;
417 		u32	ref_tag;
418 	} psv;
419 };
420 
421 struct mlx5_core_sig_ctx {
422 	struct mlx5_core_psv	psv_memory;
423 	struct mlx5_core_psv	psv_wire;
424 	struct ib_sig_err       err_item;
425 	bool			sig_status_checked;
426 	bool			sig_err_exists;
427 	u32			sigerr_count;
428 };
429 
430 enum {
431 	MLX5_MKEY_MR = 1,
432 	MLX5_MKEY_MW,
433 };
434 
435 struct mlx5_core_mkey {
436 	u64			iova;
437 	u64			size;
438 	u32			key;
439 	u32			pd;
440 	u32			type;
441 };
442 
443 #define MLX5_24BIT_MASK		((1 << 24) - 1)
444 
445 enum mlx5_res_type {
446 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
447 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
448 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
449 	MLX5_RES_SRQ	= 3,
450 	MLX5_RES_XSRQ	= 4,
451 	MLX5_RES_XRQ	= 5,
452 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
453 };
454 
455 struct mlx5_core_rsc_common {
456 	enum mlx5_res_type	res;
457 	atomic_t		refcount;
458 	struct completion	free;
459 };
460 
461 struct mlx5_core_srq {
462 	struct mlx5_core_rsc_common	common; /* must be first */
463 	u32		srqn;
464 	int		max;
465 	size_t		max_gs;
466 	size_t		max_avail_gather;
467 	int		wqe_shift;
468 	void (*event)	(struct mlx5_core_srq *, enum mlx5_event);
469 
470 	atomic_t		refcount;
471 	struct completion	free;
472 };
473 
474 struct mlx5_eq_table {
475 	void __iomem	       *update_ci;
476 	void __iomem	       *update_arm_ci;
477 	struct list_head	comp_eqs_list;
478 	struct mlx5_eq		pages_eq;
479 	struct mlx5_eq		async_eq;
480 	struct mlx5_eq		cmd_eq;
481 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
482 	struct mlx5_eq		pfault_eq;
483 #endif
484 	int			num_comp_vectors;
485 	/* protect EQs list
486 	 */
487 	spinlock_t		lock;
488 };
489 
490 struct mlx5_uars_page {
491 	void __iomem	       *map;
492 	bool			wc;
493 	u32			index;
494 	struct list_head	list;
495 	unsigned int		bfregs;
496 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
497 	unsigned long	       *fp_bitmap;
498 	unsigned int		reg_avail;
499 	unsigned int		fp_avail;
500 	struct kref		ref_count;
501 	struct mlx5_core_dev   *mdev;
502 };
503 
504 struct mlx5_bfreg_head {
505 	/* protect blue flame registers allocations */
506 	struct mutex		lock;
507 	struct list_head	list;
508 };
509 
510 struct mlx5_bfreg_data {
511 	struct mlx5_bfreg_head	reg_head;
512 	struct mlx5_bfreg_head	wc_head;
513 };
514 
515 struct mlx5_sq_bfreg {
516 	void __iomem	       *map;
517 	struct mlx5_uars_page  *up;
518 	bool			wc;
519 	u32			index;
520 	unsigned int		offset;
521 };
522 
523 struct mlx5_core_health {
524 	struct health_buffer __iomem   *health;
525 	__be32 __iomem		       *health_counter;
526 	struct timer_list		timer;
527 	u32				prev;
528 	int				miss_counter;
529 	bool				sick;
530 	/* wq spinlock to synchronize draining */
531 	spinlock_t			wq_lock;
532 	struct workqueue_struct	       *wq;
533 	unsigned long			flags;
534 	struct work_struct		work;
535 	struct delayed_work		recover_work;
536 };
537 
538 struct mlx5_qp_table {
539 	/* protect radix tree
540 	 */
541 	spinlock_t		lock;
542 	struct radix_tree_root	tree;
543 };
544 
545 struct mlx5_srq_table {
546 	/* protect radix tree
547 	 */
548 	spinlock_t		lock;
549 	struct radix_tree_root	tree;
550 };
551 
552 struct mlx5_mkey_table {
553 	/* protect radix tree
554 	 */
555 	rwlock_t		lock;
556 	struct radix_tree_root	tree;
557 };
558 
559 struct mlx5_vf_context {
560 	int	enabled;
561 	u64	port_guid;
562 	u64	node_guid;
563 	enum port_state_policy	policy;
564 };
565 
566 struct mlx5_core_sriov {
567 	struct mlx5_vf_context	*vfs_ctx;
568 	int			num_vfs;
569 	int			enabled_vfs;
570 };
571 
572 struct mlx5_irq_info {
573 	cpumask_var_t mask;
574 	char name[MLX5_MAX_IRQ_NAME];
575 };
576 
577 struct mlx5_fc_stats {
578 	struct rb_root counters;
579 	struct list_head addlist;
580 	/* protect addlist add/splice operations */
581 	spinlock_t addlist_lock;
582 
583 	struct workqueue_struct *wq;
584 	struct delayed_work work;
585 	unsigned long next_query;
586 	unsigned long sampling_interval; /* jiffies */
587 };
588 
589 struct mlx5_mpfs;
590 struct mlx5_eswitch;
591 struct mlx5_lag;
592 struct mlx5_pagefault;
593 
594 struct mlx5_rl_entry {
595 	u32                     rate;
596 	u16                     index;
597 	u16                     refcount;
598 };
599 
600 struct mlx5_rl_table {
601 	/* protect rate limit table */
602 	struct mutex            rl_lock;
603 	u16                     max_size;
604 	u32                     max_rate;
605 	u32                     min_rate;
606 	struct mlx5_rl_entry   *rl_entry;
607 };
608 
609 enum port_module_event_status_type {
610 	MLX5_MODULE_STATUS_PLUGGED   = 0x1,
611 	MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
612 	MLX5_MODULE_STATUS_ERROR     = 0x3,
613 	MLX5_MODULE_STATUS_NUM       = 0x3,
614 };
615 
616 enum  port_module_event_error_type {
617 	MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED,
618 	MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE,
619 	MLX5_MODULE_EVENT_ERROR_BUS_STUCK,
620 	MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT,
621 	MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST,
622 	MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER,
623 	MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE,
624 	MLX5_MODULE_EVENT_ERROR_BAD_CABLE,
625 	MLX5_MODULE_EVENT_ERROR_UNKNOWN,
626 	MLX5_MODULE_EVENT_ERROR_NUM,
627 };
628 
629 struct mlx5_port_module_event_stats {
630 	u64 status_counters[MLX5_MODULE_STATUS_NUM];
631 	u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
632 };
633 
634 struct mlx5_priv {
635 	char			name[MLX5_MAX_NAME_LEN];
636 	struct mlx5_eq_table	eq_table;
637 	struct mlx5_irq_info	*irq_info;
638 
639 	/* pages stuff */
640 	struct workqueue_struct *pg_wq;
641 	struct rb_root		page_root;
642 	int			fw_pages;
643 	atomic_t		reg_pages;
644 	struct list_head	free_list;
645 	int			vfs_pages;
646 
647 	struct mlx5_core_health health;
648 
649 	struct mlx5_srq_table	srq_table;
650 
651 	/* start: qp staff */
652 	struct mlx5_qp_table	qp_table;
653 	struct dentry	       *qp_debugfs;
654 	struct dentry	       *eq_debugfs;
655 	struct dentry	       *cq_debugfs;
656 	struct dentry	       *cmdif_debugfs;
657 	/* end: qp staff */
658 
659 	/* start: mkey staff */
660 	struct mlx5_mkey_table	mkey_table;
661 	/* end: mkey staff */
662 
663 	/* start: alloc staff */
664 	/* protect buffer alocation according to numa node */
665 	struct mutex            alloc_mutex;
666 	int                     numa_node;
667 
668 	struct mutex            pgdir_mutex;
669 	struct list_head        pgdir_list;
670 	/* end: alloc staff */
671 	struct dentry	       *dbg_root;
672 
673 	/* protect mkey key part */
674 	spinlock_t		mkey_lock;
675 	u8			mkey_key;
676 
677 	struct list_head        dev_list;
678 	struct list_head        ctx_list;
679 	spinlock_t              ctx_lock;
680 
681 	struct list_head	waiting_events_list;
682 	bool			is_accum_events;
683 
684 	struct mlx5_flow_steering *steering;
685 	struct mlx5_mpfs        *mpfs;
686 	struct mlx5_eswitch     *eswitch;
687 	struct mlx5_core_sriov	sriov;
688 	struct mlx5_lag		*lag;
689 	unsigned long		pci_dev_data;
690 	struct mlx5_fc_stats		fc_stats;
691 	struct mlx5_rl_table            rl_table;
692 
693 	struct mlx5_port_module_event_stats  pme_stats;
694 
695 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
696 	void		      (*pfault)(struct mlx5_core_dev *dev,
697 					void *context,
698 					struct mlx5_pagefault *pfault);
699 	void		       *pfault_ctx;
700 	struct srcu_struct      pfault_srcu;
701 #endif
702 	struct mlx5_bfreg_data		bfregs;
703 	struct mlx5_uars_page	       *uar;
704 };
705 
706 enum mlx5_device_state {
707 	MLX5_DEVICE_STATE_UP,
708 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
709 };
710 
711 enum mlx5_interface_state {
712 	MLX5_INTERFACE_STATE_UP = BIT(0),
713 };
714 
715 enum mlx5_pci_status {
716 	MLX5_PCI_STATUS_DISABLED,
717 	MLX5_PCI_STATUS_ENABLED,
718 };
719 
720 enum mlx5_pagefault_type_flags {
721 	MLX5_PFAULT_REQUESTOR = 1 << 0,
722 	MLX5_PFAULT_WRITE     = 1 << 1,
723 	MLX5_PFAULT_RDMA      = 1 << 2,
724 };
725 
726 /* Contains the details of a pagefault. */
727 struct mlx5_pagefault {
728 	u32			bytes_committed;
729 	u32			token;
730 	u8			event_subtype;
731 	u8			type;
732 	union {
733 		/* Initiator or send message responder pagefault details. */
734 		struct {
735 			/* Received packet size, only valid for responders. */
736 			u32	packet_size;
737 			/*
738 			 * Number of resource holding WQE, depends on type.
739 			 */
740 			u32	wq_num;
741 			/*
742 			 * WQE index. Refers to either the send queue or
743 			 * receive queue, according to event_subtype.
744 			 */
745 			u16	wqe_index;
746 		} wqe;
747 		/* RDMA responder pagefault details */
748 		struct {
749 			u32	r_key;
750 			/*
751 			 * Received packet size, minimal size page fault
752 			 * resolution required for forward progress.
753 			 */
754 			u32	packet_size;
755 			u32	rdma_op_len;
756 			u64	rdma_va;
757 		} rdma;
758 	};
759 
760 	struct mlx5_eq	       *eq;
761 	struct work_struct	work;
762 };
763 
764 struct mlx5_td {
765 	struct list_head tirs_list;
766 	u32              tdn;
767 };
768 
769 struct mlx5e_resources {
770 	u32                        pdn;
771 	struct mlx5_td             td;
772 	struct mlx5_core_mkey      mkey;
773 	struct mlx5_sq_bfreg       bfreg;
774 };
775 
776 #define MLX5_MAX_RESERVED_GIDS 8
777 
778 struct mlx5_rsvd_gids {
779 	unsigned int start;
780 	unsigned int count;
781 	struct ida ida;
782 };
783 
784 #define MAX_PIN_NUM	8
785 struct mlx5_pps {
786 	u8                         pin_caps[MAX_PIN_NUM];
787 	struct work_struct         out_work;
788 	u64                        start[MAX_PIN_NUM];
789 	u8                         enabled;
790 };
791 
792 struct mlx5_clock {
793 	rwlock_t                   lock;
794 	struct cyclecounter        cycles;
795 	struct timecounter         tc;
796 	struct hwtstamp_config     hwtstamp_config;
797 	u32                        nominal_c_mult;
798 	unsigned long              overflow_period;
799 	struct delayed_work        overflow_work;
800 	struct mlx5_core_dev      *mdev;
801 	struct ptp_clock          *ptp;
802 	struct ptp_clock_info      ptp_info;
803 	struct mlx5_pps            pps_info;
804 };
805 
806 struct mlx5_core_dev {
807 	struct pci_dev	       *pdev;
808 	/* sync pci state */
809 	struct mutex		pci_status_mutex;
810 	enum mlx5_pci_status	pci_status;
811 	u8			rev_id;
812 	char			board_id[MLX5_BOARD_ID_LEN];
813 	struct mlx5_cmd		cmd;
814 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
815 	struct {
816 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
817 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
818 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
819 		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
820 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
821 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
822 	} caps;
823 	phys_addr_t		iseg_base;
824 	struct mlx5_init_seg __iomem *iseg;
825 	enum mlx5_device_state	state;
826 	/* sync interface state */
827 	struct mutex		intf_state_mutex;
828 	unsigned long		intf_state;
829 	void			(*event) (struct mlx5_core_dev *dev,
830 					  enum mlx5_dev_event event,
831 					  unsigned long param);
832 	struct mlx5_priv	priv;
833 	struct mlx5_profile	*profile;
834 	atomic_t		num_qps;
835 	u32			issi;
836 	struct mlx5e_resources  mlx5e_res;
837 	struct {
838 		struct mlx5_rsvd_gids	reserved_gids;
839 		u32			roce_en;
840 	} roce;
841 #ifdef CONFIG_MLX5_FPGA
842 	struct mlx5_fpga_device *fpga;
843 #endif
844 #ifdef CONFIG_RFS_ACCEL
845 	struct cpu_rmap         *rmap;
846 #endif
847 	struct mlx5_clock        clock;
848 	struct mlx5_ib_clock_info  *clock_info;
849 	struct page             *clock_info_page;
850 };
851 
852 struct mlx5_db {
853 	__be32			*db;
854 	union {
855 		struct mlx5_db_pgdir		*pgdir;
856 		struct mlx5_ib_user_db_page	*user_page;
857 	}			u;
858 	dma_addr_t		dma;
859 	int			index;
860 };
861 
862 enum {
863 	MLX5_COMP_EQ_SIZE = 1024,
864 };
865 
866 enum {
867 	MLX5_PTYS_IB = 1 << 0,
868 	MLX5_PTYS_EN = 1 << 2,
869 };
870 
871 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
872 
873 enum {
874 	MLX5_CMD_ENT_STATE_PENDING_COMP,
875 };
876 
877 struct mlx5_cmd_work_ent {
878 	unsigned long		state;
879 	struct mlx5_cmd_msg    *in;
880 	struct mlx5_cmd_msg    *out;
881 	void		       *uout;
882 	int			uout_size;
883 	mlx5_cmd_cbk_t		callback;
884 	struct delayed_work	cb_timeout_work;
885 	void		       *context;
886 	int			idx;
887 	struct completion	done;
888 	struct mlx5_cmd        *cmd;
889 	struct work_struct	work;
890 	struct mlx5_cmd_layout *lay;
891 	int			ret;
892 	int			page_queue;
893 	u8			status;
894 	u8			token;
895 	u64			ts1;
896 	u64			ts2;
897 	u16			op;
898 	bool			polling;
899 };
900 
901 struct mlx5_pas {
902 	u64	pa;
903 	u8	log_sz;
904 };
905 
906 enum phy_port_state {
907 	MLX5_AAA_111
908 };
909 
910 struct mlx5_hca_vport_context {
911 	u32			field_select;
912 	bool			sm_virt_aware;
913 	bool			has_smi;
914 	bool			has_raw;
915 	enum port_state_policy	policy;
916 	enum phy_port_state	phys_state;
917 	enum ib_port_state	vport_state;
918 	u8			port_physical_state;
919 	u64			sys_image_guid;
920 	u64			port_guid;
921 	u64			node_guid;
922 	u32			cap_mask1;
923 	u32			cap_mask1_perm;
924 	u32			cap_mask2;
925 	u32			cap_mask2_perm;
926 	u16			lid;
927 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
928 	u8			lmc;
929 	u8			subnet_timeout;
930 	u16			sm_lid;
931 	u8			sm_sl;
932 	u16			qkey_violation_counter;
933 	u16			pkey_violation_counter;
934 	bool			grh_required;
935 };
936 
937 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
938 {
939 		return buf->frags->buf + offset;
940 }
941 
942 #define STRUCT_FIELD(header, field) \
943 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
944 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
945 
946 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
947 {
948 	return pci_get_drvdata(pdev);
949 }
950 
951 extern struct dentry *mlx5_debugfs_root;
952 
953 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
954 {
955 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
956 }
957 
958 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
959 {
960 	return ioread32be(&dev->iseg->fw_rev) >> 16;
961 }
962 
963 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
964 {
965 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
966 }
967 
968 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
969 {
970 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
971 }
972 
973 static inline u32 mlx5_base_mkey(const u32 key)
974 {
975 	return key & 0xffffff00u;
976 }
977 
978 static inline void mlx5_core_init_cq_frag_buf(struct mlx5_frag_buf_ctrl *fbc,
979 					      void *cqc)
980 {
981 	fbc->log_stride	= 6 + MLX5_GET(cqc, cqc, cqe_sz);
982 	fbc->log_sz	= MLX5_GET(cqc, cqc, log_cq_size);
983 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
984 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
985 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
986 }
987 
988 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
989 					  u32 ix)
990 {
991 	unsigned int frag = (ix >> fbc->log_frag_strides);
992 
993 	return fbc->frag_buf.frags[frag].buf +
994 		((fbc->frag_sz_m1 & ix) << fbc->log_stride);
995 }
996 
997 int mlx5_cmd_init(struct mlx5_core_dev *dev);
998 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
999 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
1000 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
1001 
1002 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1003 		  int out_size);
1004 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1005 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
1006 		     void *context);
1007 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1008 			  void *out, int out_size);
1009 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
1010 
1011 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1012 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1013 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1014 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1015 int mlx5_health_init(struct mlx5_core_dev *dev);
1016 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1017 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
1018 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1019 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1020 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
1021 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1022 			struct mlx5_frag_buf *buf, int node);
1023 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1024 		   int size, struct mlx5_frag_buf *buf);
1025 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1026 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1027 			     struct mlx5_frag_buf *buf, int node);
1028 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1029 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1030 						      gfp_t flags, int npages);
1031 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1032 				 struct mlx5_cmd_mailbox *head);
1033 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1034 			 struct mlx5_srq_attr *in);
1035 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
1036 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1037 			struct mlx5_srq_attr *out);
1038 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
1039 		      u16 lwm, int is_srq);
1040 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
1041 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
1042 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
1043 			     struct mlx5_core_mkey *mkey,
1044 			     u32 *in, int inlen,
1045 			     u32 *out, int outlen,
1046 			     mlx5_cmd_cbk_t callback, void *context);
1047 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1048 			  struct mlx5_core_mkey *mkey,
1049 			  u32 *in, int inlen);
1050 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1051 			   struct mlx5_core_mkey *mkey);
1052 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1053 			 u32 *out, int outlen);
1054 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
1055 			     u32 *mkey);
1056 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1057 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1058 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1059 		      u16 opmod, u8 port);
1060 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1061 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1062 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1063 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1064 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1065 				 s32 npages);
1066 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1067 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1068 void mlx5_register_debugfs(void);
1069 void mlx5_unregister_debugfs(void);
1070 
1071 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1072 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1073 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1074 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1075 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1076 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1077 		    unsigned int *irqn);
1078 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1079 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1080 
1081 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1082 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1083 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1084 			 int size_in, void *data_out, int size_out,
1085 			 u16 reg_num, int arg, int write);
1086 
1087 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1088 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1089 		       int node);
1090 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1091 
1092 const char *mlx5_command_str(int command);
1093 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1094 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1095 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1096 			 int npsvs, u32 *sig_index);
1097 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1098 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1099 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1100 			struct mlx5_odp_caps *odp_caps);
1101 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1102 			     u8 port_num, void *out, size_t sz);
1103 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1104 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
1105 				u32 wq_num, u8 type, int error);
1106 #endif
1107 
1108 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1109 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1110 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index);
1111 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate);
1112 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1113 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1114 		     bool map_wc, bool fast_path);
1115 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1116 
1117 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1118 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1119 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1120 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1121 
1122 static inline int fw_initializing(struct mlx5_core_dev *dev)
1123 {
1124 	return ioread32be(&dev->iseg->initializing) >> 31;
1125 }
1126 
1127 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1128 {
1129 	return mkey >> 8;
1130 }
1131 
1132 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1133 {
1134 	return mkey_idx << 8;
1135 }
1136 
1137 static inline u8 mlx5_mkey_variant(u32 mkey)
1138 {
1139 	return mkey & 0xff;
1140 }
1141 
1142 enum {
1143 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1144 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1145 };
1146 
1147 enum {
1148 	MR_CACHE_LAST_STD_ENTRY = 20,
1149 	MLX5_IMR_MTT_CACHE_ENTRY,
1150 	MLX5_IMR_KSM_CACHE_ENTRY,
1151 	MAX_MR_CACHE_ENTRIES
1152 };
1153 
1154 enum {
1155 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
1156 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
1157 };
1158 
1159 struct mlx5_interface {
1160 	void *			(*add)(struct mlx5_core_dev *dev);
1161 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
1162 	int			(*attach)(struct mlx5_core_dev *dev, void *context);
1163 	void			(*detach)(struct mlx5_core_dev *dev, void *context);
1164 	void			(*event)(struct mlx5_core_dev *dev, void *context,
1165 					 enum mlx5_dev_event event, unsigned long param);
1166 	void			(*pfault)(struct mlx5_core_dev *dev,
1167 					  void *context,
1168 					  struct mlx5_pagefault *pfault);
1169 	void *                  (*get_dev)(void *context);
1170 	int			protocol;
1171 	struct list_head	list;
1172 };
1173 
1174 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1175 int mlx5_register_interface(struct mlx5_interface *intf);
1176 void mlx5_unregister_interface(struct mlx5_interface *intf);
1177 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1178 
1179 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1180 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1181 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1182 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1183 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1184 				 u64 *values,
1185 				 int num_counters,
1186 				 size_t *offsets);
1187 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1188 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1189 
1190 #ifndef CONFIG_MLX5_CORE_IPOIB
1191 static inline
1192 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1193 					  struct ib_device *ibdev,
1194 					  const char *name,
1195 					  void (*setup)(struct net_device *))
1196 {
1197 	return ERR_PTR(-EOPNOTSUPP);
1198 }
1199 
1200 static inline void mlx5_rdma_netdev_free(struct net_device *netdev) {}
1201 #else
1202 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1203 					  struct ib_device *ibdev,
1204 					  const char *name,
1205 					  void (*setup)(struct net_device *));
1206 void mlx5_rdma_netdev_free(struct net_device *netdev);
1207 #endif /* CONFIG_MLX5_CORE_IPOIB */
1208 
1209 struct mlx5_profile {
1210 	u64	mask;
1211 	u8	log_max_qp;
1212 	struct {
1213 		int	size;
1214 		int	limit;
1215 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1216 };
1217 
1218 enum {
1219 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1220 };
1221 
1222 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1223 {
1224 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1225 }
1226 
1227 #define MLX5_TOTAL_VPORTS(mdev) (1 + pci_sriov_get_totalvfs((mdev)->pdev))
1228 #define MLX5_VPORT_MANAGER(mdev) \
1229 	(MLX5_CAP_GEN(mdev, vport_group_manager) && \
1230 	 (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && \
1231 	 mlx5_core_is_pf(mdev))
1232 
1233 static inline int mlx5_get_gid_table_len(u16 param)
1234 {
1235 	if (param > 4) {
1236 		pr_warn("gid table length is zero\n");
1237 		return 0;
1238 	}
1239 
1240 	return 8 * (1 << param);
1241 }
1242 
1243 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1244 {
1245 	return !!(dev->priv.rl_table.max_size);
1246 }
1247 
1248 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1249 {
1250 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1251 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1252 }
1253 
1254 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1255 {
1256 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1257 }
1258 
1259 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1260 {
1261 	return mlx5_core_is_mp_slave(dev) ||
1262 	       mlx5_core_is_mp_master(dev);
1263 }
1264 
1265 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1266 {
1267 	if (!mlx5_core_mp_enabled(dev))
1268 		return 1;
1269 
1270 	return MLX5_CAP_GEN(dev, native_port_num);
1271 }
1272 
1273 enum {
1274 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1275 };
1276 
1277 static inline const struct cpumask *
1278 mlx5_get_vector_affinity(struct mlx5_core_dev *dev, int vector)
1279 {
1280 	const struct cpumask *mask;
1281 	struct irq_desc *desc;
1282 	unsigned int irq;
1283 	int eqn;
1284 	int err;
1285 
1286 	err = mlx5_vector2eqn(dev, MLX5_EQ_VEC_COMP_BASE + vector, &eqn, &irq);
1287 	if (err)
1288 		return NULL;
1289 
1290 	desc = irq_to_desc(irq);
1291 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
1292 	mask = irq_data_get_effective_affinity_mask(&desc->irq_data);
1293 #else
1294 	mask = desc->irq_common_data.affinity;
1295 #endif
1296 	return mask;
1297 }
1298 
1299 #endif /* MLX5_DRIVER_H */
1300