xref: /linux-6.15/include/linux/mlx5/driver.h (revision 52cf89f7) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63 
64 enum {
65 	MLX5_BOARD_ID_LEN = 64,
66 };
67 
68 enum {
69 	MLX5_CMD_WQ_MAX_NAME	= 32,
70 };
71 
72 enum {
73 	CMD_OWNER_SW		= 0x0,
74 	CMD_OWNER_HW		= 0x1,
75 	CMD_STATUS_SUCCESS	= 0,
76 };
77 
78 enum mlx5_sqp_t {
79 	MLX5_SQP_SMI		= 0,
80 	MLX5_SQP_GSI		= 1,
81 	MLX5_SQP_IEEE_1588	= 2,
82 	MLX5_SQP_SNIFFER	= 3,
83 	MLX5_SQP_SYNC_UMR	= 4,
84 };
85 
86 enum {
87 	MLX5_MAX_PORTS	= 4,
88 };
89 
90 enum {
91 	MLX5_ATOMIC_MODE_OFFSET = 16,
92 	MLX5_ATOMIC_MODE_IB_COMP = 1,
93 	MLX5_ATOMIC_MODE_CX = 2,
94 	MLX5_ATOMIC_MODE_8B = 3,
95 	MLX5_ATOMIC_MODE_16B = 4,
96 	MLX5_ATOMIC_MODE_32B = 5,
97 	MLX5_ATOMIC_MODE_64B = 6,
98 	MLX5_ATOMIC_MODE_128B = 7,
99 	MLX5_ATOMIC_MODE_256B = 8,
100 };
101 
102 enum {
103 	MLX5_REG_SBPR            = 0xb001,
104 	MLX5_REG_SBCM            = 0xb002,
105 	MLX5_REG_QPTS            = 0x4002,
106 	MLX5_REG_QETCR		 = 0x4005,
107 	MLX5_REG_QTCT		 = 0x400a,
108 	MLX5_REG_QPDPM           = 0x4013,
109 	MLX5_REG_QCAM            = 0x4019,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_CORE_DUMP	 = 0x402e,
116 	MLX5_REG_PCAP		 = 0x5001,
117 	MLX5_REG_PMTU		 = 0x5003,
118 	MLX5_REG_PTYS		 = 0x5004,
119 	MLX5_REG_PAOS		 = 0x5006,
120 	MLX5_REG_PFCC            = 0x5007,
121 	MLX5_REG_PPCNT		 = 0x5008,
122 	MLX5_REG_PPTB            = 0x500b,
123 	MLX5_REG_PBMC            = 0x500c,
124 	MLX5_REG_PMAOS		 = 0x5012,
125 	MLX5_REG_PUDE		 = 0x5009,
126 	MLX5_REG_PMPE		 = 0x5010,
127 	MLX5_REG_PELC		 = 0x500e,
128 	MLX5_REG_PVLC		 = 0x500f,
129 	MLX5_REG_PCMR		 = 0x5041,
130 	MLX5_REG_PDDR		 = 0x5031,
131 	MLX5_REG_PMLP		 = 0x5002,
132 	MLX5_REG_PPLM		 = 0x5023,
133 	MLX5_REG_PCAM		 = 0x507f,
134 	MLX5_REG_NODE_DESC	 = 0x6001,
135 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
136 	MLX5_REG_MCIA		 = 0x9014,
137 	MLX5_REG_MFRL		 = 0x9028,
138 	MLX5_REG_MLCR		 = 0x902b,
139 	MLX5_REG_MRTC		 = 0x902d,
140 	MLX5_REG_MTRC_CAP	 = 0x9040,
141 	MLX5_REG_MTRC_CONF	 = 0x9041,
142 	MLX5_REG_MTRC_STDB	 = 0x9042,
143 	MLX5_REG_MTRC_CTRL	 = 0x9043,
144 	MLX5_REG_MPEIN		 = 0x9050,
145 	MLX5_REG_MPCNT		 = 0x9051,
146 	MLX5_REG_MTPPS		 = 0x9053,
147 	MLX5_REG_MTPPSE		 = 0x9054,
148 	MLX5_REG_MTUTC		 = 0x9055,
149 	MLX5_REG_MPEGC		 = 0x9056,
150 	MLX5_REG_MCQS		 = 0x9060,
151 	MLX5_REG_MCQI		 = 0x9061,
152 	MLX5_REG_MCC		 = 0x9062,
153 	MLX5_REG_MCDA		 = 0x9063,
154 	MLX5_REG_MCAM		 = 0x907f,
155 	MLX5_REG_MIRC		 = 0x9162,
156 	MLX5_REG_SBCAM		 = 0xB01F,
157 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
158 	MLX5_REG_DTOR            = 0xC00E,
159 };
160 
161 enum mlx5_qpts_trust_state {
162 	MLX5_QPTS_TRUST_PCP  = 1,
163 	MLX5_QPTS_TRUST_DSCP = 2,
164 };
165 
166 enum mlx5_dcbx_oper_mode {
167 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
168 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
169 };
170 
171 enum {
172 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
173 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
174 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
175 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
176 };
177 
178 enum mlx5_page_fault_resume_flags {
179 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
180 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
181 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
182 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
183 };
184 
185 enum dbg_rsc_type {
186 	MLX5_DBG_RSC_QP,
187 	MLX5_DBG_RSC_EQ,
188 	MLX5_DBG_RSC_CQ,
189 };
190 
191 enum port_state_policy {
192 	MLX5_POLICY_DOWN	= 0,
193 	MLX5_POLICY_UP		= 1,
194 	MLX5_POLICY_FOLLOW	= 2,
195 	MLX5_POLICY_INVALID	= 0xffffffff
196 };
197 
198 enum mlx5_coredev_type {
199 	MLX5_COREDEV_PF,
200 	MLX5_COREDEV_VF,
201 	MLX5_COREDEV_SF,
202 };
203 
204 struct mlx5_field_desc {
205 	int			i;
206 };
207 
208 struct mlx5_rsc_debug {
209 	struct mlx5_core_dev   *dev;
210 	void		       *object;
211 	enum dbg_rsc_type	type;
212 	struct dentry	       *root;
213 	struct mlx5_field_desc	fields[];
214 };
215 
216 enum mlx5_dev_event {
217 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
218 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
219 };
220 
221 enum mlx5_port_status {
222 	MLX5_PORT_UP        = 1,
223 	MLX5_PORT_DOWN      = 2,
224 };
225 
226 enum mlx5_cmdif_state {
227 	MLX5_CMDIF_STATE_UNINITIALIZED,
228 	MLX5_CMDIF_STATE_UP,
229 	MLX5_CMDIF_STATE_DOWN,
230 };
231 
232 struct mlx5_cmd_first {
233 	__be32		data[4];
234 };
235 
236 struct mlx5_cmd_msg {
237 	struct list_head		list;
238 	struct cmd_msg_cache	       *parent;
239 	u32				len;
240 	struct mlx5_cmd_first		first;
241 	struct mlx5_cmd_mailbox	       *next;
242 };
243 
244 struct mlx5_cmd_debug {
245 	struct dentry	       *dbg_root;
246 	void		       *in_msg;
247 	void		       *out_msg;
248 	u8			status;
249 	u16			inlen;
250 	u16			outlen;
251 };
252 
253 struct cmd_msg_cache {
254 	/* protect block chain allocations
255 	 */
256 	spinlock_t		lock;
257 	struct list_head	head;
258 	unsigned int		max_inbox_size;
259 	unsigned int		num_ent;
260 };
261 
262 enum {
263 	MLX5_NUM_COMMAND_CACHES = 5,
264 };
265 
266 struct mlx5_cmd_stats {
267 	u64		sum;
268 	u64		n;
269 	/* number of times command failed */
270 	u64		failed;
271 	/* number of times command failed on bad status returned by FW */
272 	u64		failed_mbox_status;
273 	/* last command failed returned errno */
274 	u32		last_failed_errno;
275 	/* last bad status returned by FW */
276 	u8		last_failed_mbox_status;
277 	/* last command failed syndrome returned by FW */
278 	u32		last_failed_syndrome;
279 	struct dentry  *root;
280 	/* protect command average calculations */
281 	spinlock_t	lock;
282 };
283 
284 struct mlx5_cmd {
285 	struct mlx5_nb    nb;
286 
287 	enum mlx5_cmdif_state	state;
288 	void	       *cmd_alloc_buf;
289 	dma_addr_t	alloc_dma;
290 	int		alloc_size;
291 	void	       *cmd_buf;
292 	dma_addr_t	dma;
293 	u16		cmdif_rev;
294 	u8		log_sz;
295 	u8		log_stride;
296 	int		max_reg_cmds;
297 	int		events;
298 	u32 __iomem    *vector;
299 
300 	/* protect command queue allocations
301 	 */
302 	spinlock_t	alloc_lock;
303 
304 	/* protect token allocations
305 	 */
306 	spinlock_t	token_lock;
307 	u8		token;
308 	unsigned long	bitmask;
309 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
310 	struct workqueue_struct *wq;
311 	struct semaphore sem;
312 	struct semaphore pages_sem;
313 	struct semaphore throttle_sem;
314 	int	mode;
315 	u16     allowed_opcode;
316 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
317 	struct dma_pool *pool;
318 	struct mlx5_cmd_debug dbg;
319 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
320 	int checksum_disabled;
321 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
322 };
323 
324 struct mlx5_cmd_mailbox {
325 	void	       *buf;
326 	dma_addr_t	dma;
327 	struct mlx5_cmd_mailbox *next;
328 };
329 
330 struct mlx5_buf_list {
331 	void		       *buf;
332 	dma_addr_t		map;
333 };
334 
335 struct mlx5_frag_buf {
336 	struct mlx5_buf_list	*frags;
337 	int			npages;
338 	int			size;
339 	u8			page_shift;
340 };
341 
342 struct mlx5_frag_buf_ctrl {
343 	struct mlx5_buf_list   *frags;
344 	u32			sz_m1;
345 	u16			frag_sz_m1;
346 	u16			strides_offset;
347 	u8			log_sz;
348 	u8			log_stride;
349 	u8			log_frag_strides;
350 };
351 
352 struct mlx5_core_psv {
353 	u32	psv_idx;
354 	struct psv_layout {
355 		u32	pd;
356 		u16	syndrome;
357 		u16	reserved;
358 		u16	bg;
359 		u16	app_tag;
360 		u32	ref_tag;
361 	} psv;
362 };
363 
364 struct mlx5_core_sig_ctx {
365 	struct mlx5_core_psv	psv_memory;
366 	struct mlx5_core_psv	psv_wire;
367 	struct ib_sig_err       err_item;
368 	bool			sig_status_checked;
369 	bool			sig_err_exists;
370 	u32			sigerr_count;
371 };
372 
373 #define MLX5_24BIT_MASK		((1 << 24) - 1)
374 
375 enum mlx5_res_type {
376 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
377 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
378 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
379 	MLX5_RES_SRQ	= 3,
380 	MLX5_RES_XSRQ	= 4,
381 	MLX5_RES_XRQ	= 5,
382 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
383 };
384 
385 struct mlx5_core_rsc_common {
386 	enum mlx5_res_type	res;
387 	refcount_t		refcount;
388 	struct completion	free;
389 };
390 
391 struct mlx5_uars_page {
392 	void __iomem	       *map;
393 	bool			wc;
394 	u32			index;
395 	struct list_head	list;
396 	unsigned int		bfregs;
397 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
398 	unsigned long	       *fp_bitmap;
399 	unsigned int		reg_avail;
400 	unsigned int		fp_avail;
401 	struct kref		ref_count;
402 	struct mlx5_core_dev   *mdev;
403 };
404 
405 struct mlx5_bfreg_head {
406 	/* protect blue flame registers allocations */
407 	struct mutex		lock;
408 	struct list_head	list;
409 };
410 
411 struct mlx5_bfreg_data {
412 	struct mlx5_bfreg_head	reg_head;
413 	struct mlx5_bfreg_head	wc_head;
414 };
415 
416 struct mlx5_sq_bfreg {
417 	void __iomem	       *map;
418 	struct mlx5_uars_page  *up;
419 	bool			wc;
420 	u32			index;
421 	unsigned int		offset;
422 };
423 
424 struct mlx5_core_health {
425 	struct health_buffer __iomem   *health;
426 	__be32 __iomem		       *health_counter;
427 	struct timer_list		timer;
428 	u32				prev;
429 	int				miss_counter;
430 	u8				synd;
431 	u32				fatal_error;
432 	u32				crdump_size;
433 	/* wq spinlock to synchronize draining */
434 	spinlock_t			wq_lock;
435 	struct workqueue_struct	       *wq;
436 	unsigned long			flags;
437 	struct work_struct		fatal_report_work;
438 	struct work_struct		report_work;
439 	struct devlink_health_reporter *fw_reporter;
440 	struct devlink_health_reporter *fw_fatal_reporter;
441 	struct delayed_work		update_fw_log_ts_work;
442 };
443 
444 struct mlx5_qp_table {
445 	struct notifier_block   nb;
446 
447 	/* protect radix tree
448 	 */
449 	spinlock_t		lock;
450 	struct radix_tree_root	tree;
451 };
452 
453 enum {
454 	MLX5_PF_NOTIFY_DISABLE_VF,
455 	MLX5_PF_NOTIFY_ENABLE_VF,
456 };
457 
458 struct mlx5_vf_context {
459 	int	enabled;
460 	u64	port_guid;
461 	u64	node_guid;
462 	/* Valid bits are used to validate administrative guid only.
463 	 * Enabled after ndo_set_vf_guid
464 	 */
465 	u8	port_guid_valid:1;
466 	u8	node_guid_valid:1;
467 	enum port_state_policy	policy;
468 	struct blocking_notifier_head notifier;
469 };
470 
471 struct mlx5_core_sriov {
472 	struct mlx5_vf_context	*vfs_ctx;
473 	int			num_vfs;
474 	u16			max_vfs;
475 };
476 
477 struct mlx5_fc_pool {
478 	struct mlx5_core_dev *dev;
479 	struct mutex pool_lock; /* protects pool lists */
480 	struct list_head fully_used;
481 	struct list_head partially_used;
482 	struct list_head unused;
483 	int available_fcs;
484 	int used_fcs;
485 	int threshold;
486 };
487 
488 struct mlx5_fc_stats {
489 	spinlock_t counters_idr_lock; /* protects counters_idr */
490 	struct idr counters_idr;
491 	struct list_head counters;
492 	struct llist_head addlist;
493 	struct llist_head dellist;
494 
495 	struct workqueue_struct *wq;
496 	struct delayed_work work;
497 	unsigned long next_query;
498 	unsigned long sampling_interval; /* jiffies */
499 	u32 *bulk_query_out;
500 	int bulk_query_len;
501 	size_t num_counters;
502 	bool bulk_query_alloc_failed;
503 	unsigned long next_bulk_query_alloc;
504 	struct mlx5_fc_pool fc_pool;
505 };
506 
507 struct mlx5_events;
508 struct mlx5_mpfs;
509 struct mlx5_eswitch;
510 struct mlx5_lag;
511 struct mlx5_devcom;
512 struct mlx5_fw_reset;
513 struct mlx5_eq_table;
514 struct mlx5_irq_table;
515 struct mlx5_vhca_state_notifier;
516 struct mlx5_sf_dev_table;
517 struct mlx5_sf_hw_table;
518 struct mlx5_sf_table;
519 struct mlx5_crypto_dek_priv;
520 
521 struct mlx5_rate_limit {
522 	u32			rate;
523 	u32			max_burst_sz;
524 	u16			typical_pkt_sz;
525 };
526 
527 struct mlx5_rl_entry {
528 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
529 	u64 refcount;
530 	u16 index;
531 	u16 uid;
532 	u8 dedicated : 1;
533 };
534 
535 struct mlx5_rl_table {
536 	/* protect rate limit table */
537 	struct mutex            rl_lock;
538 	u16                     max_size;
539 	u32                     max_rate;
540 	u32                     min_rate;
541 	struct mlx5_rl_entry   *rl_entry;
542 	u64 refcount;
543 };
544 
545 struct mlx5_core_roce {
546 	struct mlx5_flow_table *ft;
547 	struct mlx5_flow_group *fg;
548 	struct mlx5_flow_handle *allow_rule;
549 };
550 
551 enum {
552 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
553 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
554 	/* Set during device detach to block any further devices
555 	 * creation/deletion on drivers rescan. Unset during device attach.
556 	 */
557 	MLX5_PRIV_FLAGS_DETACH = 1 << 2,
558 };
559 
560 struct mlx5_adev {
561 	struct auxiliary_device adev;
562 	struct mlx5_core_dev *mdev;
563 	int idx;
564 };
565 
566 struct mlx5_debugfs_entries {
567 	struct dentry *dbg_root;
568 	struct dentry *qp_debugfs;
569 	struct dentry *eq_debugfs;
570 	struct dentry *cq_debugfs;
571 	struct dentry *cmdif_debugfs;
572 	struct dentry *pages_debugfs;
573 	struct dentry *lag_debugfs;
574 };
575 
576 struct mlx5_ft_pool;
577 struct mlx5_priv {
578 	/* IRQ table valid only for real pci devices PF or VF */
579 	struct mlx5_irq_table   *irq_table;
580 	struct mlx5_eq_table	*eq_table;
581 
582 	/* pages stuff */
583 	struct mlx5_nb          pg_nb;
584 	struct workqueue_struct *pg_wq;
585 	struct xarray           page_root_xa;
586 	u32			fw_pages;
587 	atomic_t		reg_pages;
588 	struct list_head	free_list;
589 	u32			vfs_pages;
590 	u32			host_pf_pages;
591 	u32			fw_pages_alloc_failed;
592 	u32			give_pages_dropped;
593 	u32			reclaim_pages_discard;
594 
595 	struct mlx5_core_health health;
596 	struct list_head	traps;
597 
598 	struct mlx5_debugfs_entries dbg;
599 
600 	/* start: alloc staff */
601 	/* protect buffer allocation according to numa node */
602 	struct mutex            alloc_mutex;
603 	int                     numa_node;
604 
605 	struct mutex            pgdir_mutex;
606 	struct list_head        pgdir_list;
607 	/* end: alloc staff */
608 
609 	struct mlx5_adev       **adev;
610 	int			adev_idx;
611 	int			sw_vhca_id;
612 	struct mlx5_events      *events;
613 
614 	struct mlx5_flow_steering *steering;
615 	struct mlx5_mpfs        *mpfs;
616 	struct mlx5_eswitch     *eswitch;
617 	struct mlx5_core_sriov	sriov;
618 	struct mlx5_lag		*lag;
619 	u32			flags;
620 	struct mlx5_devcom	*devcom;
621 	struct mlx5_fw_reset	*fw_reset;
622 	struct mlx5_core_roce	roce;
623 	struct mlx5_fc_stats		fc_stats;
624 	struct mlx5_rl_table            rl_table;
625 	struct mlx5_ft_pool		*ft_pool;
626 
627 	struct mlx5_bfreg_data		bfregs;
628 	struct mlx5_uars_page	       *uar;
629 #ifdef CONFIG_MLX5_SF
630 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
631 	struct mlx5_sf_dev_table *sf_dev_table;
632 	struct mlx5_core_dev *parent_mdev;
633 #endif
634 #ifdef CONFIG_MLX5_SF_MANAGER
635 	struct mlx5_sf_hw_table *sf_hw_table;
636 	struct mlx5_sf_table *sf_table;
637 #endif
638 };
639 
640 enum mlx5_device_state {
641 	MLX5_DEVICE_STATE_UP = 1,
642 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
643 };
644 
645 enum mlx5_interface_state {
646 	MLX5_INTERFACE_STATE_UP = BIT(0),
647 	MLX5_BREAK_FW_WAIT = BIT(1),
648 };
649 
650 enum mlx5_pci_status {
651 	MLX5_PCI_STATUS_DISABLED,
652 	MLX5_PCI_STATUS_ENABLED,
653 };
654 
655 enum mlx5_pagefault_type_flags {
656 	MLX5_PFAULT_REQUESTOR = 1 << 0,
657 	MLX5_PFAULT_WRITE     = 1 << 1,
658 	MLX5_PFAULT_RDMA      = 1 << 2,
659 };
660 
661 struct mlx5_td {
662 	/* protects tirs list changes while tirs refresh */
663 	struct mutex     list_lock;
664 	struct list_head tirs_list;
665 	u32              tdn;
666 };
667 
668 struct mlx5e_resources {
669 	struct mlx5e_hw_objs {
670 		u32                        pdn;
671 		struct mlx5_td             td;
672 		u32			   mkey;
673 		struct mlx5_sq_bfreg       bfreg;
674 	} hw_objs;
675 	struct devlink_port dl_port;
676 	struct net_device *uplink_netdev;
677 	struct mlx5_crypto_dek_priv *dek_priv;
678 };
679 
680 enum mlx5_sw_icm_type {
681 	MLX5_SW_ICM_TYPE_STEERING,
682 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
683 	MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
684 };
685 
686 #define MLX5_MAX_RESERVED_GIDS 8
687 
688 struct mlx5_rsvd_gids {
689 	unsigned int start;
690 	unsigned int count;
691 	struct ida ida;
692 };
693 
694 #define MAX_PIN_NUM	8
695 struct mlx5_pps {
696 	u8                         pin_caps[MAX_PIN_NUM];
697 	struct work_struct         out_work;
698 	u64                        start[MAX_PIN_NUM];
699 	u8                         enabled;
700 	u64                        min_npps_period;
701 	u64                        min_out_pulse_duration_ns;
702 };
703 
704 struct mlx5_timer {
705 	struct cyclecounter        cycles;
706 	struct timecounter         tc;
707 	u32                        nominal_c_mult;
708 	unsigned long              overflow_period;
709 	struct delayed_work        overflow_work;
710 };
711 
712 struct mlx5_clock {
713 	struct mlx5_nb             pps_nb;
714 	seqlock_t                  lock;
715 	struct hwtstamp_config     hwtstamp_config;
716 	struct ptp_clock          *ptp;
717 	struct ptp_clock_info      ptp_info;
718 	struct mlx5_pps            pps_info;
719 	struct mlx5_timer          timer;
720 };
721 
722 struct mlx5_dm;
723 struct mlx5_fw_tracer;
724 struct mlx5_vxlan;
725 struct mlx5_geneve;
726 struct mlx5_hv_vhca;
727 
728 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
729 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
730 
731 enum {
732 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
733 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
734 };
735 
736 enum {
737 	MKEY_CACHE_LAST_STD_ENTRY = 20,
738 	MLX5_IMR_MTT_CACHE_ENTRY,
739 	MLX5_IMR_KSM_CACHE_ENTRY,
740 	MAX_MKEY_CACHE_ENTRIES
741 };
742 
743 struct mlx5_profile {
744 	u64	mask;
745 	u8	log_max_qp;
746 	struct {
747 		int	size;
748 		int	limit;
749 	} mr_cache[MAX_MKEY_CACHE_ENTRIES];
750 };
751 
752 struct mlx5_hca_cap {
753 	u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
754 	u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
755 };
756 
757 struct mlx5_core_dev {
758 	struct device *device;
759 	enum mlx5_coredev_type coredev_type;
760 	struct pci_dev	       *pdev;
761 	/* sync pci state */
762 	struct mutex		pci_status_mutex;
763 	enum mlx5_pci_status	pci_status;
764 	u8			rev_id;
765 	char			board_id[MLX5_BOARD_ID_LEN];
766 	struct mlx5_cmd		cmd;
767 	struct {
768 		struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
769 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
770 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
771 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
772 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
773 		u8  embedded_cpu;
774 	} caps;
775 	struct mlx5_timeouts	*timeouts;
776 	u64			sys_image_guid;
777 	phys_addr_t		iseg_base;
778 	struct mlx5_init_seg __iomem *iseg;
779 	phys_addr_t             bar_addr;
780 	enum mlx5_device_state	state;
781 	/* sync interface state */
782 	struct mutex		intf_state_mutex;
783 	struct lock_class_key	lock_key;
784 	unsigned long		intf_state;
785 	struct mlx5_priv	priv;
786 	struct mlx5_profile	profile;
787 	u32			issi;
788 	struct mlx5e_resources  mlx5e_res;
789 	struct mlx5_dm          *dm;
790 	struct mlx5_vxlan       *vxlan;
791 	struct mlx5_geneve      *geneve;
792 	struct {
793 		struct mlx5_rsvd_gids	reserved_gids;
794 		u32			roce_en;
795 	} roce;
796 #ifdef CONFIG_MLX5_FPGA
797 	struct mlx5_fpga_device *fpga;
798 #endif
799 	struct mlx5_clock        clock;
800 	struct mlx5_ib_clock_info  *clock_info;
801 	struct mlx5_fw_tracer   *tracer;
802 	struct mlx5_rsc_dump    *rsc_dump;
803 	u32                      vsc_addr;
804 	struct mlx5_hv_vhca	*hv_vhca;
805 };
806 
807 struct mlx5_db {
808 	__be32			*db;
809 	union {
810 		struct mlx5_db_pgdir		*pgdir;
811 		struct mlx5_ib_user_db_page	*user_page;
812 	}			u;
813 	dma_addr_t		dma;
814 	int			index;
815 };
816 
817 enum {
818 	MLX5_COMP_EQ_SIZE = 1024,
819 };
820 
821 enum {
822 	MLX5_PTYS_IB = 1 << 0,
823 	MLX5_PTYS_EN = 1 << 2,
824 };
825 
826 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
827 
828 enum {
829 	MLX5_CMD_ENT_STATE_PENDING_COMP,
830 };
831 
832 struct mlx5_cmd_work_ent {
833 	unsigned long		state;
834 	struct mlx5_cmd_msg    *in;
835 	struct mlx5_cmd_msg    *out;
836 	void		       *uout;
837 	int			uout_size;
838 	mlx5_cmd_cbk_t		callback;
839 	struct delayed_work	cb_timeout_work;
840 	void		       *context;
841 	int			idx;
842 	struct completion	handling;
843 	struct completion	done;
844 	struct mlx5_cmd        *cmd;
845 	struct work_struct	work;
846 	struct mlx5_cmd_layout *lay;
847 	int			ret;
848 	int			page_queue;
849 	u8			status;
850 	u8			token;
851 	u64			ts1;
852 	u64			ts2;
853 	u16			op;
854 	bool			polling;
855 	/* Track the max comp handlers */
856 	refcount_t              refcnt;
857 };
858 
859 enum phy_port_state {
860 	MLX5_AAA_111
861 };
862 
863 struct mlx5_hca_vport_context {
864 	u32			field_select;
865 	bool			sm_virt_aware;
866 	bool			has_smi;
867 	bool			has_raw;
868 	enum port_state_policy	policy;
869 	enum phy_port_state	phys_state;
870 	enum ib_port_state	vport_state;
871 	u8			port_physical_state;
872 	u64			sys_image_guid;
873 	u64			port_guid;
874 	u64			node_guid;
875 	u32			cap_mask1;
876 	u32			cap_mask1_perm;
877 	u16			cap_mask2;
878 	u16			cap_mask2_perm;
879 	u16			lid;
880 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
881 	u8			lmc;
882 	u8			subnet_timeout;
883 	u16			sm_lid;
884 	u8			sm_sl;
885 	u16			qkey_violation_counter;
886 	u16			pkey_violation_counter;
887 	bool			grh_required;
888 };
889 
890 #define STRUCT_FIELD(header, field) \
891 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
892 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
893 
894 extern struct dentry *mlx5_debugfs_root;
895 
896 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
897 {
898 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
899 }
900 
901 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
902 {
903 	return ioread32be(&dev->iseg->fw_rev) >> 16;
904 }
905 
906 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
907 {
908 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
909 }
910 
911 static inline u32 mlx5_base_mkey(const u32 key)
912 {
913 	return key & 0xffffff00u;
914 }
915 
916 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
917 {
918 	return ((u32)1 << log_sz) << log_stride;
919 }
920 
921 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
922 					u8 log_stride, u8 log_sz,
923 					u16 strides_offset,
924 					struct mlx5_frag_buf_ctrl *fbc)
925 {
926 	fbc->frags      = frags;
927 	fbc->log_stride = log_stride;
928 	fbc->log_sz     = log_sz;
929 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
930 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
931 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
932 	fbc->strides_offset = strides_offset;
933 }
934 
935 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
936 				 u8 log_stride, u8 log_sz,
937 				 struct mlx5_frag_buf_ctrl *fbc)
938 {
939 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
940 }
941 
942 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
943 					  u32 ix)
944 {
945 	unsigned int frag;
946 
947 	ix  += fbc->strides_offset;
948 	frag = ix >> fbc->log_frag_strides;
949 
950 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
951 }
952 
953 static inline u32
954 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
955 {
956 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
957 
958 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
959 }
960 
961 enum {
962 	CMD_ALLOWED_OPCODE_ALL,
963 };
964 
965 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
966 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
967 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
968 
969 struct mlx5_async_ctx {
970 	struct mlx5_core_dev *dev;
971 	atomic_t num_inflight;
972 	struct completion inflight_done;
973 };
974 
975 struct mlx5_async_work;
976 
977 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
978 
979 struct mlx5_async_work {
980 	struct mlx5_async_ctx *ctx;
981 	mlx5_async_cbk_t user_callback;
982 	u16 opcode; /* cmd opcode */
983 	u16 op_mod; /* cmd op_mod */
984 	void *out; /* pointer to the cmd output buffer */
985 };
986 
987 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
988 			     struct mlx5_async_ctx *ctx);
989 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
990 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
991 		     void *out, int out_size, mlx5_async_cbk_t callback,
992 		     struct mlx5_async_work *work);
993 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
994 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
995 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
996 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
997 		  int out_size);
998 
999 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
1000 	({                                                                     \
1001 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
1002 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
1003 	})
1004 
1005 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
1006 	({                                                                     \
1007 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
1008 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
1009 	})
1010 
1011 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1012 			  void *out, int out_size);
1013 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1014 
1015 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1016 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1017 int mlx5_health_init(struct mlx5_core_dev *dev);
1018 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1019 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1020 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1021 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1022 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1023 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1024 			     struct mlx5_frag_buf *buf, int node);
1025 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1026 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1027 						      gfp_t flags, int npages);
1028 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1029 				 struct mlx5_cmd_mailbox *head);
1030 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1031 			  int inlen);
1032 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1033 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1034 			 int outlen);
1035 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1036 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1037 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1038 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1039 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1040 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1041 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1042 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1043 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1044 				 s32 npages, bool ec_function);
1045 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1046 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1047 void mlx5_register_debugfs(void);
1048 void mlx5_unregister_debugfs(void);
1049 
1050 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1051 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1052 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1053 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1054 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1055 
1056 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1057 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1058 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1059 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1060 		    void *data_out, int size_out, u16 reg_id, int arg,
1061 		    int write, bool verbose);
1062 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1063 			 int size_in, void *data_out, int size_out,
1064 			 u16 reg_num, int arg, int write);
1065 
1066 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1067 		       int node);
1068 
1069 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1070 {
1071 	return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1072 }
1073 
1074 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1075 
1076 const char *mlx5_command_str(int command);
1077 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1078 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1079 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1080 			 int npsvs, u32 *sig_index);
1081 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1082 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1083 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1084 			struct mlx5_odp_caps *odp_caps);
1085 
1086 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1087 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1088 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1089 		     struct mlx5_rate_limit *rl);
1090 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1091 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1092 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1093 			 bool dedicated_entry, u16 *index);
1094 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1095 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1096 		       struct mlx5_rate_limit *rl_1);
1097 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1098 		     bool map_wc, bool fast_path);
1099 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1100 
1101 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1102 struct cpumask *
1103 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1104 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1105 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1106 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1107 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1108 
1109 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1110 {
1111 	return mkey >> 8;
1112 }
1113 
1114 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1115 {
1116 	return mkey_idx << 8;
1117 }
1118 
1119 static inline u8 mlx5_mkey_variant(u32 mkey)
1120 {
1121 	return mkey & 0xff;
1122 }
1123 
1124 /* Async-atomic event notifier used by mlx5 core to forward FW
1125  * evetns received from event queue to mlx5 consumers.
1126  * Optimise event queue dipatching.
1127  */
1128 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1129 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1130 
1131 /* Async-atomic event notifier used for forwarding
1132  * evetns from the event queue into the to mlx5 events dispatcher,
1133  * eswitch, clock and others.
1134  */
1135 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1136 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1137 
1138 /* Blocking event notifier used to forward SW events, used for slow path */
1139 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1140 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1141 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1142 				      void *data);
1143 
1144 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1145 
1146 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1147 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1148 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1149 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1150 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1151 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1152 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1153 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1154 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1155 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1156 			   struct net_device *slave);
1157 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1158 				 u64 *values,
1159 				 int num_counters,
1160 				 size_t *offsets);
1161 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1162 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1163 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1164 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1165 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1166 			 u64 length, u32 log_alignment, u16 uid,
1167 			 phys_addr_t *addr, u32 *obj_id);
1168 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1169 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1170 
1171 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1172 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1173 
1174 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1175 					  int vf_id,
1176 					  struct notifier_block *nb);
1177 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1178 					     int vf_id,
1179 					     struct notifier_block *nb);
1180 #ifdef CONFIG_MLX5_CORE_IPOIB
1181 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1182 					  struct ib_device *ibdev,
1183 					  const char *name,
1184 					  void (*setup)(struct net_device *));
1185 #endif /* CONFIG_MLX5_CORE_IPOIB */
1186 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1187 			    struct ib_device *device,
1188 			    struct rdma_netdev_alloc_params *params);
1189 
1190 enum {
1191 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1192 };
1193 
1194 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1195 {
1196 	return dev->coredev_type == MLX5_COREDEV_PF;
1197 }
1198 
1199 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1200 {
1201 	return dev->coredev_type == MLX5_COREDEV_VF;
1202 }
1203 
1204 static inline bool mlx5_core_is_management_pf(const struct mlx5_core_dev *dev)
1205 {
1206 	return MLX5_CAP_GEN(dev, num_ports) == 1 && !MLX5_CAP_GEN(dev, native_port_num);
1207 }
1208 
1209 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1210 {
1211 	return dev->caps.embedded_cpu;
1212 }
1213 
1214 static inline bool
1215 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1216 {
1217 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1218 }
1219 
1220 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1221 {
1222 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1223 }
1224 
1225 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1226 {
1227 	return dev->priv.sriov.max_vfs;
1228 }
1229 
1230 static inline int mlx5_get_gid_table_len(u16 param)
1231 {
1232 	if (param > 4) {
1233 		pr_warn("gid table length is zero\n");
1234 		return 0;
1235 	}
1236 
1237 	return 8 * (1 << param);
1238 }
1239 
1240 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1241 {
1242 	return !!(dev->priv.rl_table.max_size);
1243 }
1244 
1245 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1246 {
1247 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1248 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1249 }
1250 
1251 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1252 {
1253 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1254 }
1255 
1256 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1257 {
1258 	return mlx5_core_is_mp_slave(dev) ||
1259 	       mlx5_core_is_mp_master(dev);
1260 }
1261 
1262 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1263 {
1264 	if (!mlx5_core_mp_enabled(dev))
1265 		return 1;
1266 
1267 	return MLX5_CAP_GEN(dev, native_port_num);
1268 }
1269 
1270 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1271 {
1272 	int idx = MLX5_CAP_GEN(dev, native_port_num);
1273 
1274 	if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1275 		return idx - 1;
1276 	else
1277 		return PCI_FUNC(dev->pdev->devfn);
1278 }
1279 
1280 enum {
1281 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1282 };
1283 
1284 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1285 
1286 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1287 {
1288 	if (MLX5_CAP_GEN(dev, roce_rw_supported))
1289 		return MLX5_CAP_GEN(dev, roce);
1290 
1291 	/* If RoCE cap is read-only in FW, get RoCE state from devlink
1292 	 * in order to support RoCE enable/disable feature
1293 	 */
1294 	return mlx5_is_roce_on(dev);
1295 }
1296 
1297 enum {
1298 	MLX5_OCTWORD = 16,
1299 };
1300 
1301 #endif /* MLX5_DRIVER_H */
1302