xref: /linux-6.15/include/linux/mlx5/driver.h (revision 4c08c586) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 enum {
63 	MLX5_BOARD_ID_LEN = 64,
64 };
65 
66 enum {
67 	/* one minute for the sake of bringup. Generally, commands must always
68 	 * complete and we may need to increase this timeout value
69 	 */
70 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
71 	MLX5_CMD_WQ_MAX_NAME	= 32,
72 };
73 
74 enum {
75 	CMD_OWNER_SW		= 0x0,
76 	CMD_OWNER_HW		= 0x1,
77 	CMD_STATUS_SUCCESS	= 0,
78 };
79 
80 enum mlx5_sqp_t {
81 	MLX5_SQP_SMI		= 0,
82 	MLX5_SQP_GSI		= 1,
83 	MLX5_SQP_IEEE_1588	= 2,
84 	MLX5_SQP_SNIFFER	= 3,
85 	MLX5_SQP_SYNC_UMR	= 4,
86 };
87 
88 enum {
89 	MLX5_MAX_PORTS	= 2,
90 };
91 
92 enum {
93 	MLX5_ATOMIC_MODE_OFFSET = 16,
94 	MLX5_ATOMIC_MODE_IB_COMP = 1,
95 	MLX5_ATOMIC_MODE_CX = 2,
96 	MLX5_ATOMIC_MODE_8B = 3,
97 	MLX5_ATOMIC_MODE_16B = 4,
98 	MLX5_ATOMIC_MODE_32B = 5,
99 	MLX5_ATOMIC_MODE_64B = 6,
100 	MLX5_ATOMIC_MODE_128B = 7,
101 	MLX5_ATOMIC_MODE_256B = 8,
102 };
103 
104 enum {
105 	MLX5_REG_QPTS            = 0x4002,
106 	MLX5_REG_QETCR		 = 0x4005,
107 	MLX5_REG_QTCT		 = 0x400a,
108 	MLX5_REG_QPDPM           = 0x4013,
109 	MLX5_REG_QCAM            = 0x4019,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_CORE_DUMP	 = 0x402e,
116 	MLX5_REG_PCAP		 = 0x5001,
117 	MLX5_REG_PMTU		 = 0x5003,
118 	MLX5_REG_PTYS		 = 0x5004,
119 	MLX5_REG_PAOS		 = 0x5006,
120 	MLX5_REG_PFCC            = 0x5007,
121 	MLX5_REG_PPCNT		 = 0x5008,
122 	MLX5_REG_PPTB            = 0x500b,
123 	MLX5_REG_PBMC            = 0x500c,
124 	MLX5_REG_PMAOS		 = 0x5012,
125 	MLX5_REG_PUDE		 = 0x5009,
126 	MLX5_REG_PMPE		 = 0x5010,
127 	MLX5_REG_PELC		 = 0x500e,
128 	MLX5_REG_PVLC		 = 0x500f,
129 	MLX5_REG_PCMR		 = 0x5041,
130 	MLX5_REG_PMLP		 = 0x5002,
131 	MLX5_REG_PPLM		 = 0x5023,
132 	MLX5_REG_PCAM		 = 0x507f,
133 	MLX5_REG_NODE_DESC	 = 0x6001,
134 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
135 	MLX5_REG_MCIA		 = 0x9014,
136 	MLX5_REG_MFRL		 = 0x9028,
137 	MLX5_REG_MLCR		 = 0x902b,
138 	MLX5_REG_MTRC_CAP	 = 0x9040,
139 	MLX5_REG_MTRC_CONF	 = 0x9041,
140 	MLX5_REG_MTRC_STDB	 = 0x9042,
141 	MLX5_REG_MTRC_CTRL	 = 0x9043,
142 	MLX5_REG_MPEIN		 = 0x9050,
143 	MLX5_REG_MPCNT		 = 0x9051,
144 	MLX5_REG_MTPPS		 = 0x9053,
145 	MLX5_REG_MTPPSE		 = 0x9054,
146 	MLX5_REG_MPEGC		 = 0x9056,
147 	MLX5_REG_MCQS		 = 0x9060,
148 	MLX5_REG_MCQI		 = 0x9061,
149 	MLX5_REG_MCC		 = 0x9062,
150 	MLX5_REG_MCDA		 = 0x9063,
151 	MLX5_REG_MCAM		 = 0x907f,
152 	MLX5_REG_MIRC		 = 0x9162,
153 	MLX5_REG_SBCAM		 = 0xB01F,
154 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
155 };
156 
157 enum mlx5_qpts_trust_state {
158 	MLX5_QPTS_TRUST_PCP  = 1,
159 	MLX5_QPTS_TRUST_DSCP = 2,
160 };
161 
162 enum mlx5_dcbx_oper_mode {
163 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
164 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
165 };
166 
167 enum {
168 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
169 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
170 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
171 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
172 };
173 
174 enum mlx5_page_fault_resume_flags {
175 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
176 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
177 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
178 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
179 };
180 
181 enum dbg_rsc_type {
182 	MLX5_DBG_RSC_QP,
183 	MLX5_DBG_RSC_EQ,
184 	MLX5_DBG_RSC_CQ,
185 };
186 
187 enum port_state_policy {
188 	MLX5_POLICY_DOWN	= 0,
189 	MLX5_POLICY_UP		= 1,
190 	MLX5_POLICY_FOLLOW	= 2,
191 	MLX5_POLICY_INVALID	= 0xffffffff
192 };
193 
194 enum mlx5_coredev_type {
195 	MLX5_COREDEV_PF,
196 	MLX5_COREDEV_VF,
197 	MLX5_COREDEV_SF,
198 };
199 
200 struct mlx5_field_desc {
201 	int			i;
202 };
203 
204 struct mlx5_rsc_debug {
205 	struct mlx5_core_dev   *dev;
206 	void		       *object;
207 	enum dbg_rsc_type	type;
208 	struct dentry	       *root;
209 	struct mlx5_field_desc	fields[];
210 };
211 
212 enum mlx5_dev_event {
213 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
214 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
215 };
216 
217 enum mlx5_port_status {
218 	MLX5_PORT_UP        = 1,
219 	MLX5_PORT_DOWN      = 2,
220 };
221 
222 enum mlx5_cmdif_state {
223 	MLX5_CMDIF_STATE_UNINITIALIZED,
224 	MLX5_CMDIF_STATE_UP,
225 	MLX5_CMDIF_STATE_DOWN,
226 };
227 
228 struct mlx5_cmd_first {
229 	__be32		data[4];
230 };
231 
232 struct mlx5_cmd_msg {
233 	struct list_head		list;
234 	struct cmd_msg_cache	       *parent;
235 	u32				len;
236 	struct mlx5_cmd_first		first;
237 	struct mlx5_cmd_mailbox	       *next;
238 };
239 
240 struct mlx5_cmd_debug {
241 	struct dentry	       *dbg_root;
242 	void		       *in_msg;
243 	void		       *out_msg;
244 	u8			status;
245 	u16			inlen;
246 	u16			outlen;
247 };
248 
249 struct cmd_msg_cache {
250 	/* protect block chain allocations
251 	 */
252 	spinlock_t		lock;
253 	struct list_head	head;
254 	unsigned int		max_inbox_size;
255 	unsigned int		num_ent;
256 };
257 
258 enum {
259 	MLX5_NUM_COMMAND_CACHES = 5,
260 };
261 
262 struct mlx5_cmd_stats {
263 	u64		sum;
264 	u64		n;
265 	struct dentry  *root;
266 	/* protect command average calculations */
267 	spinlock_t	lock;
268 };
269 
270 struct mlx5_cmd {
271 	struct mlx5_nb    nb;
272 
273 	enum mlx5_cmdif_state	state;
274 	void	       *cmd_alloc_buf;
275 	dma_addr_t	alloc_dma;
276 	int		alloc_size;
277 	void	       *cmd_buf;
278 	dma_addr_t	dma;
279 	u16		cmdif_rev;
280 	u8		log_sz;
281 	u8		log_stride;
282 	int		max_reg_cmds;
283 	int		events;
284 	u32 __iomem    *vector;
285 
286 	/* protect command queue allocations
287 	 */
288 	spinlock_t	alloc_lock;
289 
290 	/* protect token allocations
291 	 */
292 	spinlock_t	token_lock;
293 	u8		token;
294 	unsigned long	bitmask;
295 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
296 	struct workqueue_struct *wq;
297 	struct semaphore sem;
298 	struct semaphore pages_sem;
299 	int	mode;
300 	u16     allowed_opcode;
301 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
302 	struct dma_pool *pool;
303 	struct mlx5_cmd_debug dbg;
304 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
305 	int checksum_disabled;
306 	struct mlx5_cmd_stats *stats;
307 };
308 
309 struct mlx5_port_caps {
310 	int	gid_table_len;
311 	int	pkey_table_len;
312 	u8	ext_port_cap;
313 	bool	has_smi;
314 };
315 
316 struct mlx5_cmd_mailbox {
317 	void	       *buf;
318 	dma_addr_t	dma;
319 	struct mlx5_cmd_mailbox *next;
320 };
321 
322 struct mlx5_buf_list {
323 	void		       *buf;
324 	dma_addr_t		map;
325 };
326 
327 struct mlx5_frag_buf {
328 	struct mlx5_buf_list	*frags;
329 	int			npages;
330 	int			size;
331 	u8			page_shift;
332 };
333 
334 struct mlx5_frag_buf_ctrl {
335 	struct mlx5_buf_list   *frags;
336 	u32			sz_m1;
337 	u16			frag_sz_m1;
338 	u16			strides_offset;
339 	u8			log_sz;
340 	u8			log_stride;
341 	u8			log_frag_strides;
342 };
343 
344 struct mlx5_core_psv {
345 	u32	psv_idx;
346 	struct psv_layout {
347 		u32	pd;
348 		u16	syndrome;
349 		u16	reserved;
350 		u16	bg;
351 		u16	app_tag;
352 		u32	ref_tag;
353 	} psv;
354 };
355 
356 struct mlx5_core_sig_ctx {
357 	struct mlx5_core_psv	psv_memory;
358 	struct mlx5_core_psv	psv_wire;
359 	struct ib_sig_err       err_item;
360 	bool			sig_status_checked;
361 	bool			sig_err_exists;
362 	u32			sigerr_count;
363 };
364 
365 enum {
366 	MLX5_MKEY_MR = 1,
367 	MLX5_MKEY_MW,
368 	MLX5_MKEY_INDIRECT_DEVX,
369 };
370 
371 struct mlx5_core_mkey {
372 	u64			iova;
373 	u64			size;
374 	u32			key;
375 	u32			pd;
376 	u32			type;
377 };
378 
379 #define MLX5_24BIT_MASK		((1 << 24) - 1)
380 
381 enum mlx5_res_type {
382 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
383 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
384 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
385 	MLX5_RES_SRQ	= 3,
386 	MLX5_RES_XSRQ	= 4,
387 	MLX5_RES_XRQ	= 5,
388 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
389 };
390 
391 struct mlx5_core_rsc_common {
392 	enum mlx5_res_type	res;
393 	refcount_t		refcount;
394 	struct completion	free;
395 };
396 
397 struct mlx5_uars_page {
398 	void __iomem	       *map;
399 	bool			wc;
400 	u32			index;
401 	struct list_head	list;
402 	unsigned int		bfregs;
403 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
404 	unsigned long	       *fp_bitmap;
405 	unsigned int		reg_avail;
406 	unsigned int		fp_avail;
407 	struct kref		ref_count;
408 	struct mlx5_core_dev   *mdev;
409 };
410 
411 struct mlx5_bfreg_head {
412 	/* protect blue flame registers allocations */
413 	struct mutex		lock;
414 	struct list_head	list;
415 };
416 
417 struct mlx5_bfreg_data {
418 	struct mlx5_bfreg_head	reg_head;
419 	struct mlx5_bfreg_head	wc_head;
420 };
421 
422 struct mlx5_sq_bfreg {
423 	void __iomem	       *map;
424 	struct mlx5_uars_page  *up;
425 	bool			wc;
426 	u32			index;
427 	unsigned int		offset;
428 };
429 
430 struct mlx5_core_health {
431 	struct health_buffer __iomem   *health;
432 	__be32 __iomem		       *health_counter;
433 	struct timer_list		timer;
434 	u32				prev;
435 	int				miss_counter;
436 	u8				synd;
437 	u32				fatal_error;
438 	u32				crdump_size;
439 	/* wq spinlock to synchronize draining */
440 	spinlock_t			wq_lock;
441 	struct workqueue_struct	       *wq;
442 	unsigned long			flags;
443 	struct work_struct		fatal_report_work;
444 	struct work_struct		report_work;
445 	struct delayed_work		recover_work;
446 	struct devlink_health_reporter *fw_reporter;
447 	struct devlink_health_reporter *fw_fatal_reporter;
448 };
449 
450 struct mlx5_qp_table {
451 	struct notifier_block   nb;
452 
453 	/* protect radix tree
454 	 */
455 	spinlock_t		lock;
456 	struct radix_tree_root	tree;
457 };
458 
459 struct mlx5_vf_context {
460 	int	enabled;
461 	u64	port_guid;
462 	u64	node_guid;
463 	/* Valid bits are used to validate administrative guid only.
464 	 * Enabled after ndo_set_vf_guid
465 	 */
466 	u8	port_guid_valid:1;
467 	u8	node_guid_valid:1;
468 	enum port_state_policy	policy;
469 };
470 
471 struct mlx5_core_sriov {
472 	struct mlx5_vf_context	*vfs_ctx;
473 	int			num_vfs;
474 	u16			max_vfs;
475 };
476 
477 struct mlx5_fc_pool {
478 	struct mlx5_core_dev *dev;
479 	struct mutex pool_lock; /* protects pool lists */
480 	struct list_head fully_used;
481 	struct list_head partially_used;
482 	struct list_head unused;
483 	int available_fcs;
484 	int used_fcs;
485 	int threshold;
486 };
487 
488 struct mlx5_fc_stats {
489 	spinlock_t counters_idr_lock; /* protects counters_idr */
490 	struct idr counters_idr;
491 	struct list_head counters;
492 	struct llist_head addlist;
493 	struct llist_head dellist;
494 
495 	struct workqueue_struct *wq;
496 	struct delayed_work work;
497 	unsigned long next_query;
498 	unsigned long sampling_interval; /* jiffies */
499 	u32 *bulk_query_out;
500 	struct mlx5_fc_pool fc_pool;
501 };
502 
503 struct mlx5_events;
504 struct mlx5_mpfs;
505 struct mlx5_eswitch;
506 struct mlx5_lag;
507 struct mlx5_devcom;
508 struct mlx5_fw_reset;
509 struct mlx5_eq_table;
510 struct mlx5_irq_table;
511 struct mlx5_vhca_state_notifier;
512 struct mlx5_sf_dev_table;
513 struct mlx5_sf_hw_table;
514 struct mlx5_sf_table;
515 
516 struct mlx5_rate_limit {
517 	u32			rate;
518 	u32			max_burst_sz;
519 	u16			typical_pkt_sz;
520 };
521 
522 struct mlx5_rl_entry {
523 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
524 	u16 index;
525 	u64 refcount;
526 	u16 uid;
527 	u8 dedicated : 1;
528 };
529 
530 struct mlx5_rl_table {
531 	/* protect rate limit table */
532 	struct mutex            rl_lock;
533 	u16                     max_size;
534 	u32                     max_rate;
535 	u32                     min_rate;
536 	struct mlx5_rl_entry   *rl_entry;
537 };
538 
539 struct mlx5_core_roce {
540 	struct mlx5_flow_table *ft;
541 	struct mlx5_flow_group *fg;
542 	struct mlx5_flow_handle *allow_rule;
543 };
544 
545 enum {
546 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
547 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
548 };
549 
550 struct mlx5_adev {
551 	struct auxiliary_device adev;
552 	struct mlx5_core_dev *mdev;
553 	int idx;
554 };
555 
556 struct mlx5_priv {
557 	/* IRQ table valid only for real pci devices PF or VF */
558 	struct mlx5_irq_table   *irq_table;
559 	struct mlx5_eq_table	*eq_table;
560 
561 	/* pages stuff */
562 	struct mlx5_nb          pg_nb;
563 	struct workqueue_struct *pg_wq;
564 	struct xarray           page_root_xa;
565 	int			fw_pages;
566 	atomic_t		reg_pages;
567 	struct list_head	free_list;
568 	int			vfs_pages;
569 	int			host_pf_pages;
570 
571 	struct mlx5_core_health health;
572 	struct list_head	traps;
573 
574 	/* start: qp staff */
575 	struct dentry	       *qp_debugfs;
576 	struct dentry	       *eq_debugfs;
577 	struct dentry	       *cq_debugfs;
578 	struct dentry	       *cmdif_debugfs;
579 	/* end: qp staff */
580 
581 	/* start: alloc staff */
582 	/* protect buffer alocation according to numa node */
583 	struct mutex            alloc_mutex;
584 	int                     numa_node;
585 
586 	struct mutex            pgdir_mutex;
587 	struct list_head        pgdir_list;
588 	/* end: alloc staff */
589 	struct dentry	       *dbg_root;
590 
591 	struct list_head        ctx_list;
592 	spinlock_t              ctx_lock;
593 	struct mlx5_adev       **adev;
594 	int			adev_idx;
595 	struct mlx5_events      *events;
596 
597 	struct mlx5_flow_steering *steering;
598 	struct mlx5_mpfs        *mpfs;
599 	struct mlx5_eswitch     *eswitch;
600 	struct mlx5_core_sriov	sriov;
601 	struct mlx5_lag		*lag;
602 	u32			flags;
603 	struct mlx5_devcom	*devcom;
604 	struct mlx5_fw_reset	*fw_reset;
605 	struct mlx5_core_roce	roce;
606 	struct mlx5_fc_stats		fc_stats;
607 	struct mlx5_rl_table            rl_table;
608 
609 	struct mlx5_bfreg_data		bfregs;
610 	struct mlx5_uars_page	       *uar;
611 #ifdef CONFIG_MLX5_SF
612 	struct mlx5_vhca_state_notifier *vhca_state_notifier;
613 	struct mlx5_sf_dev_table *sf_dev_table;
614 	struct mlx5_core_dev *parent_mdev;
615 #endif
616 #ifdef CONFIG_MLX5_SF_MANAGER
617 	struct mlx5_sf_hw_table *sf_hw_table;
618 	struct mlx5_sf_table *sf_table;
619 #endif
620 };
621 
622 enum mlx5_device_state {
623 	MLX5_DEVICE_STATE_UNINITIALIZED,
624 	MLX5_DEVICE_STATE_UP,
625 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
626 };
627 
628 enum mlx5_interface_state {
629 	MLX5_INTERFACE_STATE_UP = BIT(0),
630 };
631 
632 enum mlx5_pci_status {
633 	MLX5_PCI_STATUS_DISABLED,
634 	MLX5_PCI_STATUS_ENABLED,
635 };
636 
637 enum mlx5_pagefault_type_flags {
638 	MLX5_PFAULT_REQUESTOR = 1 << 0,
639 	MLX5_PFAULT_WRITE     = 1 << 1,
640 	MLX5_PFAULT_RDMA      = 1 << 2,
641 };
642 
643 struct mlx5_td {
644 	/* protects tirs list changes while tirs refresh */
645 	struct mutex     list_lock;
646 	struct list_head tirs_list;
647 	u32              tdn;
648 };
649 
650 struct mlx5e_resources {
651 	u32                        pdn;
652 	struct mlx5_td             td;
653 	struct mlx5_core_mkey      mkey;
654 	struct mlx5_sq_bfreg       bfreg;
655 };
656 
657 enum mlx5_sw_icm_type {
658 	MLX5_SW_ICM_TYPE_STEERING,
659 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
660 };
661 
662 #define MLX5_MAX_RESERVED_GIDS 8
663 
664 struct mlx5_rsvd_gids {
665 	unsigned int start;
666 	unsigned int count;
667 	struct ida ida;
668 };
669 
670 #define MAX_PIN_NUM	8
671 struct mlx5_pps {
672 	u8                         pin_caps[MAX_PIN_NUM];
673 	struct work_struct         out_work;
674 	u64                        start[MAX_PIN_NUM];
675 	u8                         enabled;
676 };
677 
678 struct mlx5_clock {
679 	struct mlx5_nb             pps_nb;
680 	seqlock_t                  lock;
681 	struct cyclecounter        cycles;
682 	struct timecounter         tc;
683 	struct hwtstamp_config     hwtstamp_config;
684 	u32                        nominal_c_mult;
685 	unsigned long              overflow_period;
686 	struct delayed_work        overflow_work;
687 	struct ptp_clock          *ptp;
688 	struct ptp_clock_info      ptp_info;
689 	struct mlx5_pps            pps_info;
690 };
691 
692 struct mlx5_dm;
693 struct mlx5_fw_tracer;
694 struct mlx5_vxlan;
695 struct mlx5_geneve;
696 struct mlx5_hv_vhca;
697 
698 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
699 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
700 
701 struct mlx5_core_dev {
702 	struct device *device;
703 	enum mlx5_coredev_type coredev_type;
704 	struct pci_dev	       *pdev;
705 	/* sync pci state */
706 	struct mutex		pci_status_mutex;
707 	enum mlx5_pci_status	pci_status;
708 	u8			rev_id;
709 	char			board_id[MLX5_BOARD_ID_LEN];
710 	struct mlx5_cmd		cmd;
711 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
712 	struct {
713 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
714 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
715 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
716 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
717 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
718 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
719 		u8  embedded_cpu;
720 	} caps;
721 	u64			sys_image_guid;
722 	phys_addr_t		iseg_base;
723 	struct mlx5_init_seg __iomem *iseg;
724 	phys_addr_t             bar_addr;
725 	enum mlx5_device_state	state;
726 	/* sync interface state */
727 	struct mutex		intf_state_mutex;
728 	unsigned long		intf_state;
729 	struct mlx5_priv	priv;
730 	struct mlx5_profile	*profile;
731 	u32			issi;
732 	struct mlx5e_resources  mlx5e_res;
733 	struct mlx5_dm          *dm;
734 	struct mlx5_vxlan       *vxlan;
735 	struct mlx5_geneve      *geneve;
736 	struct {
737 		struct mlx5_rsvd_gids	reserved_gids;
738 		u32			roce_en;
739 	} roce;
740 #ifdef CONFIG_MLX5_FPGA
741 	struct mlx5_fpga_device *fpga;
742 #endif
743 #ifdef CONFIG_MLX5_ACCEL
744 	const struct mlx5_accel_ipsec_ops *ipsec_ops;
745 #endif
746 	struct mlx5_clock        clock;
747 	struct mlx5_ib_clock_info  *clock_info;
748 	struct mlx5_fw_tracer   *tracer;
749 	struct mlx5_rsc_dump    *rsc_dump;
750 	u32                      vsc_addr;
751 	struct mlx5_hv_vhca	*hv_vhca;
752 };
753 
754 struct mlx5_db {
755 	__be32			*db;
756 	union {
757 		struct mlx5_db_pgdir		*pgdir;
758 		struct mlx5_ib_user_db_page	*user_page;
759 	}			u;
760 	dma_addr_t		dma;
761 	int			index;
762 };
763 
764 enum {
765 	MLX5_COMP_EQ_SIZE = 1024,
766 };
767 
768 enum {
769 	MLX5_PTYS_IB = 1 << 0,
770 	MLX5_PTYS_EN = 1 << 2,
771 };
772 
773 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
774 
775 enum {
776 	MLX5_CMD_ENT_STATE_PENDING_COMP,
777 };
778 
779 struct mlx5_cmd_work_ent {
780 	unsigned long		state;
781 	struct mlx5_cmd_msg    *in;
782 	struct mlx5_cmd_msg    *out;
783 	void		       *uout;
784 	int			uout_size;
785 	mlx5_cmd_cbk_t		callback;
786 	struct delayed_work	cb_timeout_work;
787 	void		       *context;
788 	int			idx;
789 	struct completion	handling;
790 	struct completion	done;
791 	struct mlx5_cmd        *cmd;
792 	struct work_struct	work;
793 	struct mlx5_cmd_layout *lay;
794 	int			ret;
795 	int			page_queue;
796 	u8			status;
797 	u8			token;
798 	u64			ts1;
799 	u64			ts2;
800 	u16			op;
801 	bool			polling;
802 	/* Track the max comp handlers */
803 	refcount_t              refcnt;
804 };
805 
806 struct mlx5_pas {
807 	u64	pa;
808 	u8	log_sz;
809 };
810 
811 enum phy_port_state {
812 	MLX5_AAA_111
813 };
814 
815 struct mlx5_hca_vport_context {
816 	u32			field_select;
817 	bool			sm_virt_aware;
818 	bool			has_smi;
819 	bool			has_raw;
820 	enum port_state_policy	policy;
821 	enum phy_port_state	phys_state;
822 	enum ib_port_state	vport_state;
823 	u8			port_physical_state;
824 	u64			sys_image_guid;
825 	u64			port_guid;
826 	u64			node_guid;
827 	u32			cap_mask1;
828 	u32			cap_mask1_perm;
829 	u16			cap_mask2;
830 	u16			cap_mask2_perm;
831 	u16			lid;
832 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
833 	u8			lmc;
834 	u8			subnet_timeout;
835 	u16			sm_lid;
836 	u8			sm_sl;
837 	u16			qkey_violation_counter;
838 	u16			pkey_violation_counter;
839 	bool			grh_required;
840 };
841 
842 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
843 {
844 		return buf->frags->buf + offset;
845 }
846 
847 #define STRUCT_FIELD(header, field) \
848 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
849 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
850 
851 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
852 {
853 	return pci_get_drvdata(pdev);
854 }
855 
856 extern struct dentry *mlx5_debugfs_root;
857 
858 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
859 {
860 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
861 }
862 
863 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
864 {
865 	return ioread32be(&dev->iseg->fw_rev) >> 16;
866 }
867 
868 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
869 {
870 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
871 }
872 
873 static inline u32 mlx5_base_mkey(const u32 key)
874 {
875 	return key & 0xffffff00u;
876 }
877 
878 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
879 					u8 log_stride, u8 log_sz,
880 					u16 strides_offset,
881 					struct mlx5_frag_buf_ctrl *fbc)
882 {
883 	fbc->frags      = frags;
884 	fbc->log_stride = log_stride;
885 	fbc->log_sz     = log_sz;
886 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
887 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
888 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
889 	fbc->strides_offset = strides_offset;
890 }
891 
892 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
893 				 u8 log_stride, u8 log_sz,
894 				 struct mlx5_frag_buf_ctrl *fbc)
895 {
896 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
897 }
898 
899 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
900 					  u32 ix)
901 {
902 	unsigned int frag;
903 
904 	ix  += fbc->strides_offset;
905 	frag = ix >> fbc->log_frag_strides;
906 
907 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
908 }
909 
910 static inline u32
911 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
912 {
913 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
914 
915 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
916 }
917 
918 enum {
919 	CMD_ALLOWED_OPCODE_ALL,
920 };
921 
922 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
923 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
924 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
925 
926 struct mlx5_async_ctx {
927 	struct mlx5_core_dev *dev;
928 	atomic_t num_inflight;
929 	struct wait_queue_head wait;
930 };
931 
932 struct mlx5_async_work;
933 
934 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
935 
936 struct mlx5_async_work {
937 	struct mlx5_async_ctx *ctx;
938 	mlx5_async_cbk_t user_callback;
939 };
940 
941 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
942 			     struct mlx5_async_ctx *ctx);
943 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
944 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
945 		     void *out, int out_size, mlx5_async_cbk_t callback,
946 		     struct mlx5_async_work *work);
947 
948 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
949 		  int out_size);
950 
951 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
952 	({                                                                     \
953 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
954 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
955 	})
956 
957 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
958 	({                                                                     \
959 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
960 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
961 	})
962 
963 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
964 			  void *out, int out_size);
965 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
966 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
967 
968 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
969 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
970 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
971 void mlx5_health_flush(struct mlx5_core_dev *dev);
972 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
973 int mlx5_health_init(struct mlx5_core_dev *dev);
974 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
975 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
976 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
977 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
978 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
979 		   int size, struct mlx5_frag_buf *buf);
980 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
981 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
982 			     struct mlx5_frag_buf *buf, int node);
983 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
984 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
985 						      gfp_t flags, int npages);
986 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
987 				 struct mlx5_cmd_mailbox *head);
988 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
989 			  struct mlx5_core_mkey *mkey,
990 			  u32 *in, int inlen);
991 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
992 			   struct mlx5_core_mkey *mkey);
993 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
994 			 u32 *out, int outlen);
995 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
996 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
997 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
998 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
999 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1000 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1001 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1002 				 s32 npages, bool ec_function);
1003 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1004 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1005 void mlx5_register_debugfs(void);
1006 void mlx5_unregister_debugfs(void);
1007 
1008 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1009 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1010 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1011 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
1012 		    unsigned int *irqn);
1013 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1014 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1015 
1016 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1017 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1018 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1019 			 int size_in, void *data_out, int size_out,
1020 			 u16 reg_num, int arg, int write);
1021 
1022 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1023 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1024 		       int node);
1025 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1026 
1027 const char *mlx5_command_str(int command);
1028 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1029 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1030 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1031 			 int npsvs, u32 *sig_index);
1032 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1033 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1034 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1035 			struct mlx5_odp_caps *odp_caps);
1036 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1037 			     u8 port_num, void *out, size_t sz);
1038 
1039 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1040 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1041 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1042 		     struct mlx5_rate_limit *rl);
1043 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1044 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1045 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1046 			 bool dedicated_entry, u16 *index);
1047 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1048 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1049 		       struct mlx5_rate_limit *rl_1);
1050 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1051 		     bool map_wc, bool fast_path);
1052 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1053 
1054 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1055 struct cpumask *
1056 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1057 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1058 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1059 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1060 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1061 
1062 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1063 {
1064 	return mkey >> 8;
1065 }
1066 
1067 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1068 {
1069 	return mkey_idx << 8;
1070 }
1071 
1072 static inline u8 mlx5_mkey_variant(u32 mkey)
1073 {
1074 	return mkey & 0xff;
1075 }
1076 
1077 enum {
1078 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1079 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1080 };
1081 
1082 enum {
1083 	MR_CACHE_LAST_STD_ENTRY = 20,
1084 	MLX5_IMR_MTT_CACHE_ENTRY,
1085 	MLX5_IMR_KSM_CACHE_ENTRY,
1086 	MAX_MR_CACHE_ENTRIES
1087 };
1088 
1089 /* Async-atomic event notifier used by mlx5 core to forward FW
1090  * evetns recived from event queue to mlx5 consumers.
1091  * Optimise event queue dipatching.
1092  */
1093 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1094 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1095 
1096 /* Async-atomic event notifier used for forwarding
1097  * evetns from the event queue into the to mlx5 events dispatcher,
1098  * eswitch, clock and others.
1099  */
1100 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1101 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1102 
1103 /* Blocking event notifier used to forward SW events, used for slow path */
1104 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1105 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1106 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1107 				      void *data);
1108 
1109 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1110 
1111 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1112 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1113 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1114 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1115 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1116 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1117 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1118 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1119 			   struct net_device *slave);
1120 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1121 				 u64 *values,
1122 				 int num_counters,
1123 				 size_t *offsets);
1124 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1125 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1126 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1127 			 u64 length, u32 log_alignment, u16 uid,
1128 			 phys_addr_t *addr, u32 *obj_id);
1129 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1130 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1131 
1132 #ifdef CONFIG_MLX5_CORE_IPOIB
1133 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1134 					  struct ib_device *ibdev,
1135 					  const char *name,
1136 					  void (*setup)(struct net_device *));
1137 #endif /* CONFIG_MLX5_CORE_IPOIB */
1138 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1139 			    struct ib_device *device,
1140 			    struct rdma_netdev_alloc_params *params);
1141 
1142 struct mlx5_profile {
1143 	u64	mask;
1144 	u8	log_max_qp;
1145 	struct {
1146 		int	size;
1147 		int	limit;
1148 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1149 };
1150 
1151 enum {
1152 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1153 };
1154 
1155 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1156 {
1157 	return dev->coredev_type == MLX5_COREDEV_PF;
1158 }
1159 
1160 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1161 {
1162 	return dev->coredev_type == MLX5_COREDEV_VF;
1163 }
1164 
1165 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1166 {
1167 	return dev->caps.embedded_cpu;
1168 }
1169 
1170 static inline bool
1171 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1172 {
1173 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1174 }
1175 
1176 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1177 {
1178 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1179 }
1180 
1181 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1182 {
1183 	return dev->priv.sriov.max_vfs;
1184 }
1185 
1186 static inline int mlx5_get_gid_table_len(u16 param)
1187 {
1188 	if (param > 4) {
1189 		pr_warn("gid table length is zero\n");
1190 		return 0;
1191 	}
1192 
1193 	return 8 * (1 << param);
1194 }
1195 
1196 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1197 {
1198 	return !!(dev->priv.rl_table.max_size);
1199 }
1200 
1201 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1202 {
1203 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1204 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1205 }
1206 
1207 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1208 {
1209 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1210 }
1211 
1212 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1213 {
1214 	return mlx5_core_is_mp_slave(dev) ||
1215 	       mlx5_core_is_mp_master(dev);
1216 }
1217 
1218 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1219 {
1220 	if (!mlx5_core_mp_enabled(dev))
1221 		return 1;
1222 
1223 	return MLX5_CAP_GEN(dev, native_port_num);
1224 }
1225 
1226 enum {
1227 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1228 };
1229 
1230 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1231 {
1232 	struct devlink *devlink = priv_to_devlink(dev);
1233 	union devlink_param_value val;
1234 
1235 	devlink_param_driverinit_value_get(devlink,
1236 					   DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1237 					   &val);
1238 	return val.vbool;
1239 }
1240 
1241 #endif /* MLX5_DRIVER_H */
1242