1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/spinlock_types.h> 40 #include <linux/semaphore.h> 41 #include <linux/slab.h> 42 #include <linux/vmalloc.h> 43 #include <linux/radix-tree.h> 44 #include <linux/workqueue.h> 45 #include <linux/mempool.h> 46 #include <linux/interrupt.h> 47 48 #include <linux/mlx5/device.h> 49 #include <linux/mlx5/doorbell.h> 50 #include <linux/mlx5/srq.h> 51 52 enum { 53 MLX5_BOARD_ID_LEN = 64, 54 MLX5_MAX_NAME_LEN = 16, 55 }; 56 57 enum { 58 /* one minute for the sake of bringup. Generally, commands must always 59 * complete and we may need to increase this timeout value 60 */ 61 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 62 MLX5_CMD_WQ_MAX_NAME = 32, 63 }; 64 65 enum { 66 CMD_OWNER_SW = 0x0, 67 CMD_OWNER_HW = 0x1, 68 CMD_STATUS_SUCCESS = 0, 69 }; 70 71 enum mlx5_sqp_t { 72 MLX5_SQP_SMI = 0, 73 MLX5_SQP_GSI = 1, 74 MLX5_SQP_IEEE_1588 = 2, 75 MLX5_SQP_SNIFFER = 3, 76 MLX5_SQP_SYNC_UMR = 4, 77 }; 78 79 enum { 80 MLX5_MAX_PORTS = 2, 81 }; 82 83 enum { 84 MLX5_EQ_VEC_PAGES = 0, 85 MLX5_EQ_VEC_CMD = 1, 86 MLX5_EQ_VEC_ASYNC = 2, 87 MLX5_EQ_VEC_PFAULT = 3, 88 MLX5_EQ_VEC_COMP_BASE, 89 }; 90 91 enum { 92 MLX5_MAX_IRQ_NAME = 32 93 }; 94 95 enum { 96 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 97 MLX5_ATOMIC_MODE_CX = 2 << 16, 98 MLX5_ATOMIC_MODE_8B = 3 << 16, 99 MLX5_ATOMIC_MODE_16B = 4 << 16, 100 MLX5_ATOMIC_MODE_32B = 5 << 16, 101 MLX5_ATOMIC_MODE_64B = 6 << 16, 102 MLX5_ATOMIC_MODE_128B = 7 << 16, 103 MLX5_ATOMIC_MODE_256B = 8 << 16, 104 }; 105 106 enum { 107 MLX5_REG_QETCR = 0x4005, 108 MLX5_REG_QTCT = 0x400a, 109 MLX5_REG_DCBX_PARAM = 0x4020, 110 MLX5_REG_DCBX_APP = 0x4021, 111 MLX5_REG_PCAP = 0x5001, 112 MLX5_REG_PMTU = 0x5003, 113 MLX5_REG_PTYS = 0x5004, 114 MLX5_REG_PAOS = 0x5006, 115 MLX5_REG_PFCC = 0x5007, 116 MLX5_REG_PPCNT = 0x5008, 117 MLX5_REG_PMAOS = 0x5012, 118 MLX5_REG_PUDE = 0x5009, 119 MLX5_REG_PMPE = 0x5010, 120 MLX5_REG_PELC = 0x500e, 121 MLX5_REG_PVLC = 0x500f, 122 MLX5_REG_PCMR = 0x5041, 123 MLX5_REG_PMLP = 0x5002, 124 MLX5_REG_PCAM = 0x507f, 125 MLX5_REG_NODE_DESC = 0x6001, 126 MLX5_REG_HOST_ENDIANNESS = 0x7004, 127 MLX5_REG_MCIA = 0x9014, 128 MLX5_REG_MLCR = 0x902b, 129 MLX5_REG_MPCNT = 0x9051, 130 MLX5_REG_MTPPS = 0x9053, 131 MLX5_REG_MTPPSE = 0x9054, 132 MLX5_REG_MCAM = 0x907f, 133 }; 134 135 enum mlx5_dcbx_oper_mode { 136 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, 137 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, 138 }; 139 140 enum { 141 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 142 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 143 }; 144 145 enum mlx5_page_fault_resume_flags { 146 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 147 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 148 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 149 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 150 }; 151 152 enum dbg_rsc_type { 153 MLX5_DBG_RSC_QP, 154 MLX5_DBG_RSC_EQ, 155 MLX5_DBG_RSC_CQ, 156 }; 157 158 struct mlx5_field_desc { 159 struct dentry *dent; 160 int i; 161 }; 162 163 struct mlx5_rsc_debug { 164 struct mlx5_core_dev *dev; 165 void *object; 166 enum dbg_rsc_type type; 167 struct dentry *root; 168 struct mlx5_field_desc fields[0]; 169 }; 170 171 enum mlx5_dev_event { 172 MLX5_DEV_EVENT_SYS_ERROR, 173 MLX5_DEV_EVENT_PORT_UP, 174 MLX5_DEV_EVENT_PORT_DOWN, 175 MLX5_DEV_EVENT_PORT_INITIALIZED, 176 MLX5_DEV_EVENT_LID_CHANGE, 177 MLX5_DEV_EVENT_PKEY_CHANGE, 178 MLX5_DEV_EVENT_GUID_CHANGE, 179 MLX5_DEV_EVENT_CLIENT_REREG, 180 MLX5_DEV_EVENT_PPS, 181 }; 182 183 enum mlx5_port_status { 184 MLX5_PORT_UP = 1, 185 MLX5_PORT_DOWN = 2, 186 }; 187 188 enum mlx5_eq_type { 189 MLX5_EQ_TYPE_COMP, 190 MLX5_EQ_TYPE_ASYNC, 191 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 192 MLX5_EQ_TYPE_PF, 193 #endif 194 }; 195 196 struct mlx5_bfreg_info { 197 u32 *sys_pages; 198 int num_low_latency_bfregs; 199 unsigned int *count; 200 201 /* 202 * protect bfreg allocation data structs 203 */ 204 struct mutex lock; 205 u32 ver; 206 bool lib_uar_4k; 207 u32 num_sys_pages; 208 }; 209 210 struct mlx5_cmd_first { 211 __be32 data[4]; 212 }; 213 214 struct mlx5_cmd_msg { 215 struct list_head list; 216 struct cmd_msg_cache *parent; 217 u32 len; 218 struct mlx5_cmd_first first; 219 struct mlx5_cmd_mailbox *next; 220 }; 221 222 struct mlx5_cmd_debug { 223 struct dentry *dbg_root; 224 struct dentry *dbg_in; 225 struct dentry *dbg_out; 226 struct dentry *dbg_outlen; 227 struct dentry *dbg_status; 228 struct dentry *dbg_run; 229 void *in_msg; 230 void *out_msg; 231 u8 status; 232 u16 inlen; 233 u16 outlen; 234 }; 235 236 struct cmd_msg_cache { 237 /* protect block chain allocations 238 */ 239 spinlock_t lock; 240 struct list_head head; 241 unsigned int max_inbox_size; 242 unsigned int num_ent; 243 }; 244 245 enum { 246 MLX5_NUM_COMMAND_CACHES = 5, 247 }; 248 249 struct mlx5_cmd_stats { 250 u64 sum; 251 u64 n; 252 struct dentry *root; 253 struct dentry *avg; 254 struct dentry *count; 255 /* protect command average calculations */ 256 spinlock_t lock; 257 }; 258 259 struct mlx5_cmd { 260 void *cmd_alloc_buf; 261 dma_addr_t alloc_dma; 262 int alloc_size; 263 void *cmd_buf; 264 dma_addr_t dma; 265 u16 cmdif_rev; 266 u8 log_sz; 267 u8 log_stride; 268 int max_reg_cmds; 269 int events; 270 u32 __iomem *vector; 271 272 /* protect command queue allocations 273 */ 274 spinlock_t alloc_lock; 275 276 /* protect token allocations 277 */ 278 spinlock_t token_lock; 279 u8 token; 280 unsigned long bitmask; 281 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 282 struct workqueue_struct *wq; 283 struct semaphore sem; 284 struct semaphore pages_sem; 285 int mode; 286 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 287 struct pci_pool *pool; 288 struct mlx5_cmd_debug dbg; 289 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; 290 int checksum_disabled; 291 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 292 }; 293 294 struct mlx5_port_caps { 295 int gid_table_len; 296 int pkey_table_len; 297 u8 ext_port_cap; 298 }; 299 300 struct mlx5_cmd_mailbox { 301 void *buf; 302 dma_addr_t dma; 303 struct mlx5_cmd_mailbox *next; 304 }; 305 306 struct mlx5_buf_list { 307 void *buf; 308 dma_addr_t map; 309 }; 310 311 struct mlx5_buf { 312 struct mlx5_buf_list direct; 313 int npages; 314 int size; 315 u8 page_shift; 316 }; 317 318 struct mlx5_frag_buf { 319 struct mlx5_buf_list *frags; 320 int npages; 321 int size; 322 u8 page_shift; 323 }; 324 325 struct mlx5_eq_tasklet { 326 struct list_head list; 327 struct list_head process_list; 328 struct tasklet_struct task; 329 /* lock on completion tasklet list */ 330 spinlock_t lock; 331 }; 332 333 struct mlx5_eq_pagefault { 334 struct work_struct work; 335 /* Pagefaults lock */ 336 spinlock_t lock; 337 struct workqueue_struct *wq; 338 mempool_t *pool; 339 }; 340 341 struct mlx5_eq { 342 struct mlx5_core_dev *dev; 343 __be32 __iomem *doorbell; 344 u32 cons_index; 345 struct mlx5_buf buf; 346 int size; 347 unsigned int irqn; 348 u8 eqn; 349 int nent; 350 u64 mask; 351 struct list_head list; 352 int index; 353 struct mlx5_rsc_debug *dbg; 354 enum mlx5_eq_type type; 355 union { 356 struct mlx5_eq_tasklet tasklet_ctx; 357 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 358 struct mlx5_eq_pagefault pf_ctx; 359 #endif 360 }; 361 }; 362 363 struct mlx5_core_psv { 364 u32 psv_idx; 365 struct psv_layout { 366 u32 pd; 367 u16 syndrome; 368 u16 reserved; 369 u16 bg; 370 u16 app_tag; 371 u32 ref_tag; 372 } psv; 373 }; 374 375 struct mlx5_core_sig_ctx { 376 struct mlx5_core_psv psv_memory; 377 struct mlx5_core_psv psv_wire; 378 struct ib_sig_err err_item; 379 bool sig_status_checked; 380 bool sig_err_exists; 381 u32 sigerr_count; 382 }; 383 384 enum { 385 MLX5_MKEY_MR = 1, 386 MLX5_MKEY_MW, 387 }; 388 389 struct mlx5_core_mkey { 390 u64 iova; 391 u64 size; 392 u32 key; 393 u32 pd; 394 u32 type; 395 }; 396 397 #define MLX5_24BIT_MASK ((1 << 24) - 1) 398 399 enum mlx5_res_type { 400 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 401 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 402 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 403 MLX5_RES_SRQ = 3, 404 MLX5_RES_XSRQ = 4, 405 }; 406 407 struct mlx5_core_rsc_common { 408 enum mlx5_res_type res; 409 atomic_t refcount; 410 struct completion free; 411 }; 412 413 struct mlx5_core_srq { 414 struct mlx5_core_rsc_common common; /* must be first */ 415 u32 srqn; 416 int max; 417 int max_gs; 418 int max_avail_gather; 419 int wqe_shift; 420 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 421 422 atomic_t refcount; 423 struct completion free; 424 }; 425 426 struct mlx5_eq_table { 427 void __iomem *update_ci; 428 void __iomem *update_arm_ci; 429 struct list_head comp_eqs_list; 430 struct mlx5_eq pages_eq; 431 struct mlx5_eq async_eq; 432 struct mlx5_eq cmd_eq; 433 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 434 struct mlx5_eq pfault_eq; 435 #endif 436 int num_comp_vectors; 437 /* protect EQs list 438 */ 439 spinlock_t lock; 440 }; 441 442 struct mlx5_uars_page { 443 void __iomem *map; 444 bool wc; 445 u32 index; 446 struct list_head list; 447 unsigned int bfregs; 448 unsigned long *reg_bitmap; /* for non fast path bf regs */ 449 unsigned long *fp_bitmap; 450 unsigned int reg_avail; 451 unsigned int fp_avail; 452 struct kref ref_count; 453 struct mlx5_core_dev *mdev; 454 }; 455 456 struct mlx5_bfreg_head { 457 /* protect blue flame registers allocations */ 458 struct mutex lock; 459 struct list_head list; 460 }; 461 462 struct mlx5_bfreg_data { 463 struct mlx5_bfreg_head reg_head; 464 struct mlx5_bfreg_head wc_head; 465 }; 466 467 struct mlx5_sq_bfreg { 468 void __iomem *map; 469 struct mlx5_uars_page *up; 470 bool wc; 471 u32 index; 472 unsigned int offset; 473 }; 474 475 struct mlx5_core_health { 476 struct health_buffer __iomem *health; 477 __be32 __iomem *health_counter; 478 struct timer_list timer; 479 u32 prev; 480 int miss_counter; 481 bool sick; 482 /* wq spinlock to synchronize draining */ 483 spinlock_t wq_lock; 484 struct workqueue_struct *wq; 485 unsigned long flags; 486 struct work_struct work; 487 struct delayed_work recover_work; 488 }; 489 490 struct mlx5_cq_table { 491 /* protect radix tree 492 */ 493 spinlock_t lock; 494 struct radix_tree_root tree; 495 }; 496 497 struct mlx5_qp_table { 498 /* protect radix tree 499 */ 500 spinlock_t lock; 501 struct radix_tree_root tree; 502 }; 503 504 struct mlx5_srq_table { 505 /* protect radix tree 506 */ 507 spinlock_t lock; 508 struct radix_tree_root tree; 509 }; 510 511 struct mlx5_mkey_table { 512 /* protect radix tree 513 */ 514 rwlock_t lock; 515 struct radix_tree_root tree; 516 }; 517 518 struct mlx5_vf_context { 519 int enabled; 520 }; 521 522 struct mlx5_core_sriov { 523 struct mlx5_vf_context *vfs_ctx; 524 int num_vfs; 525 int enabled_vfs; 526 }; 527 528 struct mlx5_irq_info { 529 cpumask_var_t mask; 530 char name[MLX5_MAX_IRQ_NAME]; 531 }; 532 533 struct mlx5_fc_stats { 534 struct rb_root counters; 535 struct list_head addlist; 536 /* protect addlist add/splice operations */ 537 spinlock_t addlist_lock; 538 539 struct workqueue_struct *wq; 540 struct delayed_work work; 541 unsigned long next_query; 542 }; 543 544 struct mlx5_eswitch; 545 struct mlx5_lag; 546 struct mlx5_pagefault; 547 548 struct mlx5_rl_entry { 549 u32 rate; 550 u16 index; 551 u16 refcount; 552 }; 553 554 struct mlx5_rl_table { 555 /* protect rate limit table */ 556 struct mutex rl_lock; 557 u16 max_size; 558 u32 max_rate; 559 u32 min_rate; 560 struct mlx5_rl_entry *rl_entry; 561 }; 562 563 enum port_module_event_status_type { 564 MLX5_MODULE_STATUS_PLUGGED = 0x1, 565 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 566 MLX5_MODULE_STATUS_ERROR = 0x3, 567 MLX5_MODULE_STATUS_NUM = 0x3, 568 }; 569 570 enum port_module_event_error_type { 571 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED, 572 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE, 573 MLX5_MODULE_EVENT_ERROR_BUS_STUCK, 574 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT, 575 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST, 576 MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER, 577 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE, 578 MLX5_MODULE_EVENT_ERROR_BAD_CABLE, 579 MLX5_MODULE_EVENT_ERROR_UNKNOWN, 580 MLX5_MODULE_EVENT_ERROR_NUM, 581 }; 582 583 struct mlx5_port_module_event_stats { 584 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 585 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 586 }; 587 588 struct mlx5_priv { 589 char name[MLX5_MAX_NAME_LEN]; 590 struct mlx5_eq_table eq_table; 591 struct msix_entry *msix_arr; 592 struct mlx5_irq_info *irq_info; 593 594 /* pages stuff */ 595 struct workqueue_struct *pg_wq; 596 struct rb_root page_root; 597 int fw_pages; 598 atomic_t reg_pages; 599 struct list_head free_list; 600 int vfs_pages; 601 602 struct mlx5_core_health health; 603 604 struct mlx5_srq_table srq_table; 605 606 /* start: qp staff */ 607 struct mlx5_qp_table qp_table; 608 struct dentry *qp_debugfs; 609 struct dentry *eq_debugfs; 610 struct dentry *cq_debugfs; 611 struct dentry *cmdif_debugfs; 612 /* end: qp staff */ 613 614 /* start: cq staff */ 615 struct mlx5_cq_table cq_table; 616 /* end: cq staff */ 617 618 /* start: mkey staff */ 619 struct mlx5_mkey_table mkey_table; 620 /* end: mkey staff */ 621 622 /* start: alloc staff */ 623 /* protect buffer alocation according to numa node */ 624 struct mutex alloc_mutex; 625 int numa_node; 626 627 struct mutex pgdir_mutex; 628 struct list_head pgdir_list; 629 /* end: alloc staff */ 630 struct dentry *dbg_root; 631 632 /* protect mkey key part */ 633 spinlock_t mkey_lock; 634 u8 mkey_key; 635 636 struct list_head dev_list; 637 struct list_head ctx_list; 638 spinlock_t ctx_lock; 639 640 struct mlx5_flow_steering *steering; 641 struct mlx5_eswitch *eswitch; 642 struct mlx5_core_sriov sriov; 643 struct mlx5_lag *lag; 644 unsigned long pci_dev_data; 645 struct mlx5_fc_stats fc_stats; 646 struct mlx5_rl_table rl_table; 647 648 struct mlx5_port_module_event_stats pme_stats; 649 650 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 651 void (*pfault)(struct mlx5_core_dev *dev, 652 void *context, 653 struct mlx5_pagefault *pfault); 654 void *pfault_ctx; 655 struct srcu_struct pfault_srcu; 656 #endif 657 struct mlx5_bfreg_data bfregs; 658 struct mlx5_uars_page *uar; 659 }; 660 661 enum mlx5_device_state { 662 MLX5_DEVICE_STATE_UP, 663 MLX5_DEVICE_STATE_INTERNAL_ERROR, 664 }; 665 666 enum mlx5_interface_state { 667 MLX5_INTERFACE_STATE_DOWN = BIT(0), 668 MLX5_INTERFACE_STATE_UP = BIT(1), 669 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), 670 }; 671 672 enum mlx5_pci_status { 673 MLX5_PCI_STATUS_DISABLED, 674 MLX5_PCI_STATUS_ENABLED, 675 }; 676 677 enum mlx5_pagefault_type_flags { 678 MLX5_PFAULT_REQUESTOR = 1 << 0, 679 MLX5_PFAULT_WRITE = 1 << 1, 680 MLX5_PFAULT_RDMA = 1 << 2, 681 }; 682 683 /* Contains the details of a pagefault. */ 684 struct mlx5_pagefault { 685 u32 bytes_committed; 686 u32 token; 687 u8 event_subtype; 688 u8 type; 689 union { 690 /* Initiator or send message responder pagefault details. */ 691 struct { 692 /* Received packet size, only valid for responders. */ 693 u32 packet_size; 694 /* 695 * Number of resource holding WQE, depends on type. 696 */ 697 u32 wq_num; 698 /* 699 * WQE index. Refers to either the send queue or 700 * receive queue, according to event_subtype. 701 */ 702 u16 wqe_index; 703 } wqe; 704 /* RDMA responder pagefault details */ 705 struct { 706 u32 r_key; 707 /* 708 * Received packet size, minimal size page fault 709 * resolution required for forward progress. 710 */ 711 u32 packet_size; 712 u32 rdma_op_len; 713 u64 rdma_va; 714 } rdma; 715 }; 716 717 struct mlx5_eq *eq; 718 struct work_struct work; 719 }; 720 721 struct mlx5_td { 722 struct list_head tirs_list; 723 u32 tdn; 724 }; 725 726 struct mlx5e_resources { 727 u32 pdn; 728 struct mlx5_td td; 729 struct mlx5_core_mkey mkey; 730 }; 731 732 struct mlx5_core_dev { 733 struct pci_dev *pdev; 734 /* sync pci state */ 735 struct mutex pci_status_mutex; 736 enum mlx5_pci_status pci_status; 737 u8 rev_id; 738 char board_id[MLX5_BOARD_ID_LEN]; 739 struct mlx5_cmd cmd; 740 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 741 struct { 742 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 743 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 744 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 745 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 746 } caps; 747 phys_addr_t iseg_base; 748 struct mlx5_init_seg __iomem *iseg; 749 enum mlx5_device_state state; 750 /* sync interface state */ 751 struct mutex intf_state_mutex; 752 unsigned long intf_state; 753 void (*event) (struct mlx5_core_dev *dev, 754 enum mlx5_dev_event event, 755 unsigned long param); 756 struct mlx5_priv priv; 757 struct mlx5_profile *profile; 758 atomic_t num_qps; 759 u32 issi; 760 struct mlx5e_resources mlx5e_res; 761 #ifdef CONFIG_RFS_ACCEL 762 struct cpu_rmap *rmap; 763 #endif 764 }; 765 766 struct mlx5_db { 767 __be32 *db; 768 union { 769 struct mlx5_db_pgdir *pgdir; 770 struct mlx5_ib_user_db_page *user_page; 771 } u; 772 dma_addr_t dma; 773 int index; 774 }; 775 776 enum { 777 MLX5_COMP_EQ_SIZE = 1024, 778 }; 779 780 enum { 781 MLX5_PTYS_IB = 1 << 0, 782 MLX5_PTYS_EN = 1 << 2, 783 }; 784 785 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 786 787 struct mlx5_cmd_work_ent { 788 struct mlx5_cmd_msg *in; 789 struct mlx5_cmd_msg *out; 790 void *uout; 791 int uout_size; 792 mlx5_cmd_cbk_t callback; 793 struct delayed_work cb_timeout_work; 794 void *context; 795 int idx; 796 struct completion done; 797 struct mlx5_cmd *cmd; 798 struct work_struct work; 799 struct mlx5_cmd_layout *lay; 800 int ret; 801 int page_queue; 802 u8 status; 803 u8 token; 804 u64 ts1; 805 u64 ts2; 806 u16 op; 807 }; 808 809 struct mlx5_pas { 810 u64 pa; 811 u8 log_sz; 812 }; 813 814 enum port_state_policy { 815 MLX5_POLICY_DOWN = 0, 816 MLX5_POLICY_UP = 1, 817 MLX5_POLICY_FOLLOW = 2, 818 MLX5_POLICY_INVALID = 0xffffffff 819 }; 820 821 enum phy_port_state { 822 MLX5_AAA_111 823 }; 824 825 struct mlx5_hca_vport_context { 826 u32 field_select; 827 bool sm_virt_aware; 828 bool has_smi; 829 bool has_raw; 830 enum port_state_policy policy; 831 enum phy_port_state phys_state; 832 enum ib_port_state vport_state; 833 u8 port_physical_state; 834 u64 sys_image_guid; 835 u64 port_guid; 836 u64 node_guid; 837 u32 cap_mask1; 838 u32 cap_mask1_perm; 839 u32 cap_mask2; 840 u32 cap_mask2_perm; 841 u16 lid; 842 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 843 u8 lmc; 844 u8 subnet_timeout; 845 u16 sm_lid; 846 u8 sm_sl; 847 u16 qkey_violation_counter; 848 u16 pkey_violation_counter; 849 bool grh_required; 850 }; 851 852 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 853 { 854 return buf->direct.buf + offset; 855 } 856 857 extern struct workqueue_struct *mlx5_core_wq; 858 859 #define STRUCT_FIELD(header, field) \ 860 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 861 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 862 863 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 864 { 865 return pci_get_drvdata(pdev); 866 } 867 868 extern struct dentry *mlx5_debugfs_root; 869 870 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 871 { 872 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 873 } 874 875 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 876 { 877 return ioread32be(&dev->iseg->fw_rev) >> 16; 878 } 879 880 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 881 { 882 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 883 } 884 885 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 886 { 887 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 888 } 889 890 static inline void *mlx5_vzalloc(unsigned long size) 891 { 892 void *rtn; 893 894 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 895 if (!rtn) 896 rtn = vzalloc(size); 897 return rtn; 898 } 899 900 static inline u32 mlx5_base_mkey(const u32 key) 901 { 902 return key & 0xffffff00u; 903 } 904 905 int mlx5_cmd_init(struct mlx5_core_dev *dev); 906 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 907 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 908 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 909 910 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 911 int out_size); 912 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 913 void *out, int out_size, mlx5_cmd_cbk_t callback, 914 void *context); 915 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 916 917 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 918 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 919 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 920 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 921 int mlx5_health_init(struct mlx5_core_dev *dev); 922 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 923 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 924 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 925 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, 926 struct mlx5_buf *buf, int node); 927 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); 928 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 929 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, 930 struct mlx5_frag_buf *buf, int node); 931 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); 932 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 933 gfp_t flags, int npages); 934 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 935 struct mlx5_cmd_mailbox *head); 936 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 937 struct mlx5_srq_attr *in); 938 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 939 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 940 struct mlx5_srq_attr *out); 941 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 942 u16 lwm, int is_srq); 943 void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 944 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 945 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 946 struct mlx5_core_mkey *mkey, 947 u32 *in, int inlen, 948 u32 *out, int outlen, 949 mlx5_cmd_cbk_t callback, void *context); 950 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 951 struct mlx5_core_mkey *mkey, 952 u32 *in, int inlen); 953 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 954 struct mlx5_core_mkey *mkey); 955 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 956 u32 *out, int outlen); 957 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, 958 u32 *mkey); 959 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 960 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 961 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 962 u16 opmod, u8 port); 963 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 964 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 965 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 966 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 967 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 968 s32 npages); 969 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 970 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 971 void mlx5_register_debugfs(void); 972 void mlx5_unregister_debugfs(void); 973 int mlx5_eq_init(struct mlx5_core_dev *dev); 974 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 975 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 976 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); 977 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 978 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 979 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 980 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 981 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); 982 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 983 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 984 int nent, u64 mask, const char *name, 985 enum mlx5_eq_type type); 986 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 987 int mlx5_start_eqs(struct mlx5_core_dev *dev); 988 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 989 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, 990 unsigned int *irqn); 991 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 992 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 993 994 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 995 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 996 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 997 int size_in, void *data_out, int size_out, 998 u16 reg_num, int arg, int write); 999 1000 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1001 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1002 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1003 u32 *out, int outlen); 1004 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1005 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1006 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1007 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1008 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1009 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1010 int node); 1011 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1012 1013 const char *mlx5_command_str(int command); 1014 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1015 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1016 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1017 int npsvs, u32 *sig_index); 1018 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1019 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1020 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 1021 struct mlx5_odp_caps *odp_caps); 1022 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, 1023 u8 port_num, void *out, size_t sz); 1024 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1025 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token, 1026 u32 wq_num, u8 type, int error); 1027 #endif 1028 1029 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1030 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1031 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u16 *index); 1032 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate); 1033 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); 1034 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 1035 bool map_wc, bool fast_path); 1036 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 1037 1038 static inline int fw_initializing(struct mlx5_core_dev *dev) 1039 { 1040 return ioread32be(&dev->iseg->initializing) >> 31; 1041 } 1042 1043 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1044 { 1045 return mkey >> 8; 1046 } 1047 1048 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1049 { 1050 return mkey_idx << 8; 1051 } 1052 1053 static inline u8 mlx5_mkey_variant(u32 mkey) 1054 { 1055 return mkey & 0xff; 1056 } 1057 1058 enum { 1059 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1060 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1061 }; 1062 1063 enum { 1064 MAX_MR_CACHE_ENTRIES = 21, 1065 }; 1066 1067 enum { 1068 MLX5_INTERFACE_PROTOCOL_IB = 0, 1069 MLX5_INTERFACE_PROTOCOL_ETH = 1, 1070 }; 1071 1072 struct mlx5_interface { 1073 void * (*add)(struct mlx5_core_dev *dev); 1074 void (*remove)(struct mlx5_core_dev *dev, void *context); 1075 int (*attach)(struct mlx5_core_dev *dev, void *context); 1076 void (*detach)(struct mlx5_core_dev *dev, void *context); 1077 void (*event)(struct mlx5_core_dev *dev, void *context, 1078 enum mlx5_dev_event event, unsigned long param); 1079 void (*pfault)(struct mlx5_core_dev *dev, 1080 void *context, 1081 struct mlx5_pagefault *pfault); 1082 void * (*get_dev)(void *context); 1083 int protocol; 1084 struct list_head list; 1085 }; 1086 1087 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1088 int mlx5_register_interface(struct mlx5_interface *intf); 1089 void mlx5_unregister_interface(struct mlx5_interface *intf); 1090 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 1091 1092 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); 1093 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); 1094 bool mlx5_lag_is_active(struct mlx5_core_dev *dev); 1095 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); 1096 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 1097 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 1098 1099 struct mlx5_profile { 1100 u64 mask; 1101 u8 log_max_qp; 1102 struct { 1103 int size; 1104 int limit; 1105 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1106 }; 1107 1108 enum { 1109 MLX5_PCI_DEV_IS_VF = 1 << 0, 1110 }; 1111 1112 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1113 { 1114 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1115 } 1116 1117 static inline int mlx5_get_gid_table_len(u16 param) 1118 { 1119 if (param > 4) { 1120 pr_warn("gid table length is zero\n"); 1121 return 0; 1122 } 1123 1124 return 8 * (1 << param); 1125 } 1126 1127 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1128 { 1129 return !!(dev->priv.rl_table.max_size); 1130 } 1131 1132 enum { 1133 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1134 }; 1135 1136 #endif /* MLX5_DRIVER_H */ 1137