1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DRIVER_H 34 #define MLX5_DRIVER_H 35 36 #include <linux/kernel.h> 37 #include <linux/completion.h> 38 #include <linux/pci.h> 39 #include <linux/spinlock_types.h> 40 #include <linux/semaphore.h> 41 #include <linux/slab.h> 42 #include <linux/vmalloc.h> 43 #include <linux/radix-tree.h> 44 45 #include <linux/mlx5/device.h> 46 #include <linux/mlx5/doorbell.h> 47 48 enum { 49 MLX5_BOARD_ID_LEN = 64, 50 MLX5_MAX_NAME_LEN = 16, 51 }; 52 53 enum { 54 /* one minute for the sake of bringup. Generally, commands must always 55 * complete and we may need to increase this timeout value 56 */ 57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, 58 MLX5_CMD_WQ_MAX_NAME = 32, 59 }; 60 61 enum { 62 CMD_OWNER_SW = 0x0, 63 CMD_OWNER_HW = 0x1, 64 CMD_STATUS_SUCCESS = 0, 65 }; 66 67 enum mlx5_sqp_t { 68 MLX5_SQP_SMI = 0, 69 MLX5_SQP_GSI = 1, 70 MLX5_SQP_IEEE_1588 = 2, 71 MLX5_SQP_SNIFFER = 3, 72 MLX5_SQP_SYNC_UMR = 4, 73 }; 74 75 enum { 76 MLX5_MAX_PORTS = 2, 77 }; 78 79 enum { 80 MLX5_EQ_VEC_PAGES = 0, 81 MLX5_EQ_VEC_CMD = 1, 82 MLX5_EQ_VEC_ASYNC = 2, 83 MLX5_EQ_VEC_COMP_BASE, 84 }; 85 86 enum { 87 MLX5_MAX_IRQ_NAME = 32 88 }; 89 90 enum { 91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, 92 MLX5_ATOMIC_MODE_CX = 2 << 16, 93 MLX5_ATOMIC_MODE_8B = 3 << 16, 94 MLX5_ATOMIC_MODE_16B = 4 << 16, 95 MLX5_ATOMIC_MODE_32B = 5 << 16, 96 MLX5_ATOMIC_MODE_64B = 6 << 16, 97 MLX5_ATOMIC_MODE_128B = 7 << 16, 98 MLX5_ATOMIC_MODE_256B = 8 << 16, 99 }; 100 101 enum { 102 MLX5_REG_PCAP = 0x5001, 103 MLX5_REG_PMTU = 0x5003, 104 MLX5_REG_PTYS = 0x5004, 105 MLX5_REG_PAOS = 0x5006, 106 MLX5_REG_PMAOS = 0x5012, 107 MLX5_REG_PUDE = 0x5009, 108 MLX5_REG_PMPE = 0x5010, 109 MLX5_REG_PELC = 0x500e, 110 MLX5_REG_PVLC = 0x500f, 111 MLX5_REG_PMLP = 0, /* TBD */ 112 MLX5_REG_NODE_DESC = 0x6001, 113 MLX5_REG_HOST_ENDIANNESS = 0x7004, 114 }; 115 116 enum mlx5_page_fault_resume_flags { 117 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, 118 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, 119 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, 120 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, 121 }; 122 123 enum dbg_rsc_type { 124 MLX5_DBG_RSC_QP, 125 MLX5_DBG_RSC_EQ, 126 MLX5_DBG_RSC_CQ, 127 }; 128 129 struct mlx5_field_desc { 130 struct dentry *dent; 131 int i; 132 }; 133 134 struct mlx5_rsc_debug { 135 struct mlx5_core_dev *dev; 136 void *object; 137 enum dbg_rsc_type type; 138 struct dentry *root; 139 struct mlx5_field_desc fields[0]; 140 }; 141 142 enum mlx5_dev_event { 143 MLX5_DEV_EVENT_SYS_ERROR, 144 MLX5_DEV_EVENT_PORT_UP, 145 MLX5_DEV_EVENT_PORT_DOWN, 146 MLX5_DEV_EVENT_PORT_INITIALIZED, 147 MLX5_DEV_EVENT_LID_CHANGE, 148 MLX5_DEV_EVENT_PKEY_CHANGE, 149 MLX5_DEV_EVENT_GUID_CHANGE, 150 MLX5_DEV_EVENT_CLIENT_REREG, 151 }; 152 153 enum mlx5_port_status { 154 MLX5_PORT_UP = 1 << 1, 155 MLX5_PORT_DOWN = 1 << 2, 156 }; 157 158 struct mlx5_uuar_info { 159 struct mlx5_uar *uars; 160 int num_uars; 161 int num_low_latency_uuars; 162 unsigned long *bitmap; 163 unsigned int *count; 164 struct mlx5_bf *bfs; 165 166 /* 167 * protect uuar allocation data structs 168 */ 169 struct mutex lock; 170 u32 ver; 171 }; 172 173 struct mlx5_bf { 174 void __iomem *reg; 175 void __iomem *regreg; 176 int buf_size; 177 struct mlx5_uar *uar; 178 unsigned long offset; 179 int need_lock; 180 /* protect blue flame buffer selection when needed 181 */ 182 spinlock_t lock; 183 184 /* serialize 64 bit writes when done as two 32 bit accesses 185 */ 186 spinlock_t lock32; 187 int uuarn; 188 }; 189 190 struct mlx5_cmd_first { 191 __be32 data[4]; 192 }; 193 194 struct mlx5_cmd_msg { 195 struct list_head list; 196 struct cache_ent *cache; 197 u32 len; 198 struct mlx5_cmd_first first; 199 struct mlx5_cmd_mailbox *next; 200 }; 201 202 struct mlx5_cmd_debug { 203 struct dentry *dbg_root; 204 struct dentry *dbg_in; 205 struct dentry *dbg_out; 206 struct dentry *dbg_outlen; 207 struct dentry *dbg_status; 208 struct dentry *dbg_run; 209 void *in_msg; 210 void *out_msg; 211 u8 status; 212 u16 inlen; 213 u16 outlen; 214 }; 215 216 struct cache_ent { 217 /* protect block chain allocations 218 */ 219 spinlock_t lock; 220 struct list_head head; 221 }; 222 223 struct cmd_msg_cache { 224 struct cache_ent large; 225 struct cache_ent med; 226 227 }; 228 229 struct mlx5_cmd_stats { 230 u64 sum; 231 u64 n; 232 struct dentry *root; 233 struct dentry *avg; 234 struct dentry *count; 235 /* protect command average calculations */ 236 spinlock_t lock; 237 }; 238 239 struct mlx5_cmd { 240 void *cmd_alloc_buf; 241 dma_addr_t alloc_dma; 242 int alloc_size; 243 void *cmd_buf; 244 dma_addr_t dma; 245 u16 cmdif_rev; 246 u8 log_sz; 247 u8 log_stride; 248 int max_reg_cmds; 249 int events; 250 u32 __iomem *vector; 251 252 /* protect command queue allocations 253 */ 254 spinlock_t alloc_lock; 255 256 /* protect token allocations 257 */ 258 spinlock_t token_lock; 259 u8 token; 260 unsigned long bitmask; 261 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 262 struct workqueue_struct *wq; 263 struct semaphore sem; 264 struct semaphore pages_sem; 265 int mode; 266 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 267 struct pci_pool *pool; 268 struct mlx5_cmd_debug dbg; 269 struct cmd_msg_cache cache; 270 int checksum_disabled; 271 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 272 }; 273 274 struct mlx5_port_caps { 275 int gid_table_len; 276 int pkey_table_len; 277 u8 ext_port_cap; 278 }; 279 280 struct mlx5_cmd_mailbox { 281 void *buf; 282 dma_addr_t dma; 283 struct mlx5_cmd_mailbox *next; 284 }; 285 286 struct mlx5_buf_list { 287 void *buf; 288 dma_addr_t map; 289 }; 290 291 struct mlx5_buf { 292 struct mlx5_buf_list direct; 293 int npages; 294 int size; 295 u8 page_shift; 296 }; 297 298 struct mlx5_eq { 299 struct mlx5_core_dev *dev; 300 __be32 __iomem *doorbell; 301 u32 cons_index; 302 struct mlx5_buf buf; 303 int size; 304 u8 irqn; 305 u8 eqn; 306 int nent; 307 u64 mask; 308 struct list_head list; 309 int index; 310 struct mlx5_rsc_debug *dbg; 311 }; 312 313 struct mlx5_core_psv { 314 u32 psv_idx; 315 struct psv_layout { 316 u32 pd; 317 u16 syndrome; 318 u16 reserved; 319 u16 bg; 320 u16 app_tag; 321 u32 ref_tag; 322 } psv; 323 }; 324 325 struct mlx5_core_sig_ctx { 326 struct mlx5_core_psv psv_memory; 327 struct mlx5_core_psv psv_wire; 328 struct ib_sig_err err_item; 329 bool sig_status_checked; 330 bool sig_err_exists; 331 u32 sigerr_count; 332 }; 333 334 struct mlx5_core_mr { 335 u64 iova; 336 u64 size; 337 u32 key; 338 u32 pd; 339 }; 340 341 enum mlx5_res_type { 342 MLX5_RES_QP, 343 MLX5_RES_SRQ, 344 MLX5_RES_XSRQ, 345 }; 346 347 struct mlx5_core_rsc_common { 348 enum mlx5_res_type res; 349 atomic_t refcount; 350 struct completion free; 351 }; 352 353 struct mlx5_core_srq { 354 struct mlx5_core_rsc_common common; /* must be first */ 355 u32 srqn; 356 int max; 357 int max_gs; 358 int max_avail_gather; 359 int wqe_shift; 360 void (*event) (struct mlx5_core_srq *, enum mlx5_event); 361 362 atomic_t refcount; 363 struct completion free; 364 }; 365 366 struct mlx5_eq_table { 367 void __iomem *update_ci; 368 void __iomem *update_arm_ci; 369 struct list_head comp_eqs_list; 370 struct mlx5_eq pages_eq; 371 struct mlx5_eq async_eq; 372 struct mlx5_eq cmd_eq; 373 int num_comp_vectors; 374 /* protect EQs list 375 */ 376 spinlock_t lock; 377 }; 378 379 struct mlx5_uar { 380 u32 index; 381 struct list_head bf_list; 382 unsigned free_bf_bmap; 383 void __iomem *wc_map; 384 void __iomem *map; 385 }; 386 387 388 struct mlx5_core_health { 389 struct health_buffer __iomem *health; 390 __be32 __iomem *health_counter; 391 struct timer_list timer; 392 struct list_head list; 393 u32 prev; 394 int miss_counter; 395 }; 396 397 struct mlx5_cq_table { 398 /* protect radix tree 399 */ 400 spinlock_t lock; 401 struct radix_tree_root tree; 402 }; 403 404 struct mlx5_qp_table { 405 /* protect radix tree 406 */ 407 spinlock_t lock; 408 struct radix_tree_root tree; 409 }; 410 411 struct mlx5_srq_table { 412 /* protect radix tree 413 */ 414 spinlock_t lock; 415 struct radix_tree_root tree; 416 }; 417 418 struct mlx5_mr_table { 419 /* protect radix tree 420 */ 421 rwlock_t lock; 422 struct radix_tree_root tree; 423 }; 424 425 struct mlx5_irq_info { 426 cpumask_var_t mask; 427 char name[MLX5_MAX_IRQ_NAME]; 428 }; 429 430 struct mlx5_priv { 431 char name[MLX5_MAX_NAME_LEN]; 432 struct mlx5_eq_table eq_table; 433 struct msix_entry *msix_arr; 434 struct mlx5_irq_info *irq_info; 435 struct mlx5_uuar_info uuari; 436 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 437 438 /* pages stuff */ 439 struct workqueue_struct *pg_wq; 440 struct rb_root page_root; 441 int fw_pages; 442 atomic_t reg_pages; 443 struct list_head free_list; 444 445 struct mlx5_core_health health; 446 447 struct mlx5_srq_table srq_table; 448 449 /* start: qp staff */ 450 struct mlx5_qp_table qp_table; 451 struct dentry *qp_debugfs; 452 struct dentry *eq_debugfs; 453 struct dentry *cq_debugfs; 454 struct dentry *cmdif_debugfs; 455 /* end: qp staff */ 456 457 /* start: cq staff */ 458 struct mlx5_cq_table cq_table; 459 /* end: cq staff */ 460 461 /* start: mr staff */ 462 struct mlx5_mr_table mr_table; 463 /* end: mr staff */ 464 465 /* start: alloc staff */ 466 struct mutex pgdir_mutex; 467 struct list_head pgdir_list; 468 /* end: alloc staff */ 469 struct dentry *dbg_root; 470 471 /* protect mkey key part */ 472 spinlock_t mkey_lock; 473 u8 mkey_key; 474 475 struct list_head dev_list; 476 struct list_head ctx_list; 477 spinlock_t ctx_lock; 478 }; 479 480 struct mlx5_core_dev { 481 struct pci_dev *pdev; 482 u8 rev_id; 483 char board_id[MLX5_BOARD_ID_LEN]; 484 struct mlx5_cmd cmd; 485 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 486 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 487 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 488 phys_addr_t iseg_base; 489 struct mlx5_init_seg __iomem *iseg; 490 void (*event) (struct mlx5_core_dev *dev, 491 enum mlx5_dev_event event, 492 unsigned long param); 493 struct mlx5_priv priv; 494 struct mlx5_profile *profile; 495 atomic_t num_qps; 496 u32 issi; 497 }; 498 499 struct mlx5_db { 500 __be32 *db; 501 union { 502 struct mlx5_db_pgdir *pgdir; 503 struct mlx5_ib_user_db_page *user_page; 504 } u; 505 dma_addr_t dma; 506 int index; 507 }; 508 509 enum { 510 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, 511 }; 512 513 enum { 514 MLX5_COMP_EQ_SIZE = 1024, 515 }; 516 517 enum { 518 MLX5_PTYS_IB = 1 << 0, 519 MLX5_PTYS_EN = 1 << 2, 520 }; 521 522 struct mlx5_db_pgdir { 523 struct list_head list; 524 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 525 __be32 *db_page; 526 dma_addr_t db_dma; 527 }; 528 529 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 530 531 struct mlx5_cmd_work_ent { 532 struct mlx5_cmd_msg *in; 533 struct mlx5_cmd_msg *out; 534 void *uout; 535 int uout_size; 536 mlx5_cmd_cbk_t callback; 537 void *context; 538 int idx; 539 struct completion done; 540 struct mlx5_cmd *cmd; 541 struct work_struct work; 542 struct mlx5_cmd_layout *lay; 543 int ret; 544 int page_queue; 545 u8 status; 546 u8 token; 547 u64 ts1; 548 u64 ts2; 549 u16 op; 550 }; 551 552 struct mlx5_pas { 553 u64 pa; 554 u8 log_sz; 555 }; 556 557 enum port_state_policy { 558 MLX5_AAA_000 559 }; 560 561 enum phy_port_state { 562 MLX5_AAA_111 563 }; 564 565 struct mlx5_hca_vport_context { 566 u32 field_select; 567 bool sm_virt_aware; 568 bool has_smi; 569 bool has_raw; 570 enum port_state_policy policy; 571 enum phy_port_state phys_state; 572 enum ib_port_state vport_state; 573 u8 port_physical_state; 574 u64 sys_image_guid; 575 u64 port_guid; 576 u64 node_guid; 577 u32 cap_mask1; 578 u32 cap_mask1_perm; 579 u32 cap_mask2; 580 u32 cap_mask2_perm; 581 u16 lid; 582 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ 583 u8 lmc; 584 u8 subnet_timeout; 585 u16 sm_lid; 586 u8 sm_sl; 587 u16 qkey_violation_counter; 588 u16 pkey_violation_counter; 589 bool grh_required; 590 }; 591 592 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) 593 { 594 return buf->direct.buf + offset; 595 } 596 597 extern struct workqueue_struct *mlx5_core_wq; 598 599 #define STRUCT_FIELD(header, field) \ 600 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 601 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 602 603 struct ib_field { 604 size_t struct_offset_bytes; 605 size_t struct_size_bytes; 606 int offset_bits; 607 int size_bits; 608 }; 609 610 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 611 { 612 return pci_get_drvdata(pdev); 613 } 614 615 extern struct dentry *mlx5_debugfs_root; 616 617 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 618 { 619 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 620 } 621 622 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 623 { 624 return ioread32be(&dev->iseg->fw_rev) >> 16; 625 } 626 627 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 628 { 629 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 630 } 631 632 static inline u16 cmdif_rev(struct mlx5_core_dev *dev) 633 { 634 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 635 } 636 637 static inline void *mlx5_vzalloc(unsigned long size) 638 { 639 void *rtn; 640 641 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 642 if (!rtn) 643 rtn = vzalloc(size); 644 return rtn; 645 } 646 647 static inline u32 mlx5_base_mkey(const u32 key) 648 { 649 return key & 0xffffff00u; 650 } 651 652 int mlx5_cmd_init(struct mlx5_core_dev *dev); 653 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 654 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 655 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 656 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 657 int mlx5_cmd_status_to_err_v2(void *ptr); 658 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 659 enum mlx5_cap_mode cap_mode); 660 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 661 int out_size); 662 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 663 void *out, int out_size, mlx5_cmd_cbk_t callback, 664 void *context); 665 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 666 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 667 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 668 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 669 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 670 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 671 void mlx5_health_cleanup(void); 672 void __init mlx5_health_init(void); 673 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 674 void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 675 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); 676 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 677 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, 678 gfp_t flags, int npages); 679 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, 680 struct mlx5_cmd_mailbox *head); 681 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 682 struct mlx5_create_srq_mbox_in *in, int inlen, 683 int is_xrc); 684 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 685 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 686 struct mlx5_query_srq_mbox_out *out); 687 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 688 u16 lwm, int is_srq); 689 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 690 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 691 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 692 struct mlx5_create_mkey_mbox_in *in, int inlen, 693 mlx5_cmd_cbk_t callback, void *context, 694 struct mlx5_create_mkey_mbox_out *out); 695 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 696 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 697 struct mlx5_query_mkey_mbox_out *out, int outlen); 698 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 699 u32 *mkey); 700 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 701 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 702 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 703 u16 opmod, u8 port); 704 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 705 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 706 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 707 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 708 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 709 s32 npages); 710 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 711 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 712 void mlx5_register_debugfs(void); 713 void mlx5_unregister_debugfs(void); 714 int mlx5_eq_init(struct mlx5_core_dev *dev); 715 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 716 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 717 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 718 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 719 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 720 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); 721 #endif 722 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 723 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 724 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); 725 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 726 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 727 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 728 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 729 int mlx5_start_eqs(struct mlx5_core_dev *dev); 730 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 731 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 732 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 733 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 734 735 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 736 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 737 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 738 int size_in, void *data_out, int size_out, 739 u16 reg_num, int arg, int write); 740 741 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 742 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 743 int ptys_size, int proto_mask, u8 local_port); 744 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 745 u32 *proto_cap, int proto_mask); 746 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 747 u32 *proto_admin, int proto_mask); 748 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, 749 u8 *link_width_oper, u8 local_port); 750 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev, 751 u8 *proto_oper, int proto_mask, 752 u8 local_port); 753 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 754 int proto_mask); 755 int mlx5_set_port_status(struct mlx5_core_dev *dev, 756 enum mlx5_port_status status); 757 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 758 759 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port); 760 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port); 761 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu, 762 u8 port); 763 764 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, 765 u8 *vl_hw_cap, u8 local_port); 766 767 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 768 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 769 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 770 struct mlx5_query_eq_mbox_out *out, int outlen); 771 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 772 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 773 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 774 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 775 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 776 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 777 778 const char *mlx5_command_str(int command); 779 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 780 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 781 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 782 int npsvs, u32 *sig_index); 783 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 784 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 785 int mlx5_query_odp_caps(struct mlx5_core_dev *dev, 786 struct mlx5_odp_caps *odp_caps); 787 788 static inline u32 mlx5_mkey_to_idx(u32 mkey) 789 { 790 return mkey >> 8; 791 } 792 793 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 794 { 795 return mkey_idx << 8; 796 } 797 798 static inline u8 mlx5_mkey_variant(u32 mkey) 799 { 800 return mkey & 0xff; 801 } 802 803 enum { 804 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 805 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 806 }; 807 808 enum { 809 MAX_MR_CACHE_ENTRIES = 16, 810 }; 811 812 enum { 813 MLX5_INTERFACE_PROTOCOL_IB = 0, 814 MLX5_INTERFACE_PROTOCOL_ETH = 1, 815 }; 816 817 struct mlx5_interface { 818 void * (*add)(struct mlx5_core_dev *dev); 819 void (*remove)(struct mlx5_core_dev *dev, void *context); 820 void (*event)(struct mlx5_core_dev *dev, void *context, 821 enum mlx5_dev_event event, unsigned long param); 822 void * (*get_dev)(void *context); 823 int protocol; 824 struct list_head list; 825 }; 826 827 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 828 int mlx5_register_interface(struct mlx5_interface *intf); 829 void mlx5_unregister_interface(struct mlx5_interface *intf); 830 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 831 832 struct mlx5_profile { 833 u64 mask; 834 u8 log_max_qp; 835 struct { 836 int size; 837 int limit; 838 } mr_cache[MAX_MR_CACHE_ENTRIES]; 839 }; 840 841 static inline int mlx5_get_gid_table_len(u16 param) 842 { 843 if (param > 4) { 844 pr_warn("gid table length is zero\n"); 845 return 0; 846 } 847 848 return 8 * (1 << param); 849 } 850 851 #endif /* MLX5_DRIVER_H */ 852