xref: /linux-6.15/include/linux/mlx5/driver.h (revision 01eadc8d) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35 
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59 
60 #define MLX5_ADEV_NAME "mlx5_core"
61 
62 enum {
63 	MLX5_BOARD_ID_LEN = 64,
64 };
65 
66 enum {
67 	/* one minute for the sake of bringup. Generally, commands must always
68 	 * complete and we may need to increase this timeout value
69 	 */
70 	MLX5_CMD_TIMEOUT_MSEC	= 60 * 1000,
71 	MLX5_CMD_WQ_MAX_NAME	= 32,
72 };
73 
74 enum {
75 	CMD_OWNER_SW		= 0x0,
76 	CMD_OWNER_HW		= 0x1,
77 	CMD_STATUS_SUCCESS	= 0,
78 };
79 
80 enum mlx5_sqp_t {
81 	MLX5_SQP_SMI		= 0,
82 	MLX5_SQP_GSI		= 1,
83 	MLX5_SQP_IEEE_1588	= 2,
84 	MLX5_SQP_SNIFFER	= 3,
85 	MLX5_SQP_SYNC_UMR	= 4,
86 };
87 
88 enum {
89 	MLX5_MAX_PORTS	= 2,
90 };
91 
92 enum {
93 	MLX5_ATOMIC_MODE_OFFSET = 16,
94 	MLX5_ATOMIC_MODE_IB_COMP = 1,
95 	MLX5_ATOMIC_MODE_CX = 2,
96 	MLX5_ATOMIC_MODE_8B = 3,
97 	MLX5_ATOMIC_MODE_16B = 4,
98 	MLX5_ATOMIC_MODE_32B = 5,
99 	MLX5_ATOMIC_MODE_64B = 6,
100 	MLX5_ATOMIC_MODE_128B = 7,
101 	MLX5_ATOMIC_MODE_256B = 8,
102 };
103 
104 enum {
105 	MLX5_REG_QPTS            = 0x4002,
106 	MLX5_REG_QETCR		 = 0x4005,
107 	MLX5_REG_QTCT		 = 0x400a,
108 	MLX5_REG_QPDPM           = 0x4013,
109 	MLX5_REG_QCAM            = 0x4019,
110 	MLX5_REG_DCBX_PARAM      = 0x4020,
111 	MLX5_REG_DCBX_APP        = 0x4021,
112 	MLX5_REG_FPGA_CAP	 = 0x4022,
113 	MLX5_REG_FPGA_CTRL	 = 0x4023,
114 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 	MLX5_REG_CORE_DUMP	 = 0x402e,
116 	MLX5_REG_PCAP		 = 0x5001,
117 	MLX5_REG_PMTU		 = 0x5003,
118 	MLX5_REG_PTYS		 = 0x5004,
119 	MLX5_REG_PAOS		 = 0x5006,
120 	MLX5_REG_PFCC            = 0x5007,
121 	MLX5_REG_PPCNT		 = 0x5008,
122 	MLX5_REG_PPTB            = 0x500b,
123 	MLX5_REG_PBMC            = 0x500c,
124 	MLX5_REG_PMAOS		 = 0x5012,
125 	MLX5_REG_PUDE		 = 0x5009,
126 	MLX5_REG_PMPE		 = 0x5010,
127 	MLX5_REG_PELC		 = 0x500e,
128 	MLX5_REG_PVLC		 = 0x500f,
129 	MLX5_REG_PCMR		 = 0x5041,
130 	MLX5_REG_PMLP		 = 0x5002,
131 	MLX5_REG_PPLM		 = 0x5023,
132 	MLX5_REG_PCAM		 = 0x507f,
133 	MLX5_REG_NODE_DESC	 = 0x6001,
134 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
135 	MLX5_REG_MCIA		 = 0x9014,
136 	MLX5_REG_MFRL		 = 0x9028,
137 	MLX5_REG_MLCR		 = 0x902b,
138 	MLX5_REG_MTRC_CAP	 = 0x9040,
139 	MLX5_REG_MTRC_CONF	 = 0x9041,
140 	MLX5_REG_MTRC_STDB	 = 0x9042,
141 	MLX5_REG_MTRC_CTRL	 = 0x9043,
142 	MLX5_REG_MPEIN		 = 0x9050,
143 	MLX5_REG_MPCNT		 = 0x9051,
144 	MLX5_REG_MTPPS		 = 0x9053,
145 	MLX5_REG_MTPPSE		 = 0x9054,
146 	MLX5_REG_MPEGC		 = 0x9056,
147 	MLX5_REG_MCQS		 = 0x9060,
148 	MLX5_REG_MCQI		 = 0x9061,
149 	MLX5_REG_MCC		 = 0x9062,
150 	MLX5_REG_MCDA		 = 0x9063,
151 	MLX5_REG_MCAM		 = 0x907f,
152 	MLX5_REG_MIRC		 = 0x9162,
153 	MLX5_REG_SBCAM		 = 0xB01F,
154 	MLX5_REG_RESOURCE_DUMP   = 0xC000,
155 };
156 
157 enum mlx5_qpts_trust_state {
158 	MLX5_QPTS_TRUST_PCP  = 1,
159 	MLX5_QPTS_TRUST_DSCP = 2,
160 };
161 
162 enum mlx5_dcbx_oper_mode {
163 	MLX5E_DCBX_PARAM_VER_OPER_HOST  = 0x0,
164 	MLX5E_DCBX_PARAM_VER_OPER_AUTO  = 0x3,
165 };
166 
167 enum {
168 	MLX5_ATOMIC_OPS_CMP_SWAP	= 1 << 0,
169 	MLX5_ATOMIC_OPS_FETCH_ADD	= 1 << 1,
170 	MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
171 	MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
172 };
173 
174 enum mlx5_page_fault_resume_flags {
175 	MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
176 	MLX5_PAGE_FAULT_RESUME_WRITE	 = 1 << 1,
177 	MLX5_PAGE_FAULT_RESUME_RDMA	 = 1 << 2,
178 	MLX5_PAGE_FAULT_RESUME_ERROR	 = 1 << 7,
179 };
180 
181 enum dbg_rsc_type {
182 	MLX5_DBG_RSC_QP,
183 	MLX5_DBG_RSC_EQ,
184 	MLX5_DBG_RSC_CQ,
185 };
186 
187 enum port_state_policy {
188 	MLX5_POLICY_DOWN	= 0,
189 	MLX5_POLICY_UP		= 1,
190 	MLX5_POLICY_FOLLOW	= 2,
191 	MLX5_POLICY_INVALID	= 0xffffffff
192 };
193 
194 enum mlx5_coredev_type {
195 	MLX5_COREDEV_PF,
196 	MLX5_COREDEV_VF
197 };
198 
199 struct mlx5_field_desc {
200 	int			i;
201 };
202 
203 struct mlx5_rsc_debug {
204 	struct mlx5_core_dev   *dev;
205 	void		       *object;
206 	enum dbg_rsc_type	type;
207 	struct dentry	       *root;
208 	struct mlx5_field_desc	fields[];
209 };
210 
211 enum mlx5_dev_event {
212 	MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
213 	MLX5_DEV_EVENT_PORT_AFFINITY = 129,
214 };
215 
216 enum mlx5_port_status {
217 	MLX5_PORT_UP        = 1,
218 	MLX5_PORT_DOWN      = 2,
219 };
220 
221 enum mlx5_cmdif_state {
222 	MLX5_CMDIF_STATE_UNINITIALIZED,
223 	MLX5_CMDIF_STATE_UP,
224 	MLX5_CMDIF_STATE_DOWN,
225 };
226 
227 struct mlx5_cmd_first {
228 	__be32		data[4];
229 };
230 
231 struct mlx5_cmd_msg {
232 	struct list_head		list;
233 	struct cmd_msg_cache	       *parent;
234 	u32				len;
235 	struct mlx5_cmd_first		first;
236 	struct mlx5_cmd_mailbox	       *next;
237 };
238 
239 struct mlx5_cmd_debug {
240 	struct dentry	       *dbg_root;
241 	void		       *in_msg;
242 	void		       *out_msg;
243 	u8			status;
244 	u16			inlen;
245 	u16			outlen;
246 };
247 
248 struct cmd_msg_cache {
249 	/* protect block chain allocations
250 	 */
251 	spinlock_t		lock;
252 	struct list_head	head;
253 	unsigned int		max_inbox_size;
254 	unsigned int		num_ent;
255 };
256 
257 enum {
258 	MLX5_NUM_COMMAND_CACHES = 5,
259 };
260 
261 struct mlx5_cmd_stats {
262 	u64		sum;
263 	u64		n;
264 	struct dentry  *root;
265 	/* protect command average calculations */
266 	spinlock_t	lock;
267 };
268 
269 struct mlx5_cmd {
270 	struct mlx5_nb    nb;
271 
272 	enum mlx5_cmdif_state	state;
273 	void	       *cmd_alloc_buf;
274 	dma_addr_t	alloc_dma;
275 	int		alloc_size;
276 	void	       *cmd_buf;
277 	dma_addr_t	dma;
278 	u16		cmdif_rev;
279 	u8		log_sz;
280 	u8		log_stride;
281 	int		max_reg_cmds;
282 	int		events;
283 	u32 __iomem    *vector;
284 
285 	/* protect command queue allocations
286 	 */
287 	spinlock_t	alloc_lock;
288 
289 	/* protect token allocations
290 	 */
291 	spinlock_t	token_lock;
292 	u8		token;
293 	unsigned long	bitmask;
294 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
295 	struct workqueue_struct *wq;
296 	struct semaphore sem;
297 	struct semaphore pages_sem;
298 	int	mode;
299 	u16     allowed_opcode;
300 	struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
301 	struct dma_pool *pool;
302 	struct mlx5_cmd_debug dbg;
303 	struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
304 	int checksum_disabled;
305 	struct mlx5_cmd_stats *stats;
306 };
307 
308 struct mlx5_port_caps {
309 	int	gid_table_len;
310 	int	pkey_table_len;
311 	u8	ext_port_cap;
312 	bool	has_smi;
313 };
314 
315 struct mlx5_cmd_mailbox {
316 	void	       *buf;
317 	dma_addr_t	dma;
318 	struct mlx5_cmd_mailbox *next;
319 };
320 
321 struct mlx5_buf_list {
322 	void		       *buf;
323 	dma_addr_t		map;
324 };
325 
326 struct mlx5_frag_buf {
327 	struct mlx5_buf_list	*frags;
328 	int			npages;
329 	int			size;
330 	u8			page_shift;
331 };
332 
333 struct mlx5_frag_buf_ctrl {
334 	struct mlx5_buf_list   *frags;
335 	u32			sz_m1;
336 	u16			frag_sz_m1;
337 	u16			strides_offset;
338 	u8			log_sz;
339 	u8			log_stride;
340 	u8			log_frag_strides;
341 };
342 
343 struct mlx5_core_psv {
344 	u32	psv_idx;
345 	struct psv_layout {
346 		u32	pd;
347 		u16	syndrome;
348 		u16	reserved;
349 		u16	bg;
350 		u16	app_tag;
351 		u32	ref_tag;
352 	} psv;
353 };
354 
355 struct mlx5_core_sig_ctx {
356 	struct mlx5_core_psv	psv_memory;
357 	struct mlx5_core_psv	psv_wire;
358 	struct ib_sig_err       err_item;
359 	bool			sig_status_checked;
360 	bool			sig_err_exists;
361 	u32			sigerr_count;
362 };
363 
364 enum {
365 	MLX5_MKEY_MR = 1,
366 	MLX5_MKEY_MW,
367 	MLX5_MKEY_INDIRECT_DEVX,
368 };
369 
370 struct mlx5_core_mkey {
371 	u64			iova;
372 	u64			size;
373 	u32			key;
374 	u32			pd;
375 	u32			type;
376 };
377 
378 #define MLX5_24BIT_MASK		((1 << 24) - 1)
379 
380 enum mlx5_res_type {
381 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
382 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
383 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
384 	MLX5_RES_SRQ	= 3,
385 	MLX5_RES_XSRQ	= 4,
386 	MLX5_RES_XRQ	= 5,
387 	MLX5_RES_DCT	= MLX5_EVENT_QUEUE_TYPE_DCT,
388 };
389 
390 struct mlx5_core_rsc_common {
391 	enum mlx5_res_type	res;
392 	refcount_t		refcount;
393 	struct completion	free;
394 };
395 
396 struct mlx5_uars_page {
397 	void __iomem	       *map;
398 	bool			wc;
399 	u32			index;
400 	struct list_head	list;
401 	unsigned int		bfregs;
402 	unsigned long	       *reg_bitmap; /* for non fast path bf regs */
403 	unsigned long	       *fp_bitmap;
404 	unsigned int		reg_avail;
405 	unsigned int		fp_avail;
406 	struct kref		ref_count;
407 	struct mlx5_core_dev   *mdev;
408 };
409 
410 struct mlx5_bfreg_head {
411 	/* protect blue flame registers allocations */
412 	struct mutex		lock;
413 	struct list_head	list;
414 };
415 
416 struct mlx5_bfreg_data {
417 	struct mlx5_bfreg_head	reg_head;
418 	struct mlx5_bfreg_head	wc_head;
419 };
420 
421 struct mlx5_sq_bfreg {
422 	void __iomem	       *map;
423 	struct mlx5_uars_page  *up;
424 	bool			wc;
425 	u32			index;
426 	unsigned int		offset;
427 };
428 
429 struct mlx5_core_health {
430 	struct health_buffer __iomem   *health;
431 	__be32 __iomem		       *health_counter;
432 	struct timer_list		timer;
433 	u32				prev;
434 	int				miss_counter;
435 	u8				synd;
436 	u32				fatal_error;
437 	u32				crdump_size;
438 	/* wq spinlock to synchronize draining */
439 	spinlock_t			wq_lock;
440 	struct workqueue_struct	       *wq;
441 	unsigned long			flags;
442 	struct work_struct		fatal_report_work;
443 	struct work_struct		report_work;
444 	struct delayed_work		recover_work;
445 	struct devlink_health_reporter *fw_reporter;
446 	struct devlink_health_reporter *fw_fatal_reporter;
447 };
448 
449 struct mlx5_qp_table {
450 	struct notifier_block   nb;
451 
452 	/* protect radix tree
453 	 */
454 	spinlock_t		lock;
455 	struct radix_tree_root	tree;
456 };
457 
458 struct mlx5_vf_context {
459 	int	enabled;
460 	u64	port_guid;
461 	u64	node_guid;
462 	/* Valid bits are used to validate administrative guid only.
463 	 * Enabled after ndo_set_vf_guid
464 	 */
465 	u8	port_guid_valid:1;
466 	u8	node_guid_valid:1;
467 	enum port_state_policy	policy;
468 };
469 
470 struct mlx5_core_sriov {
471 	struct mlx5_vf_context	*vfs_ctx;
472 	int			num_vfs;
473 	u16			max_vfs;
474 };
475 
476 struct mlx5_fc_pool {
477 	struct mlx5_core_dev *dev;
478 	struct mutex pool_lock; /* protects pool lists */
479 	struct list_head fully_used;
480 	struct list_head partially_used;
481 	struct list_head unused;
482 	int available_fcs;
483 	int used_fcs;
484 	int threshold;
485 };
486 
487 struct mlx5_fc_stats {
488 	spinlock_t counters_idr_lock; /* protects counters_idr */
489 	struct idr counters_idr;
490 	struct list_head counters;
491 	struct llist_head addlist;
492 	struct llist_head dellist;
493 
494 	struct workqueue_struct *wq;
495 	struct delayed_work work;
496 	unsigned long next_query;
497 	unsigned long sampling_interval; /* jiffies */
498 	u32 *bulk_query_out;
499 	struct mlx5_fc_pool fc_pool;
500 };
501 
502 struct mlx5_events;
503 struct mlx5_mpfs;
504 struct mlx5_eswitch;
505 struct mlx5_lag;
506 struct mlx5_devcom;
507 struct mlx5_fw_reset;
508 struct mlx5_eq_table;
509 struct mlx5_irq_table;
510 
511 struct mlx5_rate_limit {
512 	u32			rate;
513 	u32			max_burst_sz;
514 	u16			typical_pkt_sz;
515 };
516 
517 struct mlx5_rl_entry {
518 	u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
519 	u16 index;
520 	u64 refcount;
521 	u16 uid;
522 	u8 dedicated : 1;
523 };
524 
525 struct mlx5_rl_table {
526 	/* protect rate limit table */
527 	struct mutex            rl_lock;
528 	u16                     max_size;
529 	u32                     max_rate;
530 	u32                     min_rate;
531 	struct mlx5_rl_entry   *rl_entry;
532 };
533 
534 struct mlx5_core_roce {
535 	struct mlx5_flow_table *ft;
536 	struct mlx5_flow_group *fg;
537 	struct mlx5_flow_handle *allow_rule;
538 };
539 
540 enum {
541 	MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
542 	MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
543 };
544 
545 struct mlx5_adev {
546 	struct auxiliary_device adev;
547 	struct mlx5_core_dev *mdev;
548 	int idx;
549 };
550 
551 struct mlx5_priv {
552 	/* IRQ table valid only for real pci devices PF or VF */
553 	struct mlx5_irq_table   *irq_table;
554 	struct mlx5_eq_table	*eq_table;
555 
556 	/* pages stuff */
557 	struct mlx5_nb          pg_nb;
558 	struct workqueue_struct *pg_wq;
559 	struct xarray           page_root_xa;
560 	int			fw_pages;
561 	atomic_t		reg_pages;
562 	struct list_head	free_list;
563 	int			vfs_pages;
564 	int			host_pf_pages;
565 
566 	struct mlx5_core_health health;
567 
568 	/* start: qp staff */
569 	struct dentry	       *qp_debugfs;
570 	struct dentry	       *eq_debugfs;
571 	struct dentry	       *cq_debugfs;
572 	struct dentry	       *cmdif_debugfs;
573 	/* end: qp staff */
574 
575 	/* start: alloc staff */
576 	/* protect buffer alocation according to numa node */
577 	struct mutex            alloc_mutex;
578 	int                     numa_node;
579 
580 	struct mutex            pgdir_mutex;
581 	struct list_head        pgdir_list;
582 	/* end: alloc staff */
583 	struct dentry	       *dbg_root;
584 
585 	struct list_head        dev_list;
586 	struct list_head        ctx_list;
587 	spinlock_t              ctx_lock;
588 	struct mlx5_adev       **adev;
589 	int			adev_idx;
590 	struct mlx5_events      *events;
591 
592 	struct mlx5_flow_steering *steering;
593 	struct mlx5_mpfs        *mpfs;
594 	struct mlx5_eswitch     *eswitch;
595 	struct mlx5_core_sriov	sriov;
596 	struct mlx5_lag		*lag;
597 	u32			flags;
598 	struct mlx5_devcom	*devcom;
599 	struct mlx5_fw_reset	*fw_reset;
600 	struct mlx5_core_roce	roce;
601 	struct mlx5_fc_stats		fc_stats;
602 	struct mlx5_rl_table            rl_table;
603 
604 	struct mlx5_bfreg_data		bfregs;
605 	struct mlx5_uars_page	       *uar;
606 };
607 
608 enum mlx5_device_state {
609 	MLX5_DEVICE_STATE_UNINITIALIZED,
610 	MLX5_DEVICE_STATE_UP,
611 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
612 };
613 
614 enum mlx5_interface_state {
615 	MLX5_INTERFACE_STATE_UP = BIT(0),
616 };
617 
618 enum mlx5_pci_status {
619 	MLX5_PCI_STATUS_DISABLED,
620 	MLX5_PCI_STATUS_ENABLED,
621 };
622 
623 enum mlx5_pagefault_type_flags {
624 	MLX5_PFAULT_REQUESTOR = 1 << 0,
625 	MLX5_PFAULT_WRITE     = 1 << 1,
626 	MLX5_PFAULT_RDMA      = 1 << 2,
627 };
628 
629 struct mlx5_td {
630 	/* protects tirs list changes while tirs refresh */
631 	struct mutex     list_lock;
632 	struct list_head tirs_list;
633 	u32              tdn;
634 };
635 
636 struct mlx5e_resources {
637 	u32                        pdn;
638 	struct mlx5_td             td;
639 	struct mlx5_core_mkey      mkey;
640 	struct mlx5_sq_bfreg       bfreg;
641 };
642 
643 enum mlx5_sw_icm_type {
644 	MLX5_SW_ICM_TYPE_STEERING,
645 	MLX5_SW_ICM_TYPE_HEADER_MODIFY,
646 };
647 
648 #define MLX5_MAX_RESERVED_GIDS 8
649 
650 struct mlx5_rsvd_gids {
651 	unsigned int start;
652 	unsigned int count;
653 	struct ida ida;
654 };
655 
656 #define MAX_PIN_NUM	8
657 struct mlx5_pps {
658 	u8                         pin_caps[MAX_PIN_NUM];
659 	struct work_struct         out_work;
660 	u64                        start[MAX_PIN_NUM];
661 	u8                         enabled;
662 };
663 
664 struct mlx5_clock {
665 	struct mlx5_nb             pps_nb;
666 	seqlock_t                  lock;
667 	struct cyclecounter        cycles;
668 	struct timecounter         tc;
669 	struct hwtstamp_config     hwtstamp_config;
670 	u32                        nominal_c_mult;
671 	unsigned long              overflow_period;
672 	struct delayed_work        overflow_work;
673 	struct ptp_clock          *ptp;
674 	struct ptp_clock_info      ptp_info;
675 	struct mlx5_pps            pps_info;
676 };
677 
678 struct mlx5_dm;
679 struct mlx5_fw_tracer;
680 struct mlx5_vxlan;
681 struct mlx5_geneve;
682 struct mlx5_hv_vhca;
683 
684 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
685 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
686 
687 struct mlx5_core_dev {
688 	struct device *device;
689 	enum mlx5_coredev_type coredev_type;
690 	struct pci_dev	       *pdev;
691 	/* sync pci state */
692 	struct mutex		pci_status_mutex;
693 	enum mlx5_pci_status	pci_status;
694 	u8			rev_id;
695 	char			board_id[MLX5_BOARD_ID_LEN];
696 	struct mlx5_cmd		cmd;
697 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
698 	struct {
699 		u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
700 		u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
701 		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
702 		u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
703 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
704 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
705 		u8  embedded_cpu;
706 	} caps;
707 	u64			sys_image_guid;
708 	phys_addr_t		iseg_base;
709 	struct mlx5_init_seg __iomem *iseg;
710 	phys_addr_t             bar_addr;
711 	enum mlx5_device_state	state;
712 	/* sync interface state */
713 	struct mutex		intf_state_mutex;
714 	unsigned long		intf_state;
715 	struct mlx5_priv	priv;
716 	struct mlx5_profile	*profile;
717 	u32			issi;
718 	struct mlx5e_resources  mlx5e_res;
719 	struct mlx5_dm          *dm;
720 	struct mlx5_vxlan       *vxlan;
721 	struct mlx5_geneve      *geneve;
722 	struct {
723 		struct mlx5_rsvd_gids	reserved_gids;
724 		u32			roce_en;
725 	} roce;
726 #ifdef CONFIG_MLX5_FPGA
727 	struct mlx5_fpga_device *fpga;
728 #endif
729 #ifdef CONFIG_MLX5_ACCEL
730 	const struct mlx5_accel_ipsec_ops *ipsec_ops;
731 #endif
732 	struct mlx5_clock        clock;
733 	struct mlx5_ib_clock_info  *clock_info;
734 	struct mlx5_fw_tracer   *tracer;
735 	struct mlx5_rsc_dump    *rsc_dump;
736 	u32                      vsc_addr;
737 	struct mlx5_hv_vhca	*hv_vhca;
738 };
739 
740 struct mlx5_db {
741 	__be32			*db;
742 	union {
743 		struct mlx5_db_pgdir		*pgdir;
744 		struct mlx5_ib_user_db_page	*user_page;
745 	}			u;
746 	dma_addr_t		dma;
747 	int			index;
748 };
749 
750 enum {
751 	MLX5_COMP_EQ_SIZE = 1024,
752 };
753 
754 enum {
755 	MLX5_PTYS_IB = 1 << 0,
756 	MLX5_PTYS_EN = 1 << 2,
757 };
758 
759 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
760 
761 enum {
762 	MLX5_CMD_ENT_STATE_PENDING_COMP,
763 };
764 
765 struct mlx5_cmd_work_ent {
766 	unsigned long		state;
767 	struct mlx5_cmd_msg    *in;
768 	struct mlx5_cmd_msg    *out;
769 	void		       *uout;
770 	int			uout_size;
771 	mlx5_cmd_cbk_t		callback;
772 	struct delayed_work	cb_timeout_work;
773 	void		       *context;
774 	int			idx;
775 	struct completion	handling;
776 	struct completion	done;
777 	struct mlx5_cmd        *cmd;
778 	struct work_struct	work;
779 	struct mlx5_cmd_layout *lay;
780 	int			ret;
781 	int			page_queue;
782 	u8			status;
783 	u8			token;
784 	u64			ts1;
785 	u64			ts2;
786 	u16			op;
787 	bool			polling;
788 	/* Track the max comp handlers */
789 	refcount_t              refcnt;
790 };
791 
792 struct mlx5_pas {
793 	u64	pa;
794 	u8	log_sz;
795 };
796 
797 enum phy_port_state {
798 	MLX5_AAA_111
799 };
800 
801 struct mlx5_hca_vport_context {
802 	u32			field_select;
803 	bool			sm_virt_aware;
804 	bool			has_smi;
805 	bool			has_raw;
806 	enum port_state_policy	policy;
807 	enum phy_port_state	phys_state;
808 	enum ib_port_state	vport_state;
809 	u8			port_physical_state;
810 	u64			sys_image_guid;
811 	u64			port_guid;
812 	u64			node_guid;
813 	u32			cap_mask1;
814 	u32			cap_mask1_perm;
815 	u16			cap_mask2;
816 	u16			cap_mask2_perm;
817 	u16			lid;
818 	u8			init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
819 	u8			lmc;
820 	u8			subnet_timeout;
821 	u16			sm_lid;
822 	u8			sm_sl;
823 	u16			qkey_violation_counter;
824 	u16			pkey_violation_counter;
825 	bool			grh_required;
826 };
827 
828 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
829 {
830 		return buf->frags->buf + offset;
831 }
832 
833 #define STRUCT_FIELD(header, field) \
834 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
835 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
836 
837 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
838 {
839 	return pci_get_drvdata(pdev);
840 }
841 
842 extern struct dentry *mlx5_debugfs_root;
843 
844 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
845 {
846 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
847 }
848 
849 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
850 {
851 	return ioread32be(&dev->iseg->fw_rev) >> 16;
852 }
853 
854 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
855 {
856 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
857 }
858 
859 static inline u32 mlx5_base_mkey(const u32 key)
860 {
861 	return key & 0xffffff00u;
862 }
863 
864 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
865 					u8 log_stride, u8 log_sz,
866 					u16 strides_offset,
867 					struct mlx5_frag_buf_ctrl *fbc)
868 {
869 	fbc->frags      = frags;
870 	fbc->log_stride = log_stride;
871 	fbc->log_sz     = log_sz;
872 	fbc->sz_m1	= (1 << fbc->log_sz) - 1;
873 	fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
874 	fbc->frag_sz_m1	= (1 << fbc->log_frag_strides) - 1;
875 	fbc->strides_offset = strides_offset;
876 }
877 
878 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
879 				 u8 log_stride, u8 log_sz,
880 				 struct mlx5_frag_buf_ctrl *fbc)
881 {
882 	mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
883 }
884 
885 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
886 					  u32 ix)
887 {
888 	unsigned int frag;
889 
890 	ix  += fbc->strides_offset;
891 	frag = ix >> fbc->log_frag_strides;
892 
893 	return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
894 }
895 
896 static inline u32
897 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
898 {
899 	u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
900 
901 	return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
902 }
903 
904 enum {
905 	CMD_ALLOWED_OPCODE_ALL,
906 };
907 
908 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
909 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
910 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
911 
912 struct mlx5_async_ctx {
913 	struct mlx5_core_dev *dev;
914 	atomic_t num_inflight;
915 	struct wait_queue_head wait;
916 };
917 
918 struct mlx5_async_work;
919 
920 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
921 
922 struct mlx5_async_work {
923 	struct mlx5_async_ctx *ctx;
924 	mlx5_async_cbk_t user_callback;
925 };
926 
927 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
928 			     struct mlx5_async_ctx *ctx);
929 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
930 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
931 		     void *out, int out_size, mlx5_async_cbk_t callback,
932 		     struct mlx5_async_work *work);
933 
934 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
935 		  int out_size);
936 
937 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out)                             \
938 	({                                                                     \
939 		mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out,    \
940 			      MLX5_ST_SZ_BYTES(ifc_cmd##_out));                \
941 	})
942 
943 #define mlx5_cmd_exec_in(dev, ifc_cmd, in)                                     \
944 	({                                                                     \
945 		u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {};                   \
946 		mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out);                   \
947 	})
948 
949 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
950 			  void *out, int out_size);
951 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
952 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
953 
954 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
955 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
956 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
957 void mlx5_health_flush(struct mlx5_core_dev *dev);
958 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
959 int mlx5_health_init(struct mlx5_core_dev *dev);
960 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
961 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
962 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
963 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
964 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
965 		   int size, struct mlx5_frag_buf *buf);
966 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
967 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
968 			     struct mlx5_frag_buf *buf, int node);
969 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
970 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
971 						      gfp_t flags, int npages);
972 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
973 				 struct mlx5_cmd_mailbox *head);
974 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
975 			  struct mlx5_core_mkey *mkey,
976 			  u32 *in, int inlen);
977 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
978 			   struct mlx5_core_mkey *mkey);
979 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
980 			 u32 *out, int outlen);
981 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
982 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
983 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
984 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
985 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
986 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
987 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
988 				 s32 npages, bool ec_function);
989 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
990 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
991 void mlx5_register_debugfs(void);
992 void mlx5_unregister_debugfs(void);
993 
994 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
995 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
996 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
997 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
998 		    unsigned int *irqn);
999 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1000 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1001 
1002 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1003 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1004 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1005 			 int size_in, void *data_out, int size_out,
1006 			 u16 reg_num, int arg, int write);
1007 
1008 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1009 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1010 		       int node);
1011 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1012 
1013 const char *mlx5_command_str(int command);
1014 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1015 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1016 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1017 			 int npsvs, u32 *sig_index);
1018 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1019 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1020 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1021 			struct mlx5_odp_caps *odp_caps);
1022 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1023 			     u8 port_num, void *out, size_t sz);
1024 
1025 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1026 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1027 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1028 		     struct mlx5_rate_limit *rl);
1029 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1030 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1031 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1032 			 bool dedicated_entry, u16 *index);
1033 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1034 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1035 		       struct mlx5_rate_limit *rl_1);
1036 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1037 		     bool map_wc, bool fast_path);
1038 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1039 
1040 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1041 struct cpumask *
1042 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1043 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1044 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1045 			   u8 roce_version, u8 roce_l3_type, const u8 *gid,
1046 			   const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1047 
1048 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1049 {
1050 	return mkey >> 8;
1051 }
1052 
1053 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1054 {
1055 	return mkey_idx << 8;
1056 }
1057 
1058 static inline u8 mlx5_mkey_variant(u32 mkey)
1059 {
1060 	return mkey & 0xff;
1061 }
1062 
1063 enum {
1064 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
1065 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
1066 };
1067 
1068 enum {
1069 	MR_CACHE_LAST_STD_ENTRY = 20,
1070 	MLX5_IMR_MTT_CACHE_ENTRY,
1071 	MLX5_IMR_KSM_CACHE_ENTRY,
1072 	MAX_MR_CACHE_ENTRIES
1073 };
1074 
1075 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1076 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1077 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1078 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1079 
1080 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1081 
1082 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1083 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1084 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1085 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1086 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1087 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1088 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1089 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1090 			   struct net_device *slave);
1091 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1092 				 u64 *values,
1093 				 int num_counters,
1094 				 size_t *offsets);
1095 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1096 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1097 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1098 			 u64 length, u32 log_alignment, u16 uid,
1099 			 phys_addr_t *addr, u32 *obj_id);
1100 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1101 			   u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1102 
1103 #ifdef CONFIG_MLX5_CORE_IPOIB
1104 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1105 					  struct ib_device *ibdev,
1106 					  const char *name,
1107 					  void (*setup)(struct net_device *));
1108 #endif /* CONFIG_MLX5_CORE_IPOIB */
1109 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1110 			    struct ib_device *device,
1111 			    struct rdma_netdev_alloc_params *params);
1112 
1113 struct mlx5_profile {
1114 	u64	mask;
1115 	u8	log_max_qp;
1116 	struct {
1117 		int	size;
1118 		int	limit;
1119 	} mr_cache[MAX_MR_CACHE_ENTRIES];
1120 };
1121 
1122 enum {
1123 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
1124 };
1125 
1126 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1127 {
1128 	return dev->coredev_type == MLX5_COREDEV_PF;
1129 }
1130 
1131 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1132 {
1133 	return dev->coredev_type == MLX5_COREDEV_VF;
1134 }
1135 
1136 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1137 {
1138 	return dev->caps.embedded_cpu;
1139 }
1140 
1141 static inline bool
1142 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1143 {
1144 	return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1145 }
1146 
1147 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1148 {
1149 	return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1150 }
1151 
1152 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1153 {
1154 	return dev->priv.sriov.max_vfs;
1155 }
1156 
1157 static inline int mlx5_get_gid_table_len(u16 param)
1158 {
1159 	if (param > 4) {
1160 		pr_warn("gid table length is zero\n");
1161 		return 0;
1162 	}
1163 
1164 	return 8 * (1 << param);
1165 }
1166 
1167 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1168 {
1169 	return !!(dev->priv.rl_table.max_size);
1170 }
1171 
1172 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1173 {
1174 	return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1175 	       MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1176 }
1177 
1178 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1179 {
1180 	return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1181 }
1182 
1183 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1184 {
1185 	return mlx5_core_is_mp_slave(dev) ||
1186 	       mlx5_core_is_mp_master(dev);
1187 }
1188 
1189 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1190 {
1191 	if (!mlx5_core_mp_enabled(dev))
1192 		return 1;
1193 
1194 	return MLX5_CAP_GEN(dev, native_port_num);
1195 }
1196 
1197 enum {
1198 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1199 };
1200 
1201 static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1202 {
1203 	struct devlink *devlink = priv_to_devlink(dev);
1204 	union devlink_param_value val;
1205 
1206 	devlink_param_driverinit_value_get(devlink,
1207 					   DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1208 					   &val);
1209 	return val.vbool;
1210 }
1211 
1212 /**
1213  * mlx5_core_net - Provide net namespace of the mlx5_core_dev
1214  * @dev: mlx5 core device
1215  *
1216  * mlx5_core_net() returns the net namespace of mlx5 core device.
1217  * This can be called only in below described limited context.
1218  * (a) When a devlink instance for mlx5_core is registered and
1219  *     when devlink reload operation is disabled.
1220  *     or
1221  * (b) during devlink reload reload_down() and reload_up callbacks
1222  *     where it is ensured that devlink instance's net namespace is
1223  *     stable.
1224  */
1225 static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
1226 {
1227 	return devlink_net(priv_to_devlink(dev));
1228 }
1229 
1230 #endif /* MLX5_DRIVER_H */
1231