1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 39 #if defined(__LITTLE_ENDIAN) 40 #define MLX5_SET_HOST_ENDIANNESS 0 41 #elif defined(__BIG_ENDIAN) 42 #define MLX5_SET_HOST_ENDIANNESS 0x80 43 #else 44 #error Host endianness not defined 45 #endif 46 47 enum { 48 MLX5_MAX_COMMANDS = 32, 49 MLX5_CMD_DATA_BLOCK_SIZE = 512, 50 MLX5_PCI_CMD_XPORT = 7, 51 }; 52 53 enum { 54 MLX5_EXTENDED_UD_AV = 0x80000000, 55 }; 56 57 enum { 58 MLX5_CQ_STATE_ARMED = 9, 59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 60 MLX5_CQ_STATE_FIRED = 0xa, 61 }; 62 63 enum { 64 MLX5_STAT_RATE_OFFSET = 5, 65 }; 66 67 enum { 68 MLX5_INLINE_SEG = 0x80000000, 69 }; 70 71 enum { 72 MLX5_PERM_LOCAL_READ = 1 << 2, 73 MLX5_PERM_LOCAL_WRITE = 1 << 3, 74 MLX5_PERM_REMOTE_READ = 1 << 4, 75 MLX5_PERM_REMOTE_WRITE = 1 << 5, 76 MLX5_PERM_ATOMIC = 1 << 6, 77 MLX5_PERM_UMR_EN = 1 << 7, 78 }; 79 80 enum { 81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 86 }; 87 88 enum { 89 MLX5_ACCESS_MODE_PA = 0, 90 MLX5_ACCESS_MODE_MTT = 1, 91 MLX5_ACCESS_MODE_KLM = 2 92 }; 93 94 enum { 95 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 97 MLX5_MKEY_BSF_EN = 1 << 30, 98 MLX5_MKEY_LEN64 = 1 << 31, 99 }; 100 101 enum { 102 MLX5_EN_RD = (u64)1, 103 MLX5_EN_WR = (u64)2 104 }; 105 106 enum { 107 MLX5_BF_REGS_PER_PAGE = 4, 108 MLX5_MAX_UAR_PAGES = 1 << 8, 109 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_BF_REGS_PER_PAGE, 110 }; 111 112 enum { 113 MLX5_MKEY_MASK_LEN = 1ull << 0, 114 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 115 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 116 MLX5_MKEY_MASK_PD = 1ull << 7, 117 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 118 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 119 MLX5_MKEY_MASK_KEY = 1ull << 13, 120 MLX5_MKEY_MASK_QPN = 1ull << 14, 121 MLX5_MKEY_MASK_LR = 1ull << 17, 122 MLX5_MKEY_MASK_LW = 1ull << 18, 123 MLX5_MKEY_MASK_RR = 1ull << 19, 124 MLX5_MKEY_MASK_RW = 1ull << 20, 125 MLX5_MKEY_MASK_A = 1ull << 21, 126 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 127 MLX5_MKEY_MASK_FREE = 1ull << 29, 128 }; 129 130 enum mlx5_event { 131 MLX5_EVENT_TYPE_COMP = 0x0, 132 133 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 134 MLX5_EVENT_TYPE_COMM_EST = 0x02, 135 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 136 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 137 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 138 139 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 140 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 141 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 142 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 143 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 144 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 145 146 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 147 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 148 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 149 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 150 151 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 152 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 153 154 MLX5_EVENT_TYPE_CMD = 0x0a, 155 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 156 }; 157 158 enum { 159 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 160 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 161 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 162 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 163 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 164 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 165 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 166 }; 167 168 enum { 169 MLX5_DEV_CAP_FLAG_RC = 1LL << 0, 170 MLX5_DEV_CAP_FLAG_UC = 1LL << 1, 171 MLX5_DEV_CAP_FLAG_UD = 1LL << 2, 172 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 173 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6, 174 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 175 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 176 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 177 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 178 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 179 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, 180 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, 181 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, 182 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 183 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41, 184 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 1LL << 46, 185 }; 186 187 enum { 188 MLX5_OPCODE_NOP = 0x00, 189 MLX5_OPCODE_SEND_INVAL = 0x01, 190 MLX5_OPCODE_RDMA_WRITE = 0x08, 191 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 192 MLX5_OPCODE_SEND = 0x0a, 193 MLX5_OPCODE_SEND_IMM = 0x0b, 194 MLX5_OPCODE_RDMA_READ = 0x10, 195 MLX5_OPCODE_ATOMIC_CS = 0x11, 196 MLX5_OPCODE_ATOMIC_FA = 0x12, 197 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 198 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 199 MLX5_OPCODE_BIND_MW = 0x18, 200 MLX5_OPCODE_CONFIG_CMD = 0x1f, 201 202 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 203 MLX5_RECV_OPCODE_SEND = 0x01, 204 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 205 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 206 207 MLX5_CQE_OPCODE_ERROR = 0x1e, 208 MLX5_CQE_OPCODE_RESIZE = 0x16, 209 210 MLX5_OPCODE_SET_PSV = 0x20, 211 MLX5_OPCODE_GET_PSV = 0x21, 212 MLX5_OPCODE_CHECK_PSV = 0x22, 213 MLX5_OPCODE_RGET_PSV = 0x26, 214 MLX5_OPCODE_RCHECK_PSV = 0x27, 215 216 MLX5_OPCODE_UMR = 0x25, 217 218 }; 219 220 enum { 221 MLX5_SET_PORT_RESET_QKEY = 0, 222 MLX5_SET_PORT_GUID0 = 16, 223 MLX5_SET_PORT_NODE_GUID = 17, 224 MLX5_SET_PORT_SYS_GUID = 18, 225 MLX5_SET_PORT_GID_TABLE = 19, 226 MLX5_SET_PORT_PKEY_TABLE = 20, 227 }; 228 229 enum { 230 MLX5_MAX_PAGE_SHIFT = 31 231 }; 232 233 struct mlx5_inbox_hdr { 234 __be16 opcode; 235 u8 rsvd[4]; 236 __be16 opmod; 237 }; 238 239 struct mlx5_outbox_hdr { 240 u8 status; 241 u8 rsvd[3]; 242 __be32 syndrome; 243 }; 244 245 struct mlx5_cmd_query_adapter_mbox_in { 246 struct mlx5_inbox_hdr hdr; 247 u8 rsvd[8]; 248 }; 249 250 struct mlx5_cmd_query_adapter_mbox_out { 251 struct mlx5_outbox_hdr hdr; 252 u8 rsvd0[24]; 253 u8 intapin; 254 u8 rsvd1[13]; 255 __be16 vsd_vendor_id; 256 u8 vsd[208]; 257 u8 vsd_psid[16]; 258 }; 259 260 struct mlx5_hca_cap { 261 u8 rsvd1[16]; 262 u8 log_max_srq_sz; 263 u8 log_max_qp_sz; 264 u8 rsvd2; 265 u8 log_max_qp; 266 u8 log_max_strq_sz; 267 u8 log_max_srqs; 268 u8 rsvd4[2]; 269 u8 rsvd5; 270 u8 log_max_cq_sz; 271 u8 rsvd6; 272 u8 log_max_cq; 273 u8 log_max_eq_sz; 274 u8 log_max_mkey; 275 u8 rsvd7; 276 u8 log_max_eq; 277 u8 max_indirection; 278 u8 log_max_mrw_sz; 279 u8 log_max_bsf_list_sz; 280 u8 log_max_klm_list_sz; 281 u8 rsvd_8_0; 282 u8 log_max_ra_req_dc; 283 u8 rsvd_8_1; 284 u8 log_max_ra_res_dc; 285 u8 rsvd9; 286 u8 log_max_ra_req_qp; 287 u8 rsvd10; 288 u8 log_max_ra_res_qp; 289 u8 rsvd11[4]; 290 __be16 max_qp_count; 291 __be16 rsvd12; 292 u8 rsvd13; 293 u8 local_ca_ack_delay; 294 u8 rsvd14; 295 u8 num_ports; 296 u8 log_max_msg; 297 u8 rsvd15[3]; 298 __be16 stat_rate_support; 299 u8 rsvd16[2]; 300 __be64 flags; 301 u8 rsvd17; 302 u8 uar_sz; 303 u8 rsvd18; 304 u8 log_pg_sz; 305 __be16 bf_log_bf_reg_size; 306 u8 rsvd19[4]; 307 __be16 max_desc_sz_sq; 308 u8 rsvd20[2]; 309 __be16 max_desc_sz_rq; 310 u8 rsvd21[2]; 311 __be16 max_desc_sz_sq_dc; 312 u8 rsvd22[4]; 313 __be16 max_qp_mcg; 314 u8 rsvd23; 315 u8 log_max_mcg; 316 u8 rsvd24; 317 u8 log_max_pd; 318 u8 rsvd25; 319 u8 log_max_xrcd; 320 u8 rsvd26[42]; 321 __be16 log_uar_page_sz; 322 u8 rsvd27[28]; 323 u8 log_msx_atomic_size_qp; 324 u8 rsvd28[2]; 325 u8 log_msx_atomic_size_dc; 326 u8 rsvd29[76]; 327 }; 328 329 330 struct mlx5_cmd_query_hca_cap_mbox_in { 331 struct mlx5_inbox_hdr hdr; 332 u8 rsvd[8]; 333 }; 334 335 336 struct mlx5_cmd_query_hca_cap_mbox_out { 337 struct mlx5_outbox_hdr hdr; 338 u8 rsvd0[8]; 339 struct mlx5_hca_cap hca_cap; 340 }; 341 342 343 struct mlx5_cmd_set_hca_cap_mbox_in { 344 struct mlx5_inbox_hdr hdr; 345 u8 rsvd[8]; 346 struct mlx5_hca_cap hca_cap; 347 }; 348 349 350 struct mlx5_cmd_set_hca_cap_mbox_out { 351 struct mlx5_outbox_hdr hdr; 352 u8 rsvd0[8]; 353 }; 354 355 356 struct mlx5_cmd_init_hca_mbox_in { 357 struct mlx5_inbox_hdr hdr; 358 u8 rsvd0[2]; 359 __be16 profile; 360 u8 rsvd1[4]; 361 }; 362 363 struct mlx5_cmd_init_hca_mbox_out { 364 struct mlx5_outbox_hdr hdr; 365 u8 rsvd[8]; 366 }; 367 368 struct mlx5_cmd_teardown_hca_mbox_in { 369 struct mlx5_inbox_hdr hdr; 370 u8 rsvd0[2]; 371 __be16 profile; 372 u8 rsvd1[4]; 373 }; 374 375 struct mlx5_cmd_teardown_hca_mbox_out { 376 struct mlx5_outbox_hdr hdr; 377 u8 rsvd[8]; 378 }; 379 380 struct mlx5_cmd_layout { 381 u8 type; 382 u8 rsvd0[3]; 383 __be32 inlen; 384 __be64 in_ptr; 385 __be32 in[4]; 386 __be32 out[4]; 387 __be64 out_ptr; 388 __be32 outlen; 389 u8 token; 390 u8 sig; 391 u8 rsvd1; 392 u8 status_own; 393 }; 394 395 396 struct health_buffer { 397 __be32 assert_var[5]; 398 __be32 rsvd0[3]; 399 __be32 assert_exit_ptr; 400 __be32 assert_callra; 401 __be32 rsvd1[2]; 402 __be32 fw_ver; 403 __be32 hw_id; 404 __be32 rsvd2; 405 u8 irisc_index; 406 u8 synd; 407 __be16 ext_sync; 408 }; 409 410 struct mlx5_init_seg { 411 __be32 fw_rev; 412 __be32 cmdif_rev_fw_sub; 413 __be32 rsvd0[2]; 414 __be32 cmdq_addr_h; 415 __be32 cmdq_addr_l_sz; 416 __be32 cmd_dbell; 417 __be32 rsvd1[121]; 418 struct health_buffer health; 419 __be32 rsvd2[884]; 420 __be32 health_counter; 421 __be32 rsvd3[1023]; 422 __be64 ieee1588_clk; 423 __be32 ieee1588_clk_type; 424 __be32 clr_intx; 425 }; 426 427 struct mlx5_eqe_comp { 428 __be32 reserved[6]; 429 __be32 cqn; 430 }; 431 432 struct mlx5_eqe_qp_srq { 433 __be32 reserved[6]; 434 __be32 qp_srq_n; 435 }; 436 437 struct mlx5_eqe_cq_err { 438 __be32 cqn; 439 u8 reserved1[7]; 440 u8 syndrome; 441 }; 442 443 struct mlx5_eqe_dropped_packet { 444 }; 445 446 struct mlx5_eqe_port_state { 447 u8 reserved0[8]; 448 u8 port; 449 }; 450 451 struct mlx5_eqe_gpio { 452 __be32 reserved0[2]; 453 __be64 gpio_event; 454 }; 455 456 struct mlx5_eqe_congestion { 457 u8 type; 458 u8 rsvd0; 459 u8 congestion_level; 460 }; 461 462 struct mlx5_eqe_stall_vl { 463 u8 rsvd0[3]; 464 u8 port_vl; 465 }; 466 467 struct mlx5_eqe_cmd { 468 __be32 vector; 469 __be32 rsvd[6]; 470 }; 471 472 struct mlx5_eqe_page_req { 473 u8 rsvd0[2]; 474 __be16 func_id; 475 u8 rsvd1[2]; 476 __be16 num_pages; 477 __be32 rsvd2[5]; 478 }; 479 480 union ev_data { 481 __be32 raw[7]; 482 struct mlx5_eqe_cmd cmd; 483 struct mlx5_eqe_comp comp; 484 struct mlx5_eqe_qp_srq qp_srq; 485 struct mlx5_eqe_cq_err cq_err; 486 struct mlx5_eqe_dropped_packet dp; 487 struct mlx5_eqe_port_state port; 488 struct mlx5_eqe_gpio gpio; 489 struct mlx5_eqe_congestion cong; 490 struct mlx5_eqe_stall_vl stall_vl; 491 struct mlx5_eqe_page_req req_pages; 492 } __packed; 493 494 struct mlx5_eqe { 495 u8 rsvd0; 496 u8 type; 497 u8 rsvd1; 498 u8 sub_type; 499 __be32 rsvd2[7]; 500 union ev_data data; 501 __be16 rsvd3; 502 u8 signature; 503 u8 owner; 504 } __packed; 505 506 struct mlx5_cmd_prot_block { 507 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 508 u8 rsvd0[48]; 509 __be64 next; 510 __be32 block_num; 511 u8 rsvd1; 512 u8 token; 513 u8 ctrl_sig; 514 u8 sig; 515 }; 516 517 struct mlx5_err_cqe { 518 u8 rsvd0[32]; 519 __be32 srqn; 520 u8 rsvd1[18]; 521 u8 vendor_err_synd; 522 u8 syndrome; 523 __be32 s_wqe_opcode_qpn; 524 __be16 wqe_counter; 525 u8 signature; 526 u8 op_own; 527 }; 528 529 struct mlx5_cqe64 { 530 u8 rsvd0[17]; 531 u8 ml_path; 532 u8 rsvd20[4]; 533 __be16 slid; 534 __be32 flags_rqpn; 535 u8 rsvd28[4]; 536 __be32 srqn; 537 __be32 imm_inval_pkey; 538 u8 rsvd40[4]; 539 __be32 byte_cnt; 540 __be64 timestamp; 541 __be32 sop_drop_qpn; 542 __be16 wqe_counter; 543 u8 signature; 544 u8 op_own; 545 }; 546 547 struct mlx5_wqe_srq_next_seg { 548 u8 rsvd0[2]; 549 __be16 next_wqe_index; 550 u8 signature; 551 u8 rsvd1[11]; 552 }; 553 554 union mlx5_ext_cqe { 555 struct ib_grh grh; 556 u8 inl[64]; 557 }; 558 559 struct mlx5_cqe128 { 560 union mlx5_ext_cqe inl_grh; 561 struct mlx5_cqe64 cqe64; 562 }; 563 564 struct mlx5_srq_ctx { 565 u8 state_log_sz; 566 u8 rsvd0[3]; 567 __be32 flags_xrcd; 568 __be32 pgoff_cqn; 569 u8 rsvd1[4]; 570 u8 log_pg_sz; 571 u8 rsvd2[7]; 572 __be32 pd; 573 __be16 lwm; 574 __be16 wqe_cnt; 575 u8 rsvd3[8]; 576 __be64 db_record; 577 }; 578 579 struct mlx5_create_srq_mbox_in { 580 struct mlx5_inbox_hdr hdr; 581 __be32 input_srqn; 582 u8 rsvd0[4]; 583 struct mlx5_srq_ctx ctx; 584 u8 rsvd1[208]; 585 __be64 pas[0]; 586 }; 587 588 struct mlx5_create_srq_mbox_out { 589 struct mlx5_outbox_hdr hdr; 590 __be32 srqn; 591 u8 rsvd[4]; 592 }; 593 594 struct mlx5_destroy_srq_mbox_in { 595 struct mlx5_inbox_hdr hdr; 596 __be32 srqn; 597 u8 rsvd[4]; 598 }; 599 600 struct mlx5_destroy_srq_mbox_out { 601 struct mlx5_outbox_hdr hdr; 602 u8 rsvd[8]; 603 }; 604 605 struct mlx5_query_srq_mbox_in { 606 struct mlx5_inbox_hdr hdr; 607 __be32 srqn; 608 u8 rsvd0[4]; 609 }; 610 611 struct mlx5_query_srq_mbox_out { 612 struct mlx5_outbox_hdr hdr; 613 u8 rsvd0[8]; 614 struct mlx5_srq_ctx ctx; 615 u8 rsvd1[32]; 616 __be64 pas[0]; 617 }; 618 619 struct mlx5_arm_srq_mbox_in { 620 struct mlx5_inbox_hdr hdr; 621 __be32 srqn; 622 __be16 rsvd; 623 __be16 lwm; 624 }; 625 626 struct mlx5_arm_srq_mbox_out { 627 struct mlx5_outbox_hdr hdr; 628 u8 rsvd[8]; 629 }; 630 631 struct mlx5_cq_context { 632 u8 status; 633 u8 cqe_sz_flags; 634 u8 st; 635 u8 rsvd3; 636 u8 rsvd4[6]; 637 __be16 page_offset; 638 __be32 log_sz_usr_page; 639 __be16 cq_period; 640 __be16 cq_max_count; 641 __be16 rsvd20; 642 __be16 c_eqn; 643 u8 log_pg_sz; 644 u8 rsvd25[7]; 645 __be32 last_notified_index; 646 __be32 solicit_producer_index; 647 __be32 consumer_counter; 648 __be32 producer_counter; 649 u8 rsvd48[8]; 650 __be64 db_record_addr; 651 }; 652 653 struct mlx5_create_cq_mbox_in { 654 struct mlx5_inbox_hdr hdr; 655 __be32 input_cqn; 656 u8 rsvdx[4]; 657 struct mlx5_cq_context ctx; 658 u8 rsvd6[192]; 659 __be64 pas[0]; 660 }; 661 662 struct mlx5_create_cq_mbox_out { 663 struct mlx5_outbox_hdr hdr; 664 __be32 cqn; 665 u8 rsvd0[4]; 666 }; 667 668 struct mlx5_destroy_cq_mbox_in { 669 struct mlx5_inbox_hdr hdr; 670 __be32 cqn; 671 u8 rsvd0[4]; 672 }; 673 674 struct mlx5_destroy_cq_mbox_out { 675 struct mlx5_outbox_hdr hdr; 676 u8 rsvd0[8]; 677 }; 678 679 struct mlx5_query_cq_mbox_in { 680 struct mlx5_inbox_hdr hdr; 681 __be32 cqn; 682 u8 rsvd0[4]; 683 }; 684 685 struct mlx5_query_cq_mbox_out { 686 struct mlx5_outbox_hdr hdr; 687 u8 rsvd0[8]; 688 struct mlx5_cq_context ctx; 689 u8 rsvd6[16]; 690 __be64 pas[0]; 691 }; 692 693 struct mlx5_enable_hca_mbox_in { 694 struct mlx5_inbox_hdr hdr; 695 u8 rsvd[8]; 696 }; 697 698 struct mlx5_enable_hca_mbox_out { 699 struct mlx5_outbox_hdr hdr; 700 u8 rsvd[8]; 701 }; 702 703 struct mlx5_disable_hca_mbox_in { 704 struct mlx5_inbox_hdr hdr; 705 u8 rsvd[8]; 706 }; 707 708 struct mlx5_disable_hca_mbox_out { 709 struct mlx5_outbox_hdr hdr; 710 u8 rsvd[8]; 711 }; 712 713 struct mlx5_eq_context { 714 u8 status; 715 u8 ec_oi; 716 u8 st; 717 u8 rsvd2[7]; 718 __be16 page_pffset; 719 __be32 log_sz_usr_page; 720 u8 rsvd3[7]; 721 u8 intr; 722 u8 log_page_size; 723 u8 rsvd4[15]; 724 __be32 consumer_counter; 725 __be32 produser_counter; 726 u8 rsvd5[16]; 727 }; 728 729 struct mlx5_create_eq_mbox_in { 730 struct mlx5_inbox_hdr hdr; 731 u8 rsvd0[3]; 732 u8 input_eqn; 733 u8 rsvd1[4]; 734 struct mlx5_eq_context ctx; 735 u8 rsvd2[8]; 736 __be64 events_mask; 737 u8 rsvd3[176]; 738 __be64 pas[0]; 739 }; 740 741 struct mlx5_create_eq_mbox_out { 742 struct mlx5_outbox_hdr hdr; 743 u8 rsvd0[3]; 744 u8 eq_number; 745 u8 rsvd1[4]; 746 }; 747 748 struct mlx5_destroy_eq_mbox_in { 749 struct mlx5_inbox_hdr hdr; 750 u8 rsvd0[3]; 751 u8 eqn; 752 u8 rsvd1[4]; 753 }; 754 755 struct mlx5_destroy_eq_mbox_out { 756 struct mlx5_outbox_hdr hdr; 757 u8 rsvd[8]; 758 }; 759 760 struct mlx5_map_eq_mbox_in { 761 struct mlx5_inbox_hdr hdr; 762 __be64 mask; 763 u8 mu; 764 u8 rsvd0[2]; 765 u8 eqn; 766 u8 rsvd1[24]; 767 }; 768 769 struct mlx5_map_eq_mbox_out { 770 struct mlx5_outbox_hdr hdr; 771 u8 rsvd[8]; 772 }; 773 774 struct mlx5_query_eq_mbox_in { 775 struct mlx5_inbox_hdr hdr; 776 u8 rsvd0[3]; 777 u8 eqn; 778 u8 rsvd1[4]; 779 }; 780 781 struct mlx5_query_eq_mbox_out { 782 struct mlx5_outbox_hdr hdr; 783 u8 rsvd[8]; 784 struct mlx5_eq_context ctx; 785 }; 786 787 struct mlx5_mkey_seg { 788 /* This is a two bit field occupying bits 31-30. 789 * bit 31 is always 0, 790 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 791 */ 792 u8 status; 793 u8 pcie_control; 794 u8 flags; 795 u8 version; 796 __be32 qpn_mkey7_0; 797 u8 rsvd1[4]; 798 __be32 flags_pd; 799 __be64 start_addr; 800 __be64 len; 801 __be32 bsfs_octo_size; 802 u8 rsvd2[16]; 803 __be32 xlt_oct_size; 804 u8 rsvd3[3]; 805 u8 log2_page_size; 806 u8 rsvd4[4]; 807 }; 808 809 struct mlx5_query_special_ctxs_mbox_in { 810 struct mlx5_inbox_hdr hdr; 811 u8 rsvd[8]; 812 }; 813 814 struct mlx5_query_special_ctxs_mbox_out { 815 struct mlx5_outbox_hdr hdr; 816 __be32 dump_fill_mkey; 817 __be32 reserved_lkey; 818 }; 819 820 struct mlx5_create_mkey_mbox_in { 821 struct mlx5_inbox_hdr hdr; 822 __be32 input_mkey_index; 823 u8 rsvd0[4]; 824 struct mlx5_mkey_seg seg; 825 u8 rsvd1[16]; 826 __be32 xlat_oct_act_size; 827 __be32 bsf_coto_act_size; 828 u8 rsvd2[168]; 829 __be64 pas[0]; 830 }; 831 832 struct mlx5_create_mkey_mbox_out { 833 struct mlx5_outbox_hdr hdr; 834 __be32 mkey; 835 u8 rsvd[4]; 836 }; 837 838 struct mlx5_destroy_mkey_mbox_in { 839 struct mlx5_inbox_hdr hdr; 840 __be32 mkey; 841 u8 rsvd[4]; 842 }; 843 844 struct mlx5_destroy_mkey_mbox_out { 845 struct mlx5_outbox_hdr hdr; 846 u8 rsvd[8]; 847 }; 848 849 struct mlx5_query_mkey_mbox_in { 850 struct mlx5_inbox_hdr hdr; 851 __be32 mkey; 852 }; 853 854 struct mlx5_query_mkey_mbox_out { 855 struct mlx5_outbox_hdr hdr; 856 __be64 pas[0]; 857 }; 858 859 struct mlx5_modify_mkey_mbox_in { 860 struct mlx5_inbox_hdr hdr; 861 __be32 mkey; 862 __be64 pas[0]; 863 }; 864 865 struct mlx5_modify_mkey_mbox_out { 866 struct mlx5_outbox_hdr hdr; 867 }; 868 869 struct mlx5_dump_mkey_mbox_in { 870 struct mlx5_inbox_hdr hdr; 871 }; 872 873 struct mlx5_dump_mkey_mbox_out { 874 struct mlx5_outbox_hdr hdr; 875 __be32 mkey; 876 }; 877 878 struct mlx5_mad_ifc_mbox_in { 879 struct mlx5_inbox_hdr hdr; 880 __be16 remote_lid; 881 u8 rsvd0; 882 u8 port; 883 u8 rsvd1[4]; 884 u8 data[256]; 885 }; 886 887 struct mlx5_mad_ifc_mbox_out { 888 struct mlx5_outbox_hdr hdr; 889 u8 rsvd[8]; 890 u8 data[256]; 891 }; 892 893 struct mlx5_access_reg_mbox_in { 894 struct mlx5_inbox_hdr hdr; 895 u8 rsvd0[2]; 896 __be16 register_id; 897 __be32 arg; 898 __be32 data[0]; 899 }; 900 901 struct mlx5_access_reg_mbox_out { 902 struct mlx5_outbox_hdr hdr; 903 u8 rsvd[8]; 904 __be32 data[0]; 905 }; 906 907 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 908 909 enum { 910 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 911 }; 912 913 #endif /* MLX5_DEVICE_H */ 914