1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 u32 _v = v; \ 75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ 83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ 84 MLX5_SET(typ, p, fld[idx], v); \ 85 } while (0) 86 87 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 92 << __mlx5_dw_bit_off(typ, fld))); \ 93 } while (0) 94 95 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 96 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 97 __mlx5_mask(typ, fld)) 98 99 #define MLX5_GET_PR(typ, p, fld) ({ \ 100 u32 ___t = MLX5_GET(typ, p, fld); \ 101 pr_debug(#fld " = 0x%x\n", ___t); \ 102 ___t; \ 103 }) 104 105 #define __MLX5_SET64(typ, p, fld, v) do { \ 106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 108 } while (0) 109 110 #define MLX5_SET64(typ, p, fld, v) do { \ 111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 112 __MLX5_SET64(typ, p, fld, v); \ 113 } while (0) 114 115 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 117 __MLX5_SET64(typ, p, fld[idx], v); \ 118 } while (0) 119 120 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 121 122 #define MLX5_GET64_PR(typ, p, fld) ({ \ 123 u64 ___t = MLX5_GET64(typ, p, fld); \ 124 pr_debug(#fld " = 0x%llx\n", ___t); \ 125 ___t; \ 126 }) 127 128 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 129 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 130 __mlx5_mask16(typ, fld)) 131 132 #define MLX5_SET16(typ, p, fld, v) do { \ 133 u16 _v = v; \ 134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 138 << __mlx5_16_bit_off(typ, fld))); \ 139 } while (0) 140 141 /* Big endian getters */ 142 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 143 __mlx5_64_off(typ, fld))) 144 145 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 146 type_t tmp; \ 147 switch (sizeof(tmp)) { \ 148 case sizeof(u8): \ 149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 150 break; \ 151 case sizeof(u16): \ 152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 153 break; \ 154 case sizeof(u32): \ 155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 156 break; \ 157 case sizeof(u64): \ 158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 159 break; \ 160 } \ 161 tmp; \ 162 }) 163 164 enum mlx5_inline_modes { 165 MLX5_INLINE_MODE_NONE, 166 MLX5_INLINE_MODE_L2, 167 MLX5_INLINE_MODE_IP, 168 MLX5_INLINE_MODE_TCP_UDP, 169 }; 170 171 enum { 172 MLX5_MAX_COMMANDS = 32, 173 MLX5_CMD_DATA_BLOCK_SIZE = 512, 174 MLX5_PCI_CMD_XPORT = 7, 175 MLX5_MKEY_BSF_OCTO_SIZE = 4, 176 MLX5_MAX_PSVS = 4, 177 }; 178 179 enum { 180 MLX5_EXTENDED_UD_AV = 0x80000000, 181 }; 182 183 enum { 184 MLX5_CQ_STATE_ARMED = 9, 185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 186 MLX5_CQ_STATE_FIRED = 0xa, 187 }; 188 189 enum { 190 MLX5_STAT_RATE_OFFSET = 5, 191 }; 192 193 enum { 194 MLX5_INLINE_SEG = 0x80000000, 195 }; 196 197 enum { 198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 199 }; 200 201 enum { 202 MLX5_MIN_PKEY_TABLE_SIZE = 128, 203 MLX5_MAX_LOG_PKEY_TABLE = 5, 204 }; 205 206 enum { 207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 208 }; 209 210 enum { 211 MLX5_PFAULT_SUBTYPE_WQE = 0, 212 MLX5_PFAULT_SUBTYPE_RDMA = 1, 213 }; 214 215 enum wqe_page_fault_type { 216 MLX5_WQE_PF_TYPE_RMP = 0, 217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, 218 MLX5_WQE_PF_TYPE_RESP = 2, 219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, 220 }; 221 222 enum { 223 MLX5_PERM_LOCAL_READ = 1 << 2, 224 MLX5_PERM_LOCAL_WRITE = 1 << 3, 225 MLX5_PERM_REMOTE_READ = 1 << 4, 226 MLX5_PERM_REMOTE_WRITE = 1 << 5, 227 MLX5_PERM_ATOMIC = 1 << 6, 228 MLX5_PERM_UMR_EN = 1 << 7, 229 }; 230 231 enum { 232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 237 }; 238 239 enum { 240 MLX5_EN_RD = (u64)1, 241 MLX5_EN_WR = (u64)2 242 }; 243 244 enum { 245 MLX5_ADAPTER_PAGE_SHIFT = 12, 246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 247 }; 248 249 enum { 250 MLX5_BFREGS_PER_UAR = 4, 251 MLX5_MAX_UARS = 1 << 8, 252 MLX5_NON_FP_BFREGS_PER_UAR = 2, 253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 254 MLX5_NON_FP_BFREGS_PER_UAR, 255 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 256 MLX5_NON_FP_BFREGS_PER_UAR, 257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 259 MLX5_MIN_DYN_BFREGS = 512, 260 MLX5_MAX_DYN_BFREGS = 1024, 261 }; 262 263 enum { 264 MLX5_MKEY_MASK_LEN = 1ull << 0, 265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 267 MLX5_MKEY_MASK_PD = 1ull << 7, 268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 271 MLX5_MKEY_MASK_KEY = 1ull << 13, 272 MLX5_MKEY_MASK_QPN = 1ull << 14, 273 MLX5_MKEY_MASK_LR = 1ull << 17, 274 MLX5_MKEY_MASK_LW = 1ull << 18, 275 MLX5_MKEY_MASK_RR = 1ull << 19, 276 MLX5_MKEY_MASK_RW = 1ull << 20, 277 MLX5_MKEY_MASK_A = 1ull << 21, 278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 279 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, 280 MLX5_MKEY_MASK_FREE = 1ull << 29, 281 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, 282 }; 283 284 enum { 285 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 286 287 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 288 MLX5_UMR_CHECK_FREE = (2 << 5), 289 290 MLX5_UMR_INLINE = (1 << 7), 291 }; 292 293 #define MLX5_UMR_MTT_ALIGNMENT 0x40 294 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 295 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 296 297 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 298 299 enum { 300 MLX5_EVENT_QUEUE_TYPE_QP = 0, 301 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 302 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 303 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 304 }; 305 306 /* mlx5 components can subscribe to any one of these events via 307 * mlx5_eq_notifier_register API. 308 */ 309 enum mlx5_event { 310 /* Special value to subscribe to any event */ 311 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 312 /* HW events enum start: comp events are not subscribable */ 313 MLX5_EVENT_TYPE_COMP = 0x0, 314 /* HW Async events enum start: subscribable events */ 315 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 316 MLX5_EVENT_TYPE_COMM_EST = 0x02, 317 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 318 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 319 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 320 321 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 322 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 323 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 324 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 325 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 326 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 327 328 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 329 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 330 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 331 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 332 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 333 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 334 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 335 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, 336 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, 337 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 338 339 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 340 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 341 342 MLX5_EVENT_TYPE_CMD = 0x0a, 343 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 344 345 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 346 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 347 348 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, 349 350 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 351 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 352 353 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 354 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 355 356 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, 357 358 MLX5_EVENT_TYPE_MAX = 0x100, 359 }; 360 361 enum { 362 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, 363 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, 364 }; 365 366 enum { 367 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 368 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 369 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, 370 }; 371 372 enum { 373 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 374 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 375 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 376 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 377 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 378 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 379 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 380 }; 381 382 enum { 383 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 384 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 385 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 386 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 387 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 388 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 389 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 390 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 391 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 392 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 393 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 394 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 395 }; 396 397 enum { 398 MLX5_ROCE_VERSION_1 = 0, 399 MLX5_ROCE_VERSION_2 = 2, 400 }; 401 402 enum { 403 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 404 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 405 }; 406 407 enum { 408 MLX5_ROCE_L3_TYPE_IPV4 = 0, 409 MLX5_ROCE_L3_TYPE_IPV6 = 1, 410 }; 411 412 enum { 413 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 414 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 415 }; 416 417 enum { 418 MLX5_OPCODE_NOP = 0x00, 419 MLX5_OPCODE_SEND_INVAL = 0x01, 420 MLX5_OPCODE_RDMA_WRITE = 0x08, 421 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 422 MLX5_OPCODE_SEND = 0x0a, 423 MLX5_OPCODE_SEND_IMM = 0x0b, 424 MLX5_OPCODE_LSO = 0x0e, 425 MLX5_OPCODE_RDMA_READ = 0x10, 426 MLX5_OPCODE_ATOMIC_CS = 0x11, 427 MLX5_OPCODE_ATOMIC_FA = 0x12, 428 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 429 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 430 MLX5_OPCODE_BIND_MW = 0x18, 431 MLX5_OPCODE_CONFIG_CMD = 0x1f, 432 MLX5_OPCODE_ENHANCED_MPSW = 0x29, 433 434 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 435 MLX5_RECV_OPCODE_SEND = 0x01, 436 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 437 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 438 439 MLX5_CQE_OPCODE_ERROR = 0x1e, 440 MLX5_CQE_OPCODE_RESIZE = 0x16, 441 442 MLX5_OPCODE_SET_PSV = 0x20, 443 MLX5_OPCODE_GET_PSV = 0x21, 444 MLX5_OPCODE_CHECK_PSV = 0x22, 445 MLX5_OPCODE_DUMP = 0x23, 446 MLX5_OPCODE_RGET_PSV = 0x26, 447 MLX5_OPCODE_RCHECK_PSV = 0x27, 448 449 MLX5_OPCODE_UMR = 0x25, 450 451 }; 452 453 enum { 454 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, 455 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, 456 }; 457 458 enum { 459 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, 460 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, 461 }; 462 463 struct mlx5_wqe_tls_static_params_seg { 464 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; 465 }; 466 467 struct mlx5_wqe_tls_progress_params_seg { 468 __be32 tis_tir_num; 469 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; 470 }; 471 472 enum { 473 MLX5_SET_PORT_RESET_QKEY = 0, 474 MLX5_SET_PORT_GUID0 = 16, 475 MLX5_SET_PORT_NODE_GUID = 17, 476 MLX5_SET_PORT_SYS_GUID = 18, 477 MLX5_SET_PORT_GID_TABLE = 19, 478 MLX5_SET_PORT_PKEY_TABLE = 20, 479 }; 480 481 enum { 482 MLX5_BW_NO_LIMIT = 0, 483 MLX5_100_MBPS_UNIT = 3, 484 MLX5_GBPS_UNIT = 4, 485 }; 486 487 enum { 488 MLX5_MAX_PAGE_SHIFT = 31 489 }; 490 491 enum { 492 MLX5_CAP_OFF_CMDIF_CSUM = 46, 493 }; 494 495 enum { 496 /* 497 * Max wqe size for rdma read is 512 bytes, so this 498 * limits our max_sge_rd as the wqe needs to fit: 499 * - ctrl segment (16 bytes) 500 * - rdma segment (16 bytes) 501 * - scatter elements (16 bytes each) 502 */ 503 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 504 }; 505 506 enum mlx5_odp_transport_cap_bits { 507 MLX5_ODP_SUPPORT_SEND = 1 << 31, 508 MLX5_ODP_SUPPORT_RECV = 1 << 30, 509 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 510 MLX5_ODP_SUPPORT_READ = 1 << 28, 511 }; 512 513 struct mlx5_odp_caps { 514 char reserved[0x10]; 515 struct { 516 __be32 rc_odp_caps; 517 __be32 uc_odp_caps; 518 __be32 ud_odp_caps; 519 } per_transport_caps; 520 char reserved2[0xe4]; 521 }; 522 523 struct mlx5_cmd_layout { 524 u8 type; 525 u8 rsvd0[3]; 526 __be32 inlen; 527 __be64 in_ptr; 528 __be32 in[4]; 529 __be32 out[4]; 530 __be64 out_ptr; 531 __be32 outlen; 532 u8 token; 533 u8 sig; 534 u8 rsvd1; 535 u8 status_own; 536 }; 537 538 enum mlx5_fatal_assert_bit_offsets { 539 MLX5_RFR_OFFSET = 31, 540 }; 541 542 struct health_buffer { 543 __be32 assert_var[5]; 544 __be32 rsvd0[3]; 545 __be32 assert_exit_ptr; 546 __be32 assert_callra; 547 __be32 rsvd1[2]; 548 __be32 fw_ver; 549 __be32 hw_id; 550 __be32 rfr; 551 u8 irisc_index; 552 u8 synd; 553 __be16 ext_synd; 554 }; 555 556 enum mlx5_initializing_bit_offsets { 557 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 558 }; 559 560 enum mlx5_cmd_addr_l_sz_offset { 561 MLX5_NIC_IFC_OFFSET = 8, 562 }; 563 564 struct mlx5_init_seg { 565 __be32 fw_rev; 566 __be32 cmdif_rev_fw_sub; 567 __be32 rsvd0[2]; 568 __be32 cmdq_addr_h; 569 __be32 cmdq_addr_l_sz; 570 __be32 cmd_dbell; 571 __be32 rsvd1[120]; 572 __be32 initializing; 573 struct health_buffer health; 574 __be32 rsvd2[880]; 575 __be32 internal_timer_h; 576 __be32 internal_timer_l; 577 __be32 rsvd3[2]; 578 __be32 health_counter; 579 __be32 rsvd4[1019]; 580 __be64 ieee1588_clk; 581 __be32 ieee1588_clk_type; 582 __be32 clr_intx; 583 }; 584 585 struct mlx5_eqe_comp { 586 __be32 reserved[6]; 587 __be32 cqn; 588 }; 589 590 struct mlx5_eqe_qp_srq { 591 __be32 reserved1[5]; 592 u8 type; 593 u8 reserved2[3]; 594 __be32 qp_srq_n; 595 }; 596 597 struct mlx5_eqe_cq_err { 598 __be32 cqn; 599 u8 reserved1[7]; 600 u8 syndrome; 601 }; 602 603 struct mlx5_eqe_xrq_err { 604 __be32 reserved1[5]; 605 __be32 type_xrqn; 606 __be32 reserved2; 607 }; 608 609 struct mlx5_eqe_port_state { 610 u8 reserved0[8]; 611 u8 port; 612 }; 613 614 struct mlx5_eqe_gpio { 615 __be32 reserved0[2]; 616 __be64 gpio_event; 617 }; 618 619 struct mlx5_eqe_congestion { 620 u8 type; 621 u8 rsvd0; 622 u8 congestion_level; 623 }; 624 625 struct mlx5_eqe_stall_vl { 626 u8 rsvd0[3]; 627 u8 port_vl; 628 }; 629 630 struct mlx5_eqe_cmd { 631 __be32 vector; 632 __be32 rsvd[6]; 633 }; 634 635 struct mlx5_eqe_page_req { 636 __be16 ec_function; 637 __be16 func_id; 638 __be32 num_pages; 639 __be32 rsvd1[5]; 640 }; 641 642 struct mlx5_eqe_page_fault { 643 __be32 bytes_committed; 644 union { 645 struct { 646 u16 reserved1; 647 __be16 wqe_index; 648 u16 reserved2; 649 __be16 packet_length; 650 __be32 token; 651 u8 reserved4[8]; 652 __be32 pftype_wq; 653 } __packed wqe; 654 struct { 655 __be32 r_key; 656 u16 reserved1; 657 __be16 packet_length; 658 __be32 rdma_op_len; 659 __be64 rdma_va; 660 __be32 pftype_token; 661 } __packed rdma; 662 } __packed; 663 } __packed; 664 665 struct mlx5_eqe_vport_change { 666 u8 rsvd0[2]; 667 __be16 vport_num; 668 __be32 rsvd1[6]; 669 } __packed; 670 671 struct mlx5_eqe_port_module { 672 u8 reserved_at_0[1]; 673 u8 module; 674 u8 reserved_at_2[1]; 675 u8 module_status; 676 u8 reserved_at_4[2]; 677 u8 error_type; 678 } __packed; 679 680 struct mlx5_eqe_pps { 681 u8 rsvd0[3]; 682 u8 pin; 683 u8 rsvd1[4]; 684 union { 685 struct { 686 __be32 time_sec; 687 __be32 time_nsec; 688 }; 689 struct { 690 __be64 time_stamp; 691 }; 692 }; 693 u8 rsvd2[12]; 694 } __packed; 695 696 struct mlx5_eqe_dct { 697 __be32 reserved[6]; 698 __be32 dctn; 699 }; 700 701 struct mlx5_eqe_temp_warning { 702 __be64 sensor_warning_msb; 703 __be64 sensor_warning_lsb; 704 } __packed; 705 706 #define SYNC_RST_STATE_MASK 0xf 707 708 enum sync_rst_state_type { 709 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, 710 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, 711 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, 712 }; 713 714 struct mlx5_eqe_sync_fw_update { 715 u8 reserved_at_0[3]; 716 u8 sync_rst_state; 717 }; 718 719 union ev_data { 720 __be32 raw[7]; 721 struct mlx5_eqe_cmd cmd; 722 struct mlx5_eqe_comp comp; 723 struct mlx5_eqe_qp_srq qp_srq; 724 struct mlx5_eqe_cq_err cq_err; 725 struct mlx5_eqe_port_state port; 726 struct mlx5_eqe_gpio gpio; 727 struct mlx5_eqe_congestion cong; 728 struct mlx5_eqe_stall_vl stall_vl; 729 struct mlx5_eqe_page_req req_pages; 730 struct mlx5_eqe_page_fault page_fault; 731 struct mlx5_eqe_vport_change vport_change; 732 struct mlx5_eqe_port_module port_module; 733 struct mlx5_eqe_pps pps; 734 struct mlx5_eqe_dct dct; 735 struct mlx5_eqe_temp_warning temp_warning; 736 struct mlx5_eqe_xrq_err xrq_err; 737 struct mlx5_eqe_sync_fw_update sync_fw_update; 738 } __packed; 739 740 struct mlx5_eqe { 741 u8 rsvd0; 742 u8 type; 743 u8 rsvd1; 744 u8 sub_type; 745 __be32 rsvd2[7]; 746 union ev_data data; 747 __be16 rsvd3; 748 u8 signature; 749 u8 owner; 750 } __packed; 751 752 struct mlx5_cmd_prot_block { 753 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 754 u8 rsvd0[48]; 755 __be64 next; 756 __be32 block_num; 757 u8 rsvd1; 758 u8 token; 759 u8 ctrl_sig; 760 u8 sig; 761 }; 762 763 enum { 764 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 765 }; 766 767 struct mlx5_err_cqe { 768 u8 rsvd0[32]; 769 __be32 srqn; 770 u8 rsvd1[18]; 771 u8 vendor_err_synd; 772 u8 syndrome; 773 __be32 s_wqe_opcode_qpn; 774 __be16 wqe_counter; 775 u8 signature; 776 u8 op_own; 777 }; 778 779 struct mlx5_cqe64 { 780 u8 tls_outer_l3_tunneled; 781 u8 rsvd0; 782 __be16 wqe_id; 783 u8 lro_tcppsh_abort_dupack; 784 u8 lro_min_ttl; 785 __be16 lro_tcp_win; 786 __be32 lro_ack_seq_num; 787 __be32 rss_hash_result; 788 u8 rss_hash_type; 789 u8 ml_path; 790 u8 rsvd20[2]; 791 __be16 check_sum; 792 __be16 slid; 793 __be32 flags_rqpn; 794 u8 hds_ip_ext; 795 u8 l4_l3_hdr_type; 796 __be16 vlan_info; 797 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 798 union { 799 __be32 immediate; 800 __be32 inval_rkey; 801 __be32 pkey; 802 __be32 ft_metadata; 803 }; 804 u8 rsvd40[4]; 805 __be32 byte_cnt; 806 __be32 timestamp_h; 807 __be32 timestamp_l; 808 __be32 sop_drop_qpn; 809 __be16 wqe_counter; 810 u8 signature; 811 u8 op_own; 812 }; 813 814 struct mlx5_mini_cqe8 { 815 union { 816 __be32 rx_hash_result; 817 struct { 818 __be16 checksum; 819 __be16 stridx; 820 }; 821 struct { 822 __be16 wqe_counter; 823 u8 s_wqe_opcode; 824 u8 reserved; 825 } s_wqe_info; 826 }; 827 __be32 byte_cnt; 828 }; 829 830 enum { 831 MLX5_NO_INLINE_DATA, 832 MLX5_INLINE_DATA32_SEG, 833 MLX5_INLINE_DATA64_SEG, 834 MLX5_COMPRESSED, 835 }; 836 837 enum { 838 MLX5_CQE_FORMAT_CSUM = 0x1, 839 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3, 840 }; 841 842 #define MLX5_MINI_CQE_ARRAY_SIZE 8 843 844 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 845 { 846 return (cqe->op_own >> 2) & 0x3; 847 } 848 849 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 850 { 851 return cqe->op_own >> 4; 852 } 853 854 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 855 { 856 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 857 } 858 859 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 860 { 861 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 862 } 863 864 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 865 { 866 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 867 } 868 869 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 870 { 871 return cqe->tls_outer_l3_tunneled & 0x1; 872 } 873 874 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) 875 { 876 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; 877 } 878 879 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 880 { 881 return cqe->l4_l3_hdr_type & 0x1; 882 } 883 884 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 885 { 886 u32 hi, lo; 887 888 hi = be32_to_cpu(cqe->timestamp_h); 889 lo = be32_to_cpu(cqe->timestamp_l); 890 891 return (u64)lo | ((u64)hi << 32); 892 } 893 894 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9) 895 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6) 896 897 struct mpwrq_cqe_bc { 898 __be16 filler_consumed_strides; 899 __be16 byte_cnt; 900 }; 901 902 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 903 { 904 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 905 906 return be16_to_cpu(bc->byte_cnt); 907 } 908 909 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 910 { 911 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 912 } 913 914 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 915 { 916 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 917 918 return mpwrq_get_cqe_bc_consumed_strides(bc); 919 } 920 921 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 922 { 923 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 924 925 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 926 } 927 928 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 929 { 930 return be16_to_cpu(cqe->wqe_counter); 931 } 932 933 enum { 934 CQE_L4_HDR_TYPE_NONE = 0x0, 935 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 936 CQE_L4_HDR_TYPE_UDP = 0x2, 937 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 938 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 939 }; 940 941 enum { 942 CQE_RSS_HTYPE_IP = 0x3 << 2, 943 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 944 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 945 */ 946 CQE_RSS_HTYPE_L4 = 0x3 << 6, 947 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 948 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 949 */ 950 }; 951 952 enum { 953 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 954 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 955 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 956 }; 957 958 enum { 959 CQE_L2_OK = 1 << 0, 960 CQE_L3_OK = 1 << 1, 961 CQE_L4_OK = 1 << 2, 962 }; 963 964 enum { 965 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, 966 CQE_TLS_OFFLOAD_DECRYPTED = 0x1, 967 CQE_TLS_OFFLOAD_RESYNC = 0x2, 968 CQE_TLS_OFFLOAD_ERROR = 0x3, 969 }; 970 971 struct mlx5_sig_err_cqe { 972 u8 rsvd0[16]; 973 __be32 expected_trans_sig; 974 __be32 actual_trans_sig; 975 __be32 expected_reftag; 976 __be32 actual_reftag; 977 __be16 syndrome; 978 u8 rsvd22[2]; 979 __be32 mkey; 980 __be64 err_offset; 981 u8 rsvd30[8]; 982 __be32 qpn; 983 u8 rsvd38[2]; 984 u8 signature; 985 u8 op_own; 986 }; 987 988 struct mlx5_wqe_srq_next_seg { 989 u8 rsvd0[2]; 990 __be16 next_wqe_index; 991 u8 signature; 992 u8 rsvd1[11]; 993 }; 994 995 union mlx5_ext_cqe { 996 struct ib_grh grh; 997 u8 inl[64]; 998 }; 999 1000 struct mlx5_cqe128 { 1001 union mlx5_ext_cqe inl_grh; 1002 struct mlx5_cqe64 cqe64; 1003 }; 1004 1005 enum { 1006 MLX5_MKEY_STATUS_FREE = 1 << 6, 1007 }; 1008 1009 enum { 1010 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 1011 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 1012 MLX5_MKEY_BSF_EN = 1 << 30, 1013 }; 1014 1015 struct mlx5_mkey_seg { 1016 /* This is a two bit field occupying bits 31-30. 1017 * bit 31 is always 0, 1018 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 1019 */ 1020 u8 status; 1021 u8 pcie_control; 1022 u8 flags; 1023 u8 version; 1024 __be32 qpn_mkey7_0; 1025 u8 rsvd1[4]; 1026 __be32 flags_pd; 1027 __be64 start_addr; 1028 __be64 len; 1029 __be32 bsfs_octo_size; 1030 u8 rsvd2[16]; 1031 __be32 xlt_oct_size; 1032 u8 rsvd3[3]; 1033 u8 log2_page_size; 1034 u8 rsvd4[4]; 1035 }; 1036 1037 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1038 1039 enum { 1040 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1041 }; 1042 1043 enum { 1044 VPORT_STATE_DOWN = 0x0, 1045 VPORT_STATE_UP = 0x1, 1046 }; 1047 1048 enum { 1049 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, 1050 MLX5_VPORT_ADMIN_STATE_UP = 0x1, 1051 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, 1052 }; 1053 1054 enum { 1055 MLX5_L3_PROT_TYPE_IPV4 = 0, 1056 MLX5_L3_PROT_TYPE_IPV6 = 1, 1057 }; 1058 1059 enum { 1060 MLX5_L4_PROT_TYPE_TCP = 0, 1061 MLX5_L4_PROT_TYPE_UDP = 1, 1062 }; 1063 1064 enum { 1065 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1066 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1067 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1068 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1069 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1070 }; 1071 1072 enum { 1073 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1074 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1075 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1076 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 1077 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, 1078 }; 1079 1080 enum { 1081 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1082 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1083 }; 1084 1085 enum { 1086 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1087 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1088 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1089 }; 1090 1091 enum mlx5_list_type { 1092 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1093 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1094 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1095 }; 1096 1097 enum { 1098 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1099 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1100 }; 1101 1102 enum mlx5_wol_mode { 1103 MLX5_WOL_DISABLE = 0, 1104 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1105 MLX5_WOL_MAGIC = 1 << 2, 1106 MLX5_WOL_ARP = 1 << 3, 1107 MLX5_WOL_BROADCAST = 1 << 4, 1108 MLX5_WOL_MULTICAST = 1 << 5, 1109 MLX5_WOL_UNICAST = 1 << 6, 1110 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1111 }; 1112 1113 enum mlx5_mpls_supported_fields { 1114 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, 1115 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, 1116 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, 1117 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 1118 }; 1119 1120 enum mlx5_flex_parser_protos { 1121 MLX5_FLEX_PROTO_GENEVE = 1 << 3, 1122 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, 1123 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, 1124 }; 1125 1126 /* MLX5 DEV CAPs */ 1127 1128 /* TODO: EAT.ME */ 1129 enum mlx5_cap_mode { 1130 HCA_CAP_OPMOD_GET_MAX = 0, 1131 HCA_CAP_OPMOD_GET_CUR = 1, 1132 }; 1133 1134 enum mlx5_cap_type { 1135 MLX5_CAP_GENERAL = 0, 1136 MLX5_CAP_ETHERNET_OFFLOADS, 1137 MLX5_CAP_ODP, 1138 MLX5_CAP_ATOMIC, 1139 MLX5_CAP_ROCE, 1140 MLX5_CAP_IPOIB_OFFLOADS, 1141 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1142 MLX5_CAP_FLOW_TABLE, 1143 MLX5_CAP_ESWITCH_FLOW_TABLE, 1144 MLX5_CAP_ESWITCH, 1145 MLX5_CAP_RESERVED, 1146 MLX5_CAP_VECTOR_CALC, 1147 MLX5_CAP_QOS, 1148 MLX5_CAP_DEBUG, 1149 MLX5_CAP_RESERVED_14, 1150 MLX5_CAP_DEV_MEM, 1151 MLX5_CAP_RESERVED_16, 1152 MLX5_CAP_TLS, 1153 MLX5_CAP_VDPA_EMULATION = 0x13, 1154 MLX5_CAP_DEV_EVENT = 0x14, 1155 MLX5_CAP_IPSEC, 1156 /* NUM OF CAP Types */ 1157 MLX5_CAP_NUM 1158 }; 1159 1160 enum mlx5_pcam_reg_groups { 1161 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1162 }; 1163 1164 enum mlx5_pcam_feature_groups { 1165 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1166 }; 1167 1168 enum mlx5_mcam_reg_groups { 1169 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1170 MLX5_MCAM_REGS_0x9080_0x90FF = 0x1, 1171 MLX5_MCAM_REGS_0x9100_0x917F = 0x2, 1172 MLX5_MCAM_REGS_NUM = 0x3, 1173 }; 1174 1175 enum mlx5_mcam_feature_groups { 1176 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1177 }; 1178 1179 enum mlx5_qcam_reg_groups { 1180 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1181 }; 1182 1183 enum mlx5_qcam_feature_groups { 1184 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1185 }; 1186 1187 /* GET Dev Caps macros */ 1188 #define MLX5_CAP_GEN(mdev, cap) \ 1189 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1190 1191 #define MLX5_CAP_GEN_64(mdev, cap) \ 1192 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1193 1194 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1195 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap) 1196 1197 #define MLX5_CAP_ETH(mdev, cap) \ 1198 MLX5_GET(per_protocol_networking_offload_caps,\ 1199 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1200 1201 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1202 MLX5_GET(per_protocol_networking_offload_caps,\ 1203 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1204 1205 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ 1206 MLX5_GET(per_protocol_networking_offload_caps,\ 1207 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap) 1208 1209 #define MLX5_CAP_ROCE(mdev, cap) \ 1210 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap) 1211 1212 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1213 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap) 1214 1215 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1216 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap) 1217 1218 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1219 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap) 1220 1221 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1222 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1223 1224 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ 1225 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1226 1227 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1228 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap) 1229 1230 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1231 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1232 1233 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1234 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1235 1236 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1237 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1238 1239 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ 1240 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap) 1241 1242 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1243 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1244 1245 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1246 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1247 1248 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1249 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1250 1251 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1252 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1253 1254 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1255 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1256 1257 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ 1258 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap) 1259 1260 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ 1261 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) 1262 1263 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \ 1264 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap) 1265 1266 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1267 MLX5_GET(flow_table_eswitch_cap, \ 1268 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1269 1270 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1271 MLX5_GET(flow_table_eswitch_cap, \ 1272 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1273 1274 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1275 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1276 1277 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1278 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1279 1280 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1281 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1282 1283 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1284 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1285 1286 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1287 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1288 1289 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1290 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1291 1292 #define MLX5_CAP_ESW(mdev, cap) \ 1293 MLX5_GET(e_switch_cap, \ 1294 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap) 1295 1296 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ 1297 MLX5_GET64(flow_table_eswitch_cap, \ 1298 (mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1299 1300 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1301 MLX5_GET(e_switch_cap, \ 1302 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap) 1303 1304 #define MLX5_CAP_ODP(mdev, cap)\ 1305 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap) 1306 1307 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1308 MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap) 1309 1310 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1311 MLX5_GET(vector_calc_cap, \ 1312 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap) 1313 1314 #define MLX5_CAP_QOS(mdev, cap)\ 1315 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) 1316 1317 #define MLX5_CAP_DEBUG(mdev, cap)\ 1318 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap) 1319 1320 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1321 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1322 1323 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1324 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1325 1326 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1327 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ 1328 mng_access_reg_cap_mask.access_regs.reg) 1329 1330 #define MLX5_CAP_MCAM_REG1(mdev, reg) \ 1331 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \ 1332 mng_access_reg_cap_mask.access_regs1.reg) 1333 1334 #define MLX5_CAP_MCAM_REG2(mdev, reg) \ 1335 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ 1336 mng_access_reg_cap_mask.access_regs2.reg) 1337 1338 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1339 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1340 1341 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1342 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1343 1344 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1345 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1346 1347 #define MLX5_CAP_FPGA(mdev, cap) \ 1348 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1349 1350 #define MLX5_CAP64_FPGA(mdev, cap) \ 1351 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1352 1353 #define MLX5_CAP_DEV_MEM(mdev, cap)\ 1354 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap) 1355 1356 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ 1357 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap) 1358 1359 #define MLX5_CAP_TLS(mdev, cap) \ 1360 MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap) 1361 1362 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1363 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap) 1364 1365 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ 1366 MLX5_GET(virtio_emulation_cap, \ 1367 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap) 1368 1369 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ 1370 MLX5_GET64(virtio_emulation_cap, \ 1371 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap) 1372 1373 #define MLX5_CAP_IPSEC(mdev, cap)\ 1374 MLX5_GET(ipsec_cap, (mdev)->caps.hca_cur[MLX5_CAP_IPSEC], cap) 1375 1376 enum { 1377 MLX5_CMD_STAT_OK = 0x0, 1378 MLX5_CMD_STAT_INT_ERR = 0x1, 1379 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1380 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1381 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1382 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1383 MLX5_CMD_STAT_RES_BUSY = 0x6, 1384 MLX5_CMD_STAT_LIM_ERR = 0x8, 1385 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1386 MLX5_CMD_STAT_IX_ERR = 0xa, 1387 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1388 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1389 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1390 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1391 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1392 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1393 }; 1394 1395 enum { 1396 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1397 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1398 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1399 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1400 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1401 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1402 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1403 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1404 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, 1405 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1406 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1407 }; 1408 1409 enum { 1410 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1411 }; 1412 1413 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1414 { 1415 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1416 return 0; 1417 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1418 } 1419 1420 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 1421 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 1422 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1423 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1424 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1425 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1426 1427 #endif /* MLX5_DEVICE_H */ 1428