1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 #include <linux/bitfield.h> 40 41 #if defined(__LITTLE_ENDIAN) 42 #define MLX5_SET_HOST_ENDIANNESS 0 43 #elif defined(__BIG_ENDIAN) 44 #define MLX5_SET_HOST_ENDIANNESS 0x80 45 #else 46 #error Host endianness not defined 47 #endif 48 49 /* helper macros */ 50 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 51 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 52 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) 53 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 54 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 55 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 56 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 57 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 58 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 59 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 60 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 61 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 62 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 63 64 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 65 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 66 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 67 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 68 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 69 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 70 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 71 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) 72 73 /* insert a value to a struct */ 74 #define MLX5_SET(typ, p, fld, v) do { \ 75 u32 _v = v; \ 76 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 77 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 78 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 79 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ 80 << __mlx5_dw_bit_off(typ, fld))); \ 81 } while (0) 82 83 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ 84 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ 85 MLX5_SET(typ, p, fld[idx], v); \ 86 } while (0) 87 88 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 89 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 90 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 91 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 92 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 93 << __mlx5_dw_bit_off(typ, fld))); \ 94 } while (0) 95 96 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 97 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 98 __mlx5_mask(typ, fld)) 99 100 #define MLX5_GET_PR(typ, p, fld) ({ \ 101 u32 ___t = MLX5_GET(typ, p, fld); \ 102 pr_debug(#fld " = 0x%x\n", ___t); \ 103 ___t; \ 104 }) 105 106 #define __MLX5_SET64(typ, p, fld, v) do { \ 107 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 108 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 109 } while (0) 110 111 #define MLX5_SET64(typ, p, fld, v) do { \ 112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 113 __MLX5_SET64(typ, p, fld, v); \ 114 } while (0) 115 116 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 117 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 118 __MLX5_SET64(typ, p, fld[idx], v); \ 119 } while (0) 120 121 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 122 123 #define MLX5_GET64_PR(typ, p, fld) ({ \ 124 u64 ___t = MLX5_GET64(typ, p, fld); \ 125 pr_debug(#fld " = 0x%llx\n", ___t); \ 126 ___t; \ 127 }) 128 129 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 130 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 131 __mlx5_mask16(typ, fld)) 132 133 #define MLX5_SET16(typ, p, fld, v) do { \ 134 u16 _v = v; \ 135 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 136 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 137 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 138 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 139 << __mlx5_16_bit_off(typ, fld))); \ 140 } while (0) 141 142 /* Big endian getters */ 143 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 144 __mlx5_64_off(typ, fld))) 145 146 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 147 type_t tmp; \ 148 switch (sizeof(tmp)) { \ 149 case sizeof(u8): \ 150 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 151 break; \ 152 case sizeof(u16): \ 153 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 154 break; \ 155 case sizeof(u32): \ 156 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 157 break; \ 158 case sizeof(u64): \ 159 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 160 break; \ 161 } \ 162 tmp; \ 163 }) 164 165 enum mlx5_inline_modes { 166 MLX5_INLINE_MODE_NONE, 167 MLX5_INLINE_MODE_L2, 168 MLX5_INLINE_MODE_IP, 169 MLX5_INLINE_MODE_TCP_UDP, 170 }; 171 172 enum { 173 MLX5_MAX_COMMANDS = 32, 174 MLX5_CMD_DATA_BLOCK_SIZE = 512, 175 MLX5_PCI_CMD_XPORT = 7, 176 MLX5_MKEY_BSF_OCTO_SIZE = 4, 177 MLX5_MAX_PSVS = 4, 178 }; 179 180 enum { 181 MLX5_EXTENDED_UD_AV = 0x80000000, 182 }; 183 184 enum { 185 MLX5_CQ_STATE_ARMED = 9, 186 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 187 MLX5_CQ_STATE_FIRED = 0xa, 188 }; 189 190 enum { 191 MLX5_STAT_RATE_OFFSET = 5, 192 }; 193 194 enum { 195 MLX5_INLINE_SEG = 0x80000000, 196 }; 197 198 enum { 199 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 200 }; 201 202 enum { 203 MLX5_MIN_PKEY_TABLE_SIZE = 128, 204 MLX5_MAX_LOG_PKEY_TABLE = 5, 205 }; 206 207 enum { 208 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 209 }; 210 211 enum { 212 MLX5_PFAULT_SUBTYPE_WQE = 0, 213 MLX5_PFAULT_SUBTYPE_RDMA = 1, 214 }; 215 216 enum wqe_page_fault_type { 217 MLX5_WQE_PF_TYPE_RMP = 0, 218 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, 219 MLX5_WQE_PF_TYPE_RESP = 2, 220 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, 221 }; 222 223 enum { 224 MLX5_PERM_LOCAL_READ = 1 << 2, 225 MLX5_PERM_LOCAL_WRITE = 1 << 3, 226 MLX5_PERM_REMOTE_READ = 1 << 4, 227 MLX5_PERM_REMOTE_WRITE = 1 << 5, 228 MLX5_PERM_ATOMIC = 1 << 6, 229 MLX5_PERM_UMR_EN = 1 << 7, 230 }; 231 232 enum { 233 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 234 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 235 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 236 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 237 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 238 }; 239 240 enum { 241 MLX5_EN_RD = (u64)1, 242 MLX5_EN_WR = (u64)2 243 }; 244 245 enum { 246 MLX5_ADAPTER_PAGE_SHIFT = 12, 247 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 248 }; 249 250 enum { 251 MLX5_BFREGS_PER_UAR = 4, 252 MLX5_MAX_UARS = 1 << 8, 253 MLX5_NON_FP_BFREGS_PER_UAR = 2, 254 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 255 MLX5_NON_FP_BFREGS_PER_UAR, 256 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 257 MLX5_NON_FP_BFREGS_PER_UAR, 258 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 259 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 260 MLX5_MIN_DYN_BFREGS = 512, 261 MLX5_MAX_DYN_BFREGS = 1024, 262 }; 263 264 enum { 265 MLX5_MKEY_MASK_LEN = 1ull << 0, 266 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 267 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 268 MLX5_MKEY_MASK_PD = 1ull << 7, 269 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 270 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 271 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 272 MLX5_MKEY_MASK_KEY = 1ull << 13, 273 MLX5_MKEY_MASK_QPN = 1ull << 14, 274 MLX5_MKEY_MASK_LR = 1ull << 17, 275 MLX5_MKEY_MASK_LW = 1ull << 18, 276 MLX5_MKEY_MASK_RR = 1ull << 19, 277 MLX5_MKEY_MASK_RW = 1ull << 20, 278 MLX5_MKEY_MASK_A = 1ull << 21, 279 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 280 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, 281 MLX5_MKEY_MASK_FREE = 1ull << 29, 282 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, 283 }; 284 285 enum { 286 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 287 288 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 289 MLX5_UMR_CHECK_FREE = (2 << 5), 290 291 MLX5_UMR_INLINE = (1 << 7), 292 }; 293 294 #define MLX5_UMR_FLEX_ALIGNMENT 0x40 295 #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt)) 296 #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm)) 297 298 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 299 300 enum { 301 MLX5_EVENT_QUEUE_TYPE_QP = 0, 302 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 303 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 304 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 305 }; 306 307 /* mlx5 components can subscribe to any one of these events via 308 * mlx5_eq_notifier_register API. 309 */ 310 enum mlx5_event { 311 /* Special value to subscribe to any event */ 312 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 313 /* HW events enum start: comp events are not subscribable */ 314 MLX5_EVENT_TYPE_COMP = 0x0, 315 /* HW Async events enum start: subscribable events */ 316 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 317 MLX5_EVENT_TYPE_COMM_EST = 0x02, 318 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 319 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 320 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 321 322 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 323 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 324 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 325 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 326 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 327 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 328 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 329 330 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 331 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 332 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 333 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 334 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 335 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 336 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 337 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, 338 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, 339 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 340 341 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 342 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 343 344 MLX5_EVENT_TYPE_CMD = 0x0a, 345 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 346 347 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 348 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 349 350 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, 351 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf, 352 353 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 354 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 355 356 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 357 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 358 359 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, 360 361 MLX5_EVENT_TYPE_MAX = 0x100, 362 }; 363 364 enum mlx5_driver_event { 365 MLX5_DRIVER_EVENT_TYPE_TRAP = 0, 366 MLX5_DRIVER_EVENT_UPLINK_NETDEV, 367 MLX5_DRIVER_EVENT_MACSEC_SA_ADDED, 368 MLX5_DRIVER_EVENT_MACSEC_SA_DELETED, 369 MLX5_DRIVER_EVENT_SF_PEER_DEVLINK, 370 }; 371 372 enum { 373 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, 374 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, 375 MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2, 376 }; 377 378 enum { 379 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 380 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 381 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7, 382 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, 383 }; 384 385 enum { 386 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 387 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 388 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 389 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 390 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 391 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 392 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 393 }; 394 395 enum { 396 MLX5_ROCE_VERSION_1 = 0, 397 MLX5_ROCE_VERSION_2 = 2, 398 }; 399 400 enum { 401 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 402 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 403 }; 404 405 enum { 406 MLX5_ROCE_L3_TYPE_IPV4 = 0, 407 MLX5_ROCE_L3_TYPE_IPV6 = 1, 408 }; 409 410 enum { 411 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 412 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 413 }; 414 415 enum { 416 MLX5_OPCODE_NOP = 0x00, 417 MLX5_OPCODE_SEND_INVAL = 0x01, 418 MLX5_OPCODE_RDMA_WRITE = 0x08, 419 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 420 MLX5_OPCODE_SEND = 0x0a, 421 MLX5_OPCODE_SEND_IMM = 0x0b, 422 MLX5_OPCODE_LSO = 0x0e, 423 MLX5_OPCODE_RDMA_READ = 0x10, 424 MLX5_OPCODE_ATOMIC_CS = 0x11, 425 MLX5_OPCODE_ATOMIC_FA = 0x12, 426 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 427 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 428 MLX5_OPCODE_BIND_MW = 0x18, 429 MLX5_OPCODE_CONFIG_CMD = 0x1f, 430 MLX5_OPCODE_ENHANCED_MPSW = 0x29, 431 432 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 433 MLX5_RECV_OPCODE_SEND = 0x01, 434 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 435 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 436 437 MLX5_CQE_OPCODE_ERROR = 0x1e, 438 MLX5_CQE_OPCODE_RESIZE = 0x16, 439 440 MLX5_OPCODE_SET_PSV = 0x20, 441 MLX5_OPCODE_GET_PSV = 0x21, 442 MLX5_OPCODE_CHECK_PSV = 0x22, 443 MLX5_OPCODE_DUMP = 0x23, 444 MLX5_OPCODE_RGET_PSV = 0x26, 445 MLX5_OPCODE_RCHECK_PSV = 0x27, 446 447 MLX5_OPCODE_UMR = 0x25, 448 449 MLX5_OPCODE_FLOW_TBL_ACCESS = 0x2c, 450 451 MLX5_OPCODE_ACCESS_ASO = 0x2d, 452 }; 453 454 enum { 455 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, 456 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, 457 }; 458 459 enum { 460 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, 461 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, 462 }; 463 464 struct mlx5_wqe_tls_static_params_seg { 465 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; 466 }; 467 468 struct mlx5_wqe_tls_progress_params_seg { 469 __be32 tis_tir_num; 470 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; 471 }; 472 473 enum { 474 MLX5_SET_PORT_RESET_QKEY = 0, 475 MLX5_SET_PORT_GUID0 = 16, 476 MLX5_SET_PORT_NODE_GUID = 17, 477 MLX5_SET_PORT_SYS_GUID = 18, 478 MLX5_SET_PORT_GID_TABLE = 19, 479 MLX5_SET_PORT_PKEY_TABLE = 20, 480 }; 481 482 enum { 483 MLX5_BW_NO_LIMIT = 0, 484 MLX5_100_MBPS_UNIT = 3, 485 MLX5_GBPS_UNIT = 4, 486 }; 487 488 enum { 489 MLX5_MAX_PAGE_SHIFT = 31 490 }; 491 492 enum { 493 /* 494 * Max wqe size for rdma read is 512 bytes, so this 495 * limits our max_sge_rd as the wqe needs to fit: 496 * - ctrl segment (16 bytes) 497 * - rdma segment (16 bytes) 498 * - scatter elements (16 bytes each) 499 */ 500 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 501 }; 502 503 enum mlx5_odp_transport_cap_bits { 504 MLX5_ODP_SUPPORT_SEND = 1 << 31, 505 MLX5_ODP_SUPPORT_RECV = 1 << 30, 506 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 507 MLX5_ODP_SUPPORT_READ = 1 << 28, 508 }; 509 510 struct mlx5_odp_caps { 511 char reserved[0x10]; 512 struct { 513 __be32 rc_odp_caps; 514 __be32 uc_odp_caps; 515 __be32 ud_odp_caps; 516 } per_transport_caps; 517 char reserved2[0xe4]; 518 }; 519 520 struct mlx5_cmd_layout { 521 u8 type; 522 u8 rsvd0[3]; 523 __be32 inlen; 524 __be64 in_ptr; 525 __be32 in[4]; 526 __be32 out[4]; 527 __be64 out_ptr; 528 __be32 outlen; 529 u8 token; 530 u8 sig; 531 u8 rsvd1; 532 u8 status_own; 533 }; 534 535 enum mlx5_rfr_severity_bit_offsets { 536 MLX5_RFR_BIT_OFFSET = 0x7, 537 }; 538 539 struct health_buffer { 540 __be32 assert_var[6]; 541 __be32 rsvd0[2]; 542 __be32 assert_exit_ptr; 543 __be32 assert_callra; 544 __be32 rsvd1[1]; 545 __be32 time; 546 __be32 fw_ver; 547 __be32 hw_id; 548 u8 rfr_severity; 549 u8 rsvd2[3]; 550 u8 irisc_index; 551 u8 synd; 552 __be16 ext_synd; 553 }; 554 555 enum mlx5_initializing_bit_offsets { 556 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 557 }; 558 559 enum mlx5_cmd_addr_l_sz_offset { 560 MLX5_NIC_IFC_OFFSET = 8, 561 }; 562 563 struct mlx5_init_seg { 564 __be32 fw_rev; 565 __be32 cmdif_rev_fw_sub; 566 __be32 rsvd0[2]; 567 __be32 cmdq_addr_h; 568 __be32 cmdq_addr_l_sz; 569 __be32 cmd_dbell; 570 __be32 rsvd1[120]; 571 __be32 initializing; 572 struct health_buffer health; 573 __be32 rsvd2[878]; 574 __be32 cmd_exec_to; 575 __be32 cmd_q_init_to; 576 __be32 internal_timer_h; 577 __be32 internal_timer_l; 578 __be32 rsvd3[2]; 579 __be32 health_counter; 580 __be32 rsvd4[11]; 581 __be32 real_time_h; 582 __be32 real_time_l; 583 __be32 rsvd5[1006]; 584 __be64 ieee1588_clk; 585 __be32 ieee1588_clk_type; 586 __be32 clr_intx; 587 }; 588 589 struct mlx5_eqe_comp { 590 __be32 reserved[6]; 591 __be32 cqn; 592 }; 593 594 struct mlx5_eqe_qp_srq { 595 __be32 reserved1[5]; 596 u8 type; 597 u8 reserved2[3]; 598 __be32 qp_srq_n; 599 }; 600 601 struct mlx5_eqe_cq_err { 602 __be32 cqn; 603 u8 reserved1[7]; 604 u8 syndrome; 605 }; 606 607 struct mlx5_eqe_xrq_err { 608 __be32 reserved1[5]; 609 __be32 type_xrqn; 610 __be32 reserved2; 611 }; 612 613 struct mlx5_eqe_port_state { 614 u8 reserved0[8]; 615 u8 port; 616 }; 617 618 struct mlx5_eqe_gpio { 619 __be32 reserved0[2]; 620 __be64 gpio_event; 621 }; 622 623 struct mlx5_eqe_congestion { 624 u8 type; 625 u8 rsvd0; 626 u8 congestion_level; 627 }; 628 629 struct mlx5_eqe_stall_vl { 630 u8 rsvd0[3]; 631 u8 port_vl; 632 }; 633 634 struct mlx5_eqe_cmd { 635 __be32 vector; 636 __be32 rsvd[6]; 637 }; 638 639 struct mlx5_eqe_page_req { 640 __be16 ec_function; 641 __be16 func_id; 642 __be32 num_pages; 643 __be32 rsvd1[5]; 644 }; 645 646 struct mlx5_eqe_page_fault { 647 __be32 bytes_committed; 648 union { 649 struct { 650 u16 reserved1; 651 __be16 wqe_index; 652 u16 reserved2; 653 __be16 packet_length; 654 __be32 token; 655 u8 reserved4[8]; 656 __be32 pftype_wq; 657 } __packed wqe; 658 struct { 659 __be32 r_key; 660 u16 reserved1; 661 __be16 packet_length; 662 __be32 rdma_op_len; 663 __be64 rdma_va; 664 __be32 pftype_token; 665 } __packed rdma; 666 } __packed; 667 } __packed; 668 669 struct mlx5_eqe_vport_change { 670 u8 rsvd0[2]; 671 __be16 vport_num; 672 __be32 rsvd1[6]; 673 } __packed; 674 675 struct mlx5_eqe_port_module { 676 u8 reserved_at_0[1]; 677 u8 module; 678 u8 reserved_at_2[1]; 679 u8 module_status; 680 u8 reserved_at_4[2]; 681 u8 error_type; 682 } __packed; 683 684 struct mlx5_eqe_pps { 685 u8 rsvd0[3]; 686 u8 pin; 687 u8 rsvd1[4]; 688 union { 689 struct { 690 __be32 time_sec; 691 __be32 time_nsec; 692 }; 693 struct { 694 __be64 time_stamp; 695 }; 696 }; 697 u8 rsvd2[12]; 698 } __packed; 699 700 struct mlx5_eqe_dct { 701 __be32 reserved[6]; 702 __be32 dctn; 703 }; 704 705 struct mlx5_eqe_temp_warning { 706 __be64 sensor_warning_msb; 707 __be64 sensor_warning_lsb; 708 } __packed; 709 710 struct mlx5_eqe_obj_change { 711 u8 rsvd0[2]; 712 __be16 obj_type; 713 __be32 obj_id; 714 } __packed; 715 716 #define SYNC_RST_STATE_MASK 0xf 717 718 enum sync_rst_state_type { 719 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, 720 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, 721 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, 722 MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3, 723 }; 724 725 struct mlx5_eqe_sync_fw_update { 726 u8 reserved_at_0[3]; 727 u8 sync_rst_state; 728 }; 729 730 struct mlx5_eqe_vhca_state { 731 __be16 ec_function; 732 __be16 function_id; 733 } __packed; 734 735 union ev_data { 736 __be32 raw[7]; 737 struct mlx5_eqe_cmd cmd; 738 struct mlx5_eqe_comp comp; 739 struct mlx5_eqe_qp_srq qp_srq; 740 struct mlx5_eqe_cq_err cq_err; 741 struct mlx5_eqe_port_state port; 742 struct mlx5_eqe_gpio gpio; 743 struct mlx5_eqe_congestion cong; 744 struct mlx5_eqe_stall_vl stall_vl; 745 struct mlx5_eqe_page_req req_pages; 746 struct mlx5_eqe_page_fault page_fault; 747 struct mlx5_eqe_vport_change vport_change; 748 struct mlx5_eqe_port_module port_module; 749 struct mlx5_eqe_pps pps; 750 struct mlx5_eqe_dct dct; 751 struct mlx5_eqe_temp_warning temp_warning; 752 struct mlx5_eqe_xrq_err xrq_err; 753 struct mlx5_eqe_sync_fw_update sync_fw_update; 754 struct mlx5_eqe_vhca_state vhca_state; 755 struct mlx5_eqe_obj_change obj_change; 756 } __packed; 757 758 struct mlx5_eqe { 759 u8 rsvd0; 760 u8 type; 761 u8 rsvd1; 762 u8 sub_type; 763 __be32 rsvd2[7]; 764 union ev_data data; 765 __be16 rsvd3; 766 u8 signature; 767 u8 owner; 768 } __packed; 769 770 struct mlx5_cmd_prot_block { 771 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 772 u8 rsvd0[48]; 773 __be64 next; 774 __be32 block_num; 775 u8 rsvd1; 776 u8 token; 777 u8 ctrl_sig; 778 u8 sig; 779 }; 780 781 enum { 782 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 783 }; 784 785 struct mlx5_err_cqe { 786 u8 rsvd0[32]; 787 __be32 srqn; 788 u8 rsvd1[18]; 789 u8 vendor_err_synd; 790 u8 syndrome; 791 __be32 s_wqe_opcode_qpn; 792 __be16 wqe_counter; 793 u8 signature; 794 u8 op_own; 795 }; 796 797 struct mlx5_cqe64 { 798 u8 tls_outer_l3_tunneled; 799 u8 rsvd0; 800 __be16 wqe_id; 801 union { 802 struct { 803 u8 tcppsh_abort_dupack; 804 u8 min_ttl; 805 __be16 tcp_win; 806 __be32 ack_seq_num; 807 } lro; 808 struct { 809 u8 reserved0:1; 810 u8 match:1; 811 u8 flush:1; 812 u8 reserved3:5; 813 u8 header_size; 814 __be16 header_entry_index; 815 __be32 data_offset; 816 } shampo; 817 }; 818 __be32 rss_hash_result; 819 u8 rss_hash_type; 820 u8 ml_path; 821 u8 rsvd20[2]; 822 __be16 check_sum; 823 __be16 slid; 824 __be32 flags_rqpn; 825 u8 hds_ip_ext; 826 u8 l4_l3_hdr_type; 827 __be16 vlan_info; 828 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 829 union { 830 __be32 immediate; 831 __be32 inval_rkey; 832 __be32 pkey; 833 __be32 ft_metadata; 834 }; 835 u8 rsvd40[4]; 836 __be32 byte_cnt; 837 __be32 timestamp_h; 838 __be32 timestamp_l; 839 __be32 sop_drop_qpn; 840 __be16 wqe_counter; 841 union { 842 u8 signature; 843 u8 validity_iteration_count; 844 }; 845 u8 op_own; 846 }; 847 848 struct mlx5_mini_cqe8 { 849 union { 850 __be32 rx_hash_result; 851 struct { 852 __be16 checksum; 853 __be16 stridx; 854 }; 855 struct { 856 __be16 wqe_counter; 857 u8 s_wqe_opcode; 858 u8 reserved; 859 } s_wqe_info; 860 }; 861 __be32 byte_cnt; 862 }; 863 864 enum { 865 MLX5_NO_INLINE_DATA, 866 MLX5_INLINE_DATA32_SEG, 867 MLX5_INLINE_DATA64_SEG, 868 MLX5_COMPRESSED, 869 }; 870 871 enum { 872 MLX5_CQE_FORMAT_CSUM = 0x1, 873 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3, 874 }; 875 876 enum { 877 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0, 878 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1, 879 }; 880 881 #define MLX5_MINI_CQE_ARRAY_SIZE 8 882 883 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 884 { 885 return (cqe->op_own >> 2) & 0x3; 886 } 887 888 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 889 { 890 return cqe->op_own >> 4; 891 } 892 893 static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe) 894 { 895 /* num_of_mini_cqes is zero based */ 896 return get_cqe_opcode(cqe) + 1; 897 } 898 899 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 900 { 901 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1; 902 } 903 904 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 905 { 906 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 907 } 908 909 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 910 { 911 return cqe->tls_outer_l3_tunneled & 0x1; 912 } 913 914 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) 915 { 916 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; 917 } 918 919 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 920 { 921 return cqe->l4_l3_hdr_type & 0x1; 922 } 923 924 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 925 { 926 u32 hi, lo; 927 928 hi = be32_to_cpu(cqe->timestamp_h); 929 lo = be32_to_cpu(cqe->timestamp_l); 930 931 return (u64)lo | ((u64)hi << 32); 932 } 933 934 static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe) 935 { 936 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; 937 } 938 939 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3 940 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9 941 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16 942 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6 943 #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13 944 945 struct mpwrq_cqe_bc { 946 __be16 filler_consumed_strides; 947 __be16 byte_cnt; 948 }; 949 950 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 951 { 952 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 953 954 return be16_to_cpu(bc->byte_cnt); 955 } 956 957 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 958 { 959 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 960 } 961 962 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 963 { 964 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 965 966 return mpwrq_get_cqe_bc_consumed_strides(bc); 967 } 968 969 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 970 { 971 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 972 973 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 974 } 975 976 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 977 { 978 return be16_to_cpu(cqe->wqe_counter); 979 } 980 981 enum { 982 CQE_L4_HDR_TYPE_NONE = 0x0, 983 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 984 CQE_L4_HDR_TYPE_UDP = 0x2, 985 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 986 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 987 }; 988 989 enum { 990 CQE_RSS_HTYPE_IP = GENMASK(3, 2), 991 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 992 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 993 */ 994 CQE_RSS_IP_NONE = 0x0, 995 CQE_RSS_IPV4 = 0x1, 996 CQE_RSS_IPV6 = 0x2, 997 CQE_RSS_RESERVED = 0x3, 998 999 CQE_RSS_HTYPE_L4 = GENMASK(7, 6), 1000 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 1001 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 1002 */ 1003 CQE_RSS_L4_NONE = 0x0, 1004 CQE_RSS_L4_TCP = 0x1, 1005 CQE_RSS_L4_UDP = 0x2, 1006 CQE_RSS_L4_IPSEC = 0x3, 1007 }; 1008 1009 enum { 1010 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 1011 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 1012 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 1013 }; 1014 1015 enum { 1016 CQE_L2_OK = 1 << 0, 1017 CQE_L3_OK = 1 << 1, 1018 CQE_L4_OK = 1 << 2, 1019 }; 1020 1021 enum { 1022 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, 1023 CQE_TLS_OFFLOAD_DECRYPTED = 0x1, 1024 CQE_TLS_OFFLOAD_RESYNC = 0x2, 1025 CQE_TLS_OFFLOAD_ERROR = 0x3, 1026 }; 1027 1028 struct mlx5_sig_err_cqe { 1029 u8 rsvd0[16]; 1030 __be32 expected_trans_sig; 1031 __be32 actual_trans_sig; 1032 __be32 expected_reftag; 1033 __be32 actual_reftag; 1034 __be16 syndrome; 1035 u8 rsvd22[2]; 1036 __be32 mkey; 1037 __be64 err_offset; 1038 u8 rsvd30[8]; 1039 __be32 qpn; 1040 u8 rsvd38[2]; 1041 u8 signature; 1042 u8 op_own; 1043 }; 1044 1045 struct mlx5_wqe_srq_next_seg { 1046 u8 rsvd0[2]; 1047 __be16 next_wqe_index; 1048 u8 signature; 1049 u8 rsvd1[11]; 1050 }; 1051 1052 union mlx5_ext_cqe { 1053 struct ib_grh grh; 1054 u8 inl[64]; 1055 }; 1056 1057 struct mlx5_cqe128 { 1058 union mlx5_ext_cqe inl_grh; 1059 struct mlx5_cqe64 cqe64; 1060 }; 1061 1062 enum { 1063 MLX5_MKEY_STATUS_FREE = 1 << 6, 1064 }; 1065 1066 enum { 1067 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 1068 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 1069 MLX5_MKEY_BSF_EN = 1 << 30, 1070 }; 1071 1072 struct mlx5_mkey_seg { 1073 /* This is a two bit field occupying bits 31-30. 1074 * bit 31 is always 0, 1075 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation 1076 */ 1077 u8 status; 1078 u8 pcie_control; 1079 u8 flags; 1080 u8 version; 1081 __be32 qpn_mkey7_0; 1082 u8 rsvd1[4]; 1083 __be32 flags_pd; 1084 __be64 start_addr; 1085 __be64 len; 1086 __be32 bsfs_octo_size; 1087 u8 rsvd2[16]; 1088 __be32 xlt_oct_size; 1089 u8 rsvd3[3]; 1090 u8 log2_page_size; 1091 u8 rsvd4[4]; 1092 }; 1093 1094 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1095 1096 enum { 1097 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1098 }; 1099 1100 enum { 1101 VPORT_STATE_DOWN = 0x0, 1102 VPORT_STATE_UP = 0x1, 1103 }; 1104 1105 enum { 1106 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, 1107 MLX5_VPORT_ADMIN_STATE_UP = 0x1, 1108 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, 1109 }; 1110 1111 enum { 1112 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1, 1113 MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3, 1114 }; 1115 1116 enum { 1117 MLX5_L3_PROT_TYPE_IPV4 = 0, 1118 MLX5_L3_PROT_TYPE_IPV6 = 1, 1119 }; 1120 1121 enum { 1122 MLX5_L4_PROT_TYPE_TCP = 0, 1123 MLX5_L4_PROT_TYPE_UDP = 1, 1124 }; 1125 1126 enum { 1127 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1128 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1129 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1130 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1131 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1132 }; 1133 1134 enum { 1135 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1136 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1137 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1138 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 1139 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, 1140 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, 1141 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6, 1142 }; 1143 1144 enum { 1145 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1146 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1147 }; 1148 1149 enum { 1150 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1151 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1152 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1153 }; 1154 1155 enum mlx5_list_type { 1156 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1157 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1158 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1159 }; 1160 1161 enum { 1162 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1163 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1164 }; 1165 1166 enum mlx5_wol_mode { 1167 MLX5_WOL_DISABLE = 0, 1168 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1169 MLX5_WOL_MAGIC = 1 << 2, 1170 MLX5_WOL_ARP = 1 << 3, 1171 MLX5_WOL_BROADCAST = 1 << 4, 1172 MLX5_WOL_MULTICAST = 1 << 5, 1173 MLX5_WOL_UNICAST = 1 << 6, 1174 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1175 }; 1176 1177 enum mlx5_mpls_supported_fields { 1178 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, 1179 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, 1180 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, 1181 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 1182 }; 1183 1184 enum mlx5_flex_parser_protos { 1185 MLX5_FLEX_PROTO_GENEVE = 1 << 3, 1186 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, 1187 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, 1188 MLX5_FLEX_PROTO_ICMP = 1 << 8, 1189 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9, 1190 }; 1191 1192 /* MLX5 DEV CAPs */ 1193 1194 /* TODO: EAT.ME */ 1195 enum mlx5_cap_mode { 1196 HCA_CAP_OPMOD_GET_MAX = 0, 1197 HCA_CAP_OPMOD_GET_CUR = 1, 1198 }; 1199 1200 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate 1201 * capability memory. 1202 */ 1203 enum mlx5_cap_type { 1204 MLX5_CAP_GENERAL = 0, 1205 MLX5_CAP_ETHERNET_OFFLOADS, 1206 MLX5_CAP_ODP, 1207 MLX5_CAP_ATOMIC, 1208 MLX5_CAP_ROCE, 1209 MLX5_CAP_IPOIB_OFFLOADS, 1210 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1211 MLX5_CAP_FLOW_TABLE, 1212 MLX5_CAP_ESWITCH_FLOW_TABLE, 1213 MLX5_CAP_ESWITCH, 1214 MLX5_CAP_QOS = 0xc, 1215 MLX5_CAP_DEBUG, 1216 MLX5_CAP_RESERVED_14, 1217 MLX5_CAP_DEV_MEM, 1218 MLX5_CAP_RESERVED_16, 1219 MLX5_CAP_TLS, 1220 MLX5_CAP_VDPA_EMULATION = 0x13, 1221 MLX5_CAP_DEV_EVENT = 0x14, 1222 MLX5_CAP_IPSEC, 1223 MLX5_CAP_CRYPTO = 0x1a, 1224 MLX5_CAP_MACSEC = 0x1f, 1225 MLX5_CAP_GENERAL_2 = 0x20, 1226 MLX5_CAP_PORT_SELECTION = 0x25, 1227 MLX5_CAP_ADV_VIRTUALIZATION = 0x26, 1228 /* NUM OF CAP Types */ 1229 MLX5_CAP_NUM 1230 }; 1231 1232 enum mlx5_pcam_reg_groups { 1233 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1234 }; 1235 1236 enum mlx5_pcam_feature_groups { 1237 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1238 }; 1239 1240 enum mlx5_mcam_reg_groups { 1241 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1242 MLX5_MCAM_REGS_0x9100_0x917F = 0x2, 1243 MLX5_MCAM_REGS_NUM = 0x3, 1244 }; 1245 1246 enum mlx5_mcam_feature_groups { 1247 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1248 }; 1249 1250 enum mlx5_qcam_reg_groups { 1251 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1252 }; 1253 1254 enum mlx5_qcam_feature_groups { 1255 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1256 }; 1257 1258 /* GET Dev Caps macros */ 1259 #define MLX5_CAP_GEN(mdev, cap) \ 1260 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) 1261 1262 #define MLX5_CAP_GEN_64(mdev, cap) \ 1263 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) 1264 1265 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1266 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap) 1267 1268 #define MLX5_CAP_GEN_2(mdev, cap) \ 1269 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) 1270 1271 #define MLX5_CAP_GEN_2_64(mdev, cap) \ 1272 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) 1273 1274 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \ 1275 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap) 1276 1277 #define MLX5_CAP_ETH(mdev, cap) \ 1278 MLX5_GET(per_protocol_networking_offload_caps,\ 1279 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap) 1280 1281 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ 1282 MLX5_GET(per_protocol_networking_offload_caps,\ 1283 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap) 1284 1285 #define MLX5_CAP_ROCE(mdev, cap) \ 1286 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap) 1287 1288 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1289 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap) 1290 1291 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1292 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap) 1293 1294 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1295 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap) 1296 1297 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1298 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) 1299 1300 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ 1301 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) 1302 1303 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1304 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1305 1306 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1307 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1308 1309 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1310 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1311 1312 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1313 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1314 1315 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1316 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1317 1318 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ 1319 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) 1320 1321 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1322 MLX5_GET(flow_table_eswitch_cap, \ 1323 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) 1324 1325 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1326 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1327 1328 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1329 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1330 1331 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1332 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1333 1334 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \ 1335 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap) 1336 1337 #define MLX5_CAP_ESW(mdev, cap) \ 1338 MLX5_GET(e_switch_cap, \ 1339 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap) 1340 1341 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ 1342 MLX5_GET64(flow_table_eswitch_cap, \ 1343 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) 1344 1345 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \ 1346 MLX5_GET(port_selection_cap, \ 1347 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap) 1348 1349 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \ 1350 MLX5_GET(port_selection_cap, \ 1351 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap) 1352 1353 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ 1354 MLX5_GET(adv_virtualization_cap, \ 1355 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap) 1356 1357 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ 1358 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) 1359 1360 #define MLX5_CAP_ODP(mdev, cap)\ 1361 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap) 1362 1363 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1364 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap) 1365 1366 #define MLX5_CAP_QOS(mdev, cap)\ 1367 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap) 1368 1369 #define MLX5_CAP_DEBUG(mdev, cap)\ 1370 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap) 1371 1372 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1373 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1374 1375 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1376 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1377 1378 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1379 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ 1380 mng_access_reg_cap_mask.access_regs.reg) 1381 1382 #define MLX5_CAP_MCAM_REG2(mdev, reg) \ 1383 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ 1384 mng_access_reg_cap_mask.access_regs2.reg) 1385 1386 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1387 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1388 1389 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1390 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1391 1392 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1393 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1394 1395 #define MLX5_CAP_FPGA(mdev, cap) \ 1396 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1397 1398 #define MLX5_CAP64_FPGA(mdev, cap) \ 1399 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1400 1401 #define MLX5_CAP_DEV_MEM(mdev, cap)\ 1402 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) 1403 1404 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ 1405 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) 1406 1407 #define MLX5_CAP_TLS(mdev, cap) \ 1408 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap) 1409 1410 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1411 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap) 1412 1413 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ 1414 MLX5_GET(virtio_emulation_cap, \ 1415 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) 1416 1417 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ 1418 MLX5_GET64(virtio_emulation_cap, \ 1419 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) 1420 1421 #define MLX5_CAP_IPSEC(mdev, cap)\ 1422 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap) 1423 1424 #define MLX5_CAP_CRYPTO(mdev, cap)\ 1425 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap) 1426 1427 #define MLX5_CAP_MACSEC(mdev, cap)\ 1428 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap) 1429 1430 enum { 1431 MLX5_CMD_STAT_OK = 0x0, 1432 MLX5_CMD_STAT_INT_ERR = 0x1, 1433 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1434 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1435 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1436 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1437 MLX5_CMD_STAT_RES_BUSY = 0x6, 1438 MLX5_CMD_STAT_LIM_ERR = 0x8, 1439 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1440 MLX5_CMD_STAT_IX_ERR = 0xa, 1441 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1442 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1443 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1444 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1445 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1446 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1447 }; 1448 1449 enum { 1450 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1451 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1452 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1453 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1454 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1455 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1456 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1457 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1458 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, 1459 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1460 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1461 }; 1462 1463 enum { 1464 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1465 }; 1466 1467 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1468 { 1469 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1470 return 0; 1471 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1472 } 1473 1474 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2 1475 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1 1476 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 1477 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 1478 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1479 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1480 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1481 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1482 1483 #endif /* MLX5_DEVICE_H */ 1484