1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 58 59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 67 68 /* insert a value to a struct */ 69 #define MLX5_SET(typ, p, fld, v) do { \ 70 u32 _v = v; \ 71 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 72 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 73 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 74 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ 75 << __mlx5_dw_bit_off(typ, fld))); \ 76 } while (0) 77 78 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 79 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 80 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 81 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 82 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 83 << __mlx5_dw_bit_off(typ, fld))); \ 84 } while (0) 85 86 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 87 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 88 __mlx5_mask(typ, fld)) 89 90 #define MLX5_GET_PR(typ, p, fld) ({ \ 91 u32 ___t = MLX5_GET(typ, p, fld); \ 92 pr_debug(#fld " = 0x%x\n", ___t); \ 93 ___t; \ 94 }) 95 96 #define __MLX5_SET64(typ, p, fld, v) do { \ 97 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 99 } while (0) 100 101 #define MLX5_SET64(typ, p, fld, v) do { \ 102 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 103 __MLX5_SET64(typ, p, fld, v); \ 104 } while (0) 105 106 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 108 __MLX5_SET64(typ, p, fld[idx], v); \ 109 } while (0) 110 111 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 112 113 #define MLX5_GET64_PR(typ, p, fld) ({ \ 114 u64 ___t = MLX5_GET64(typ, p, fld); \ 115 pr_debug(#fld " = 0x%llx\n", ___t); \ 116 ___t; \ 117 }) 118 119 /* Big endian getters */ 120 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 121 __mlx5_64_off(typ, fld))) 122 123 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 124 type_t tmp; \ 125 switch (sizeof(tmp)) { \ 126 case sizeof(u8): \ 127 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 128 break; \ 129 case sizeof(u16): \ 130 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 131 break; \ 132 case sizeof(u32): \ 133 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 134 break; \ 135 case sizeof(u64): \ 136 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 137 break; \ 138 } \ 139 tmp; \ 140 }) 141 142 enum mlx5_inline_modes { 143 MLX5_INLINE_MODE_NONE, 144 MLX5_INLINE_MODE_L2, 145 MLX5_INLINE_MODE_IP, 146 MLX5_INLINE_MODE_TCP_UDP, 147 }; 148 149 enum { 150 MLX5_MAX_COMMANDS = 32, 151 MLX5_CMD_DATA_BLOCK_SIZE = 512, 152 MLX5_PCI_CMD_XPORT = 7, 153 MLX5_MKEY_BSF_OCTO_SIZE = 4, 154 MLX5_MAX_PSVS = 4, 155 }; 156 157 enum { 158 MLX5_EXTENDED_UD_AV = 0x80000000, 159 }; 160 161 enum { 162 MLX5_CQ_STATE_ARMED = 9, 163 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 164 MLX5_CQ_STATE_FIRED = 0xa, 165 }; 166 167 enum { 168 MLX5_STAT_RATE_OFFSET = 5, 169 }; 170 171 enum { 172 MLX5_INLINE_SEG = 0x80000000, 173 }; 174 175 enum { 176 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 177 }; 178 179 enum { 180 MLX5_MIN_PKEY_TABLE_SIZE = 128, 181 MLX5_MAX_LOG_PKEY_TABLE = 5, 182 }; 183 184 enum { 185 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 186 }; 187 188 enum { 189 MLX5_PFAULT_SUBTYPE_WQE = 0, 190 MLX5_PFAULT_SUBTYPE_RDMA = 1, 191 }; 192 193 enum { 194 MLX5_PERM_LOCAL_READ = 1 << 2, 195 MLX5_PERM_LOCAL_WRITE = 1 << 3, 196 MLX5_PERM_REMOTE_READ = 1 << 4, 197 MLX5_PERM_REMOTE_WRITE = 1 << 5, 198 MLX5_PERM_ATOMIC = 1 << 6, 199 MLX5_PERM_UMR_EN = 1 << 7, 200 }; 201 202 enum { 203 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 204 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 205 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 206 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 207 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 208 }; 209 210 enum { 211 MLX5_EN_RD = (u64)1, 212 MLX5_EN_WR = (u64)2 213 }; 214 215 enum { 216 MLX5_ADAPTER_PAGE_SHIFT = 12, 217 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 218 }; 219 220 enum { 221 MLX5_BFREGS_PER_UAR = 4, 222 MLX5_MAX_UARS = 1 << 8, 223 MLX5_NON_FP_BFREGS_PER_UAR = 2, 224 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 225 MLX5_NON_FP_BFREGS_PER_UAR, 226 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 227 MLX5_NON_FP_BFREGS_PER_UAR, 228 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 229 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 230 }; 231 232 enum { 233 MLX5_MKEY_MASK_LEN = 1ull << 0, 234 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 235 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 236 MLX5_MKEY_MASK_PD = 1ull << 7, 237 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 238 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 239 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 240 MLX5_MKEY_MASK_KEY = 1ull << 13, 241 MLX5_MKEY_MASK_QPN = 1ull << 14, 242 MLX5_MKEY_MASK_LR = 1ull << 17, 243 MLX5_MKEY_MASK_LW = 1ull << 18, 244 MLX5_MKEY_MASK_RR = 1ull << 19, 245 MLX5_MKEY_MASK_RW = 1ull << 20, 246 MLX5_MKEY_MASK_A = 1ull << 21, 247 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 248 MLX5_MKEY_MASK_FREE = 1ull << 29, 249 }; 250 251 enum { 252 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 253 254 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 255 MLX5_UMR_CHECK_FREE = (2 << 5), 256 257 MLX5_UMR_INLINE = (1 << 7), 258 }; 259 260 #define MLX5_UMR_MTT_ALIGNMENT 0x40 261 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 262 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 263 264 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 265 266 enum { 267 MLX5_EVENT_QUEUE_TYPE_QP = 0, 268 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 269 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 270 }; 271 272 enum mlx5_event { 273 MLX5_EVENT_TYPE_COMP = 0x0, 274 275 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 276 MLX5_EVENT_TYPE_COMM_EST = 0x02, 277 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 278 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 279 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 280 281 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 282 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 283 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 284 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 285 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 286 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 287 288 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 289 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 290 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 291 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 292 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 293 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 294 295 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 296 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 297 298 MLX5_EVENT_TYPE_CMD = 0x0a, 299 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 300 301 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 302 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 303 304 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 305 }; 306 307 enum { 308 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 309 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 310 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 311 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 312 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 313 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 314 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 315 }; 316 317 enum { 318 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 319 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 320 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 321 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 322 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 323 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 324 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 325 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 326 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 327 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 328 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 329 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 330 }; 331 332 enum { 333 MLX5_ROCE_VERSION_1 = 0, 334 MLX5_ROCE_VERSION_2 = 2, 335 }; 336 337 enum { 338 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 339 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 340 }; 341 342 enum { 343 MLX5_ROCE_L3_TYPE_IPV4 = 0, 344 MLX5_ROCE_L3_TYPE_IPV6 = 1, 345 }; 346 347 enum { 348 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 349 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 350 }; 351 352 enum { 353 MLX5_OPCODE_NOP = 0x00, 354 MLX5_OPCODE_SEND_INVAL = 0x01, 355 MLX5_OPCODE_RDMA_WRITE = 0x08, 356 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 357 MLX5_OPCODE_SEND = 0x0a, 358 MLX5_OPCODE_SEND_IMM = 0x0b, 359 MLX5_OPCODE_LSO = 0x0e, 360 MLX5_OPCODE_RDMA_READ = 0x10, 361 MLX5_OPCODE_ATOMIC_CS = 0x11, 362 MLX5_OPCODE_ATOMIC_FA = 0x12, 363 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 364 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 365 MLX5_OPCODE_BIND_MW = 0x18, 366 MLX5_OPCODE_CONFIG_CMD = 0x1f, 367 368 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 369 MLX5_RECV_OPCODE_SEND = 0x01, 370 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 371 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 372 373 MLX5_CQE_OPCODE_ERROR = 0x1e, 374 MLX5_CQE_OPCODE_RESIZE = 0x16, 375 376 MLX5_OPCODE_SET_PSV = 0x20, 377 MLX5_OPCODE_GET_PSV = 0x21, 378 MLX5_OPCODE_CHECK_PSV = 0x22, 379 MLX5_OPCODE_RGET_PSV = 0x26, 380 MLX5_OPCODE_RCHECK_PSV = 0x27, 381 382 MLX5_OPCODE_UMR = 0x25, 383 384 }; 385 386 enum { 387 MLX5_SET_PORT_RESET_QKEY = 0, 388 MLX5_SET_PORT_GUID0 = 16, 389 MLX5_SET_PORT_NODE_GUID = 17, 390 MLX5_SET_PORT_SYS_GUID = 18, 391 MLX5_SET_PORT_GID_TABLE = 19, 392 MLX5_SET_PORT_PKEY_TABLE = 20, 393 }; 394 395 enum { 396 MLX5_BW_NO_LIMIT = 0, 397 MLX5_100_MBPS_UNIT = 3, 398 MLX5_GBPS_UNIT = 4, 399 }; 400 401 enum { 402 MLX5_MAX_PAGE_SHIFT = 31 403 }; 404 405 enum { 406 MLX5_CAP_OFF_CMDIF_CSUM = 46, 407 }; 408 409 enum { 410 /* 411 * Max wqe size for rdma read is 512 bytes, so this 412 * limits our max_sge_rd as the wqe needs to fit: 413 * - ctrl segment (16 bytes) 414 * - rdma segment (16 bytes) 415 * - scatter elements (16 bytes each) 416 */ 417 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 418 }; 419 420 enum mlx5_odp_transport_cap_bits { 421 MLX5_ODP_SUPPORT_SEND = 1 << 31, 422 MLX5_ODP_SUPPORT_RECV = 1 << 30, 423 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 424 MLX5_ODP_SUPPORT_READ = 1 << 28, 425 }; 426 427 struct mlx5_odp_caps { 428 char reserved[0x10]; 429 struct { 430 __be32 rc_odp_caps; 431 __be32 uc_odp_caps; 432 __be32 ud_odp_caps; 433 } per_transport_caps; 434 char reserved2[0xe4]; 435 }; 436 437 struct mlx5_cmd_layout { 438 u8 type; 439 u8 rsvd0[3]; 440 __be32 inlen; 441 __be64 in_ptr; 442 __be32 in[4]; 443 __be32 out[4]; 444 __be64 out_ptr; 445 __be32 outlen; 446 u8 token; 447 u8 sig; 448 u8 rsvd1; 449 u8 status_own; 450 }; 451 452 struct health_buffer { 453 __be32 assert_var[5]; 454 __be32 rsvd0[3]; 455 __be32 assert_exit_ptr; 456 __be32 assert_callra; 457 __be32 rsvd1[2]; 458 __be32 fw_ver; 459 __be32 hw_id; 460 __be32 rsvd2; 461 u8 irisc_index; 462 u8 synd; 463 __be16 ext_synd; 464 }; 465 466 struct mlx5_init_seg { 467 __be32 fw_rev; 468 __be32 cmdif_rev_fw_sub; 469 __be32 rsvd0[2]; 470 __be32 cmdq_addr_h; 471 __be32 cmdq_addr_l_sz; 472 __be32 cmd_dbell; 473 __be32 rsvd1[120]; 474 __be32 initializing; 475 struct health_buffer health; 476 __be32 rsvd2[880]; 477 __be32 internal_timer_h; 478 __be32 internal_timer_l; 479 __be32 rsvd3[2]; 480 __be32 health_counter; 481 __be32 rsvd4[1019]; 482 __be64 ieee1588_clk; 483 __be32 ieee1588_clk_type; 484 __be32 clr_intx; 485 }; 486 487 struct mlx5_eqe_comp { 488 __be32 reserved[6]; 489 __be32 cqn; 490 }; 491 492 struct mlx5_eqe_qp_srq { 493 __be32 reserved1[5]; 494 u8 type; 495 u8 reserved2[3]; 496 __be32 qp_srq_n; 497 }; 498 499 struct mlx5_eqe_cq_err { 500 __be32 cqn; 501 u8 reserved1[7]; 502 u8 syndrome; 503 }; 504 505 struct mlx5_eqe_port_state { 506 u8 reserved0[8]; 507 u8 port; 508 }; 509 510 struct mlx5_eqe_gpio { 511 __be32 reserved0[2]; 512 __be64 gpio_event; 513 }; 514 515 struct mlx5_eqe_congestion { 516 u8 type; 517 u8 rsvd0; 518 u8 congestion_level; 519 }; 520 521 struct mlx5_eqe_stall_vl { 522 u8 rsvd0[3]; 523 u8 port_vl; 524 }; 525 526 struct mlx5_eqe_cmd { 527 __be32 vector; 528 __be32 rsvd[6]; 529 }; 530 531 struct mlx5_eqe_page_req { 532 u8 rsvd0[2]; 533 __be16 func_id; 534 __be32 num_pages; 535 __be32 rsvd1[5]; 536 }; 537 538 struct mlx5_eqe_page_fault { 539 __be32 bytes_committed; 540 union { 541 struct { 542 u16 reserved1; 543 __be16 wqe_index; 544 u16 reserved2; 545 __be16 packet_length; 546 __be32 token; 547 u8 reserved4[8]; 548 __be32 pftype_wq; 549 } __packed wqe; 550 struct { 551 __be32 r_key; 552 u16 reserved1; 553 __be16 packet_length; 554 __be32 rdma_op_len; 555 __be64 rdma_va; 556 __be32 pftype_token; 557 } __packed rdma; 558 } __packed; 559 } __packed; 560 561 struct mlx5_eqe_vport_change { 562 u8 rsvd0[2]; 563 __be16 vport_num; 564 __be32 rsvd1[6]; 565 } __packed; 566 567 struct mlx5_eqe_port_module { 568 u8 reserved_at_0[1]; 569 u8 module; 570 u8 reserved_at_2[1]; 571 u8 module_status; 572 u8 reserved_at_4[2]; 573 u8 error_type; 574 } __packed; 575 576 struct mlx5_eqe_pps { 577 u8 rsvd0[3]; 578 u8 pin; 579 u8 rsvd1[4]; 580 union { 581 struct { 582 __be32 time_sec; 583 __be32 time_nsec; 584 }; 585 struct { 586 __be64 time_stamp; 587 }; 588 }; 589 u8 rsvd2[12]; 590 } __packed; 591 592 union ev_data { 593 __be32 raw[7]; 594 struct mlx5_eqe_cmd cmd; 595 struct mlx5_eqe_comp comp; 596 struct mlx5_eqe_qp_srq qp_srq; 597 struct mlx5_eqe_cq_err cq_err; 598 struct mlx5_eqe_port_state port; 599 struct mlx5_eqe_gpio gpio; 600 struct mlx5_eqe_congestion cong; 601 struct mlx5_eqe_stall_vl stall_vl; 602 struct mlx5_eqe_page_req req_pages; 603 struct mlx5_eqe_page_fault page_fault; 604 struct mlx5_eqe_vport_change vport_change; 605 struct mlx5_eqe_port_module port_module; 606 struct mlx5_eqe_pps pps; 607 } __packed; 608 609 struct mlx5_eqe { 610 u8 rsvd0; 611 u8 type; 612 u8 rsvd1; 613 u8 sub_type; 614 __be32 rsvd2[7]; 615 union ev_data data; 616 __be16 rsvd3; 617 u8 signature; 618 u8 owner; 619 } __packed; 620 621 struct mlx5_cmd_prot_block { 622 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 623 u8 rsvd0[48]; 624 __be64 next; 625 __be32 block_num; 626 u8 rsvd1; 627 u8 token; 628 u8 ctrl_sig; 629 u8 sig; 630 }; 631 632 enum { 633 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 634 }; 635 636 struct mlx5_err_cqe { 637 u8 rsvd0[32]; 638 __be32 srqn; 639 u8 rsvd1[18]; 640 u8 vendor_err_synd; 641 u8 syndrome; 642 __be32 s_wqe_opcode_qpn; 643 __be16 wqe_counter; 644 u8 signature; 645 u8 op_own; 646 }; 647 648 struct mlx5_cqe64 { 649 u8 outer_l3_tunneled; 650 u8 rsvd0; 651 __be16 wqe_id; 652 u8 lro_tcppsh_abort_dupack; 653 u8 lro_min_ttl; 654 __be16 lro_tcp_win; 655 __be32 lro_ack_seq_num; 656 __be32 rss_hash_result; 657 u8 rss_hash_type; 658 u8 ml_path; 659 u8 rsvd20[2]; 660 __be16 check_sum; 661 __be16 slid; 662 __be32 flags_rqpn; 663 u8 hds_ip_ext; 664 u8 l4_l3_hdr_type; 665 __be16 vlan_info; 666 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 667 __be32 imm_inval_pkey; 668 u8 rsvd40[4]; 669 __be32 byte_cnt; 670 __be32 timestamp_h; 671 __be32 timestamp_l; 672 __be32 sop_drop_qpn; 673 __be16 wqe_counter; 674 u8 signature; 675 u8 op_own; 676 }; 677 678 struct mlx5_mini_cqe8 { 679 union { 680 __be32 rx_hash_result; 681 struct { 682 __be16 checksum; 683 __be16 rsvd; 684 }; 685 struct { 686 __be16 wqe_counter; 687 u8 s_wqe_opcode; 688 u8 reserved; 689 } s_wqe_info; 690 }; 691 __be32 byte_cnt; 692 }; 693 694 enum { 695 MLX5_NO_INLINE_DATA, 696 MLX5_INLINE_DATA32_SEG, 697 MLX5_INLINE_DATA64_SEG, 698 MLX5_COMPRESSED, 699 }; 700 701 enum { 702 MLX5_CQE_FORMAT_CSUM = 0x1, 703 }; 704 705 #define MLX5_MINI_CQE_ARRAY_SIZE 8 706 707 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 708 { 709 return (cqe->op_own >> 2) & 0x3; 710 } 711 712 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 713 { 714 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 715 } 716 717 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 718 { 719 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 720 } 721 722 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 723 { 724 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 725 } 726 727 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe) 728 { 729 return cqe->outer_l3_tunneled & 0x1; 730 } 731 732 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) 733 { 734 return !!(cqe->l4_l3_hdr_type & 0x1); 735 } 736 737 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 738 { 739 u32 hi, lo; 740 741 hi = be32_to_cpu(cqe->timestamp_h); 742 lo = be32_to_cpu(cqe->timestamp_l); 743 744 return (u64)lo | ((u64)hi << 32); 745 } 746 747 struct mpwrq_cqe_bc { 748 __be16 filler_consumed_strides; 749 __be16 byte_cnt; 750 }; 751 752 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 753 { 754 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 755 756 return be16_to_cpu(bc->byte_cnt); 757 } 758 759 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 760 { 761 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 762 } 763 764 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 765 { 766 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 767 768 return mpwrq_get_cqe_bc_consumed_strides(bc); 769 } 770 771 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 772 { 773 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 774 775 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 776 } 777 778 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 779 { 780 return be16_to_cpu(cqe->wqe_counter); 781 } 782 783 enum { 784 CQE_L4_HDR_TYPE_NONE = 0x0, 785 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 786 CQE_L4_HDR_TYPE_UDP = 0x2, 787 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 788 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 789 }; 790 791 enum { 792 CQE_RSS_HTYPE_IP = 0x3 << 2, 793 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 794 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 795 */ 796 CQE_RSS_HTYPE_L4 = 0x3 << 6, 797 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 798 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 799 */ 800 }; 801 802 enum { 803 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 804 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 805 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 806 }; 807 808 enum { 809 CQE_L2_OK = 1 << 0, 810 CQE_L3_OK = 1 << 1, 811 CQE_L4_OK = 1 << 2, 812 }; 813 814 struct mlx5_sig_err_cqe { 815 u8 rsvd0[16]; 816 __be32 expected_trans_sig; 817 __be32 actual_trans_sig; 818 __be32 expected_reftag; 819 __be32 actual_reftag; 820 __be16 syndrome; 821 u8 rsvd22[2]; 822 __be32 mkey; 823 __be64 err_offset; 824 u8 rsvd30[8]; 825 __be32 qpn; 826 u8 rsvd38[2]; 827 u8 signature; 828 u8 op_own; 829 }; 830 831 struct mlx5_wqe_srq_next_seg { 832 u8 rsvd0[2]; 833 __be16 next_wqe_index; 834 u8 signature; 835 u8 rsvd1[11]; 836 }; 837 838 union mlx5_ext_cqe { 839 struct ib_grh grh; 840 u8 inl[64]; 841 }; 842 843 struct mlx5_cqe128 { 844 union mlx5_ext_cqe inl_grh; 845 struct mlx5_cqe64 cqe64; 846 }; 847 848 enum { 849 MLX5_MKEY_STATUS_FREE = 1 << 6, 850 }; 851 852 enum { 853 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 854 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 855 MLX5_MKEY_BSF_EN = 1 << 30, 856 MLX5_MKEY_LEN64 = 1 << 31, 857 }; 858 859 struct mlx5_mkey_seg { 860 /* This is a two bit field occupying bits 31-30. 861 * bit 31 is always 0, 862 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 863 */ 864 u8 status; 865 u8 pcie_control; 866 u8 flags; 867 u8 version; 868 __be32 qpn_mkey7_0; 869 u8 rsvd1[4]; 870 __be32 flags_pd; 871 __be64 start_addr; 872 __be64 len; 873 __be32 bsfs_octo_size; 874 u8 rsvd2[16]; 875 __be32 xlt_oct_size; 876 u8 rsvd3[3]; 877 u8 log2_page_size; 878 u8 rsvd4[4]; 879 }; 880 881 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 882 883 enum { 884 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 885 }; 886 887 enum { 888 VPORT_STATE_DOWN = 0x0, 889 VPORT_STATE_UP = 0x1, 890 }; 891 892 enum { 893 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 894 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 895 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 896 }; 897 898 enum { 899 MLX5_L3_PROT_TYPE_IPV4 = 0, 900 MLX5_L3_PROT_TYPE_IPV6 = 1, 901 }; 902 903 enum { 904 MLX5_L4_PROT_TYPE_TCP = 0, 905 MLX5_L4_PROT_TYPE_UDP = 1, 906 }; 907 908 enum { 909 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 910 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 911 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 912 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 913 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 914 }; 915 916 enum { 917 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 918 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 919 MLX5_MATCH_INNER_HEADERS = 1 << 2, 920 921 }; 922 923 enum { 924 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 925 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 926 }; 927 928 enum { 929 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 930 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 931 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 932 }; 933 934 enum mlx5_list_type { 935 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 936 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 937 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 938 }; 939 940 enum { 941 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 942 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 943 }; 944 945 enum mlx5_wol_mode { 946 MLX5_WOL_DISABLE = 0, 947 MLX5_WOL_SECURED_MAGIC = 1 << 1, 948 MLX5_WOL_MAGIC = 1 << 2, 949 MLX5_WOL_ARP = 1 << 3, 950 MLX5_WOL_BROADCAST = 1 << 4, 951 MLX5_WOL_MULTICAST = 1 << 5, 952 MLX5_WOL_UNICAST = 1 << 6, 953 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 954 }; 955 956 /* MLX5 DEV CAPs */ 957 958 /* TODO: EAT.ME */ 959 enum mlx5_cap_mode { 960 HCA_CAP_OPMOD_GET_MAX = 0, 961 HCA_CAP_OPMOD_GET_CUR = 1, 962 }; 963 964 enum mlx5_cap_type { 965 MLX5_CAP_GENERAL = 0, 966 MLX5_CAP_ETHERNET_OFFLOADS, 967 MLX5_CAP_ODP, 968 MLX5_CAP_ATOMIC, 969 MLX5_CAP_ROCE, 970 MLX5_CAP_IPOIB_OFFLOADS, 971 MLX5_CAP_EOIB_OFFLOADS, 972 MLX5_CAP_FLOW_TABLE, 973 MLX5_CAP_ESWITCH_FLOW_TABLE, 974 MLX5_CAP_ESWITCH, 975 MLX5_CAP_RESERVED, 976 MLX5_CAP_VECTOR_CALC, 977 MLX5_CAP_QOS, 978 MLX5_CAP_FPGA, 979 /* NUM OF CAP Types */ 980 MLX5_CAP_NUM 981 }; 982 983 enum mlx5_pcam_reg_groups { 984 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 985 }; 986 987 enum mlx5_pcam_feature_groups { 988 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 989 }; 990 991 enum mlx5_mcam_reg_groups { 992 MLX5_MCAM_REGS_FIRST_128 = 0x0, 993 }; 994 995 enum mlx5_mcam_feature_groups { 996 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 997 }; 998 999 /* GET Dev Caps macros */ 1000 #define MLX5_CAP_GEN(mdev, cap) \ 1001 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1002 1003 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1004 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap) 1005 1006 #define MLX5_CAP_ETH(mdev, cap) \ 1007 MLX5_GET(per_protocol_networking_offload_caps,\ 1008 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1009 1010 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1011 MLX5_GET(per_protocol_networking_offload_caps,\ 1012 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1013 1014 #define MLX5_CAP_ROCE(mdev, cap) \ 1015 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap) 1016 1017 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1018 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap) 1019 1020 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1021 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap) 1022 1023 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1024 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap) 1025 1026 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1027 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1028 1029 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1030 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap) 1031 1032 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1033 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1034 1035 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1036 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1037 1038 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1039 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1040 1041 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1042 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1043 1044 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1045 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1046 1047 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1048 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1049 1050 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1051 MLX5_GET(flow_table_eswitch_cap, \ 1052 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1053 1054 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1055 MLX5_GET(flow_table_eswitch_cap, \ 1056 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1057 1058 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1059 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1060 1061 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1062 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1063 1064 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1065 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1066 1067 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1068 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1069 1070 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1071 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1072 1073 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1074 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1075 1076 #define MLX5_CAP_ESW(mdev, cap) \ 1077 MLX5_GET(e_switch_cap, \ 1078 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap) 1079 1080 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1081 MLX5_GET(e_switch_cap, \ 1082 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap) 1083 1084 #define MLX5_CAP_ODP(mdev, cap)\ 1085 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap) 1086 1087 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1088 MLX5_GET(vector_calc_cap, \ 1089 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap) 1090 1091 #define MLX5_CAP_QOS(mdev, cap)\ 1092 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) 1093 1094 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1095 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1096 1097 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1098 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1099 1100 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1101 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1102 1103 #define MLX5_CAP_FPGA(mdev, cap) \ 1104 MLX5_GET(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap) 1105 1106 #define MLX5_CAP64_FPGA(mdev, cap) \ 1107 MLX5_GET64(fpga_cap, (mdev)->caps.hca_cur[MLX5_CAP_FPGA], cap) 1108 1109 enum { 1110 MLX5_CMD_STAT_OK = 0x0, 1111 MLX5_CMD_STAT_INT_ERR = 0x1, 1112 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1113 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1114 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1115 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1116 MLX5_CMD_STAT_RES_BUSY = 0x6, 1117 MLX5_CMD_STAT_LIM_ERR = 0x8, 1118 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1119 MLX5_CMD_STAT_IX_ERR = 0xa, 1120 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1121 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1122 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1123 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1124 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1125 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1126 }; 1127 1128 enum { 1129 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1130 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1131 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1132 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1133 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1134 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1135 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1136 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1137 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1138 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1139 }; 1140 1141 enum { 1142 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1143 }; 1144 1145 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1146 { 1147 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1148 return 0; 1149 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1150 } 1151 1152 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 1153 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 1154 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1155 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1156 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1157 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1158 1159 #endif /* MLX5_DEVICE_H */ 1160