1 /* 2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 39 #if defined(__LITTLE_ENDIAN) 40 #define MLX5_SET_HOST_ENDIANNESS 0 41 #elif defined(__BIG_ENDIAN) 42 #define MLX5_SET_HOST_ENDIANNESS 0x80 43 #else 44 #error Host endianness not defined 45 #endif 46 47 enum { 48 MLX5_MAX_COMMANDS = 32, 49 MLX5_CMD_DATA_BLOCK_SIZE = 512, 50 MLX5_PCI_CMD_XPORT = 7, 51 }; 52 53 enum { 54 MLX5_EXTENDED_UD_AV = 0x80000000, 55 }; 56 57 enum { 58 MLX5_CQ_STATE_ARMED = 9, 59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 60 MLX5_CQ_STATE_FIRED = 0xa, 61 }; 62 63 enum { 64 MLX5_STAT_RATE_OFFSET = 5, 65 }; 66 67 enum { 68 MLX5_INLINE_SEG = 0x80000000, 69 }; 70 71 enum { 72 MLX5_PERM_LOCAL_READ = 1 << 2, 73 MLX5_PERM_LOCAL_WRITE = 1 << 3, 74 MLX5_PERM_REMOTE_READ = 1 << 4, 75 MLX5_PERM_REMOTE_WRITE = 1 << 5, 76 MLX5_PERM_ATOMIC = 1 << 6, 77 MLX5_PERM_UMR_EN = 1 << 7, 78 }; 79 80 enum { 81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 86 }; 87 88 enum { 89 MLX5_ACCESS_MODE_PA = 0, 90 MLX5_ACCESS_MODE_MTT = 1, 91 MLX5_ACCESS_MODE_KLM = 2 92 }; 93 94 enum { 95 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 97 MLX5_MKEY_BSF_EN = 1 << 30, 98 MLX5_MKEY_LEN64 = 1 << 31, 99 }; 100 101 enum { 102 MLX5_EN_RD = (u64)1, 103 MLX5_EN_WR = (u64)2 104 }; 105 106 enum { 107 MLX5_BF_REGS_PER_PAGE = 4, 108 MLX5_MAX_UAR_PAGES = 1 << 8, 109 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 110 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 111 }; 112 113 enum { 114 MLX5_MKEY_MASK_LEN = 1ull << 0, 115 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 116 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 117 MLX5_MKEY_MASK_PD = 1ull << 7, 118 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 119 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 120 MLX5_MKEY_MASK_KEY = 1ull << 13, 121 MLX5_MKEY_MASK_QPN = 1ull << 14, 122 MLX5_MKEY_MASK_LR = 1ull << 17, 123 MLX5_MKEY_MASK_LW = 1ull << 18, 124 MLX5_MKEY_MASK_RR = 1ull << 19, 125 MLX5_MKEY_MASK_RW = 1ull << 20, 126 MLX5_MKEY_MASK_A = 1ull << 21, 127 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 128 MLX5_MKEY_MASK_FREE = 1ull << 29, 129 }; 130 131 enum mlx5_event { 132 MLX5_EVENT_TYPE_COMP = 0x0, 133 134 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 135 MLX5_EVENT_TYPE_COMM_EST = 0x02, 136 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 137 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 138 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 139 140 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 141 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 142 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 143 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 144 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 145 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 146 147 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 148 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 149 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 150 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 151 152 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 153 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 154 155 MLX5_EVENT_TYPE_CMD = 0x0a, 156 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 157 }; 158 159 enum { 160 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 161 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 162 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 163 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 164 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 165 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 166 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 167 }; 168 169 enum { 170 MLX5_DEV_CAP_FLAG_RC = 1LL << 0, 171 MLX5_DEV_CAP_FLAG_UC = 1LL << 1, 172 MLX5_DEV_CAP_FLAG_UD = 1LL << 2, 173 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 174 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6, 175 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 176 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 177 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 178 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 179 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 180 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 181 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 182 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32, 183 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38, 184 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39, 185 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 186 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41, 187 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 188 }; 189 190 enum { 191 MLX5_OPCODE_NOP = 0x00, 192 MLX5_OPCODE_SEND_INVAL = 0x01, 193 MLX5_OPCODE_RDMA_WRITE = 0x08, 194 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 195 MLX5_OPCODE_SEND = 0x0a, 196 MLX5_OPCODE_SEND_IMM = 0x0b, 197 MLX5_OPCODE_RDMA_READ = 0x10, 198 MLX5_OPCODE_ATOMIC_CS = 0x11, 199 MLX5_OPCODE_ATOMIC_FA = 0x12, 200 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 201 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 202 MLX5_OPCODE_BIND_MW = 0x18, 203 MLX5_OPCODE_CONFIG_CMD = 0x1f, 204 205 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 206 MLX5_RECV_OPCODE_SEND = 0x01, 207 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 208 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 209 210 MLX5_CQE_OPCODE_ERROR = 0x1e, 211 MLX5_CQE_OPCODE_RESIZE = 0x16, 212 213 MLX5_OPCODE_SET_PSV = 0x20, 214 MLX5_OPCODE_GET_PSV = 0x21, 215 MLX5_OPCODE_CHECK_PSV = 0x22, 216 MLX5_OPCODE_RGET_PSV = 0x26, 217 MLX5_OPCODE_RCHECK_PSV = 0x27, 218 219 MLX5_OPCODE_UMR = 0x25, 220 221 }; 222 223 enum { 224 MLX5_SET_PORT_RESET_QKEY = 0, 225 MLX5_SET_PORT_GUID0 = 16, 226 MLX5_SET_PORT_NODE_GUID = 17, 227 MLX5_SET_PORT_SYS_GUID = 18, 228 MLX5_SET_PORT_GID_TABLE = 19, 229 MLX5_SET_PORT_PKEY_TABLE = 20, 230 }; 231 232 enum { 233 MLX5_MAX_PAGE_SHIFT = 31 234 }; 235 236 enum { 237 MLX5_ADAPTER_PAGE_SHIFT = 12, 238 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 239 }; 240 241 enum { 242 MLX5_CAP_OFF_DCT = 41, 243 MLX5_CAP_OFF_CMDIF_CSUM = 46, 244 }; 245 246 struct mlx5_inbox_hdr { 247 __be16 opcode; 248 u8 rsvd[4]; 249 __be16 opmod; 250 }; 251 252 struct mlx5_outbox_hdr { 253 u8 status; 254 u8 rsvd[3]; 255 __be32 syndrome; 256 }; 257 258 struct mlx5_cmd_query_adapter_mbox_in { 259 struct mlx5_inbox_hdr hdr; 260 u8 rsvd[8]; 261 }; 262 263 struct mlx5_cmd_query_adapter_mbox_out { 264 struct mlx5_outbox_hdr hdr; 265 u8 rsvd0[24]; 266 u8 intapin; 267 u8 rsvd1[13]; 268 __be16 vsd_vendor_id; 269 u8 vsd[208]; 270 u8 vsd_psid[16]; 271 }; 272 273 struct mlx5_hca_cap { 274 u8 rsvd1[16]; 275 u8 log_max_srq_sz; 276 u8 log_max_qp_sz; 277 u8 rsvd2; 278 u8 log_max_qp; 279 u8 log_max_strq_sz; 280 u8 log_max_srqs; 281 u8 rsvd4[2]; 282 u8 rsvd5; 283 u8 log_max_cq_sz; 284 u8 rsvd6; 285 u8 log_max_cq; 286 u8 log_max_eq_sz; 287 u8 log_max_mkey; 288 u8 rsvd7; 289 u8 log_max_eq; 290 u8 max_indirection; 291 u8 log_max_mrw_sz; 292 u8 log_max_bsf_list_sz; 293 u8 log_max_klm_list_sz; 294 u8 rsvd_8_0; 295 u8 log_max_ra_req_dc; 296 u8 rsvd_8_1; 297 u8 log_max_ra_res_dc; 298 u8 rsvd9; 299 u8 log_max_ra_req_qp; 300 u8 rsvd10; 301 u8 log_max_ra_res_qp; 302 u8 rsvd11[4]; 303 __be16 max_qp_count; 304 __be16 rsvd12; 305 u8 rsvd13; 306 u8 local_ca_ack_delay; 307 u8 rsvd14; 308 u8 num_ports; 309 u8 log_max_msg; 310 u8 rsvd15[3]; 311 __be16 stat_rate_support; 312 u8 rsvd16[2]; 313 __be64 flags; 314 u8 rsvd17; 315 u8 uar_sz; 316 u8 rsvd18; 317 u8 log_pg_sz; 318 __be16 bf_log_bf_reg_size; 319 u8 rsvd19[4]; 320 __be16 max_desc_sz_sq; 321 u8 rsvd20[2]; 322 __be16 max_desc_sz_rq; 323 u8 rsvd21[2]; 324 __be16 max_desc_sz_sq_dc; 325 __be32 max_qp_mcg; 326 u8 rsvd22[3]; 327 u8 log_max_mcg; 328 u8 rsvd23; 329 u8 log_max_pd; 330 u8 rsvd24; 331 u8 log_max_xrcd; 332 u8 rsvd25[42]; 333 __be16 log_uar_page_sz; 334 u8 rsvd26[28]; 335 u8 log_max_atomic_size_qp; 336 u8 rsvd27[2]; 337 u8 log_max_atomic_size_dc; 338 u8 rsvd28[76]; 339 }; 340 341 342 struct mlx5_cmd_query_hca_cap_mbox_in { 343 struct mlx5_inbox_hdr hdr; 344 u8 rsvd[8]; 345 }; 346 347 348 struct mlx5_cmd_query_hca_cap_mbox_out { 349 struct mlx5_outbox_hdr hdr; 350 u8 rsvd0[8]; 351 struct mlx5_hca_cap hca_cap; 352 }; 353 354 355 struct mlx5_cmd_set_hca_cap_mbox_in { 356 struct mlx5_inbox_hdr hdr; 357 u8 rsvd[8]; 358 struct mlx5_hca_cap hca_cap; 359 }; 360 361 362 struct mlx5_cmd_set_hca_cap_mbox_out { 363 struct mlx5_outbox_hdr hdr; 364 u8 rsvd0[8]; 365 }; 366 367 368 struct mlx5_cmd_init_hca_mbox_in { 369 struct mlx5_inbox_hdr hdr; 370 u8 rsvd0[2]; 371 __be16 profile; 372 u8 rsvd1[4]; 373 }; 374 375 struct mlx5_cmd_init_hca_mbox_out { 376 struct mlx5_outbox_hdr hdr; 377 u8 rsvd[8]; 378 }; 379 380 struct mlx5_cmd_teardown_hca_mbox_in { 381 struct mlx5_inbox_hdr hdr; 382 u8 rsvd0[2]; 383 __be16 profile; 384 u8 rsvd1[4]; 385 }; 386 387 struct mlx5_cmd_teardown_hca_mbox_out { 388 struct mlx5_outbox_hdr hdr; 389 u8 rsvd[8]; 390 }; 391 392 struct mlx5_cmd_layout { 393 u8 type; 394 u8 rsvd0[3]; 395 __be32 inlen; 396 __be64 in_ptr; 397 __be32 in[4]; 398 __be32 out[4]; 399 __be64 out_ptr; 400 __be32 outlen; 401 u8 token; 402 u8 sig; 403 u8 rsvd1; 404 u8 status_own; 405 }; 406 407 408 struct health_buffer { 409 __be32 assert_var[5]; 410 __be32 rsvd0[3]; 411 __be32 assert_exit_ptr; 412 __be32 assert_callra; 413 __be32 rsvd1[2]; 414 __be32 fw_ver; 415 __be32 hw_id; 416 __be32 rsvd2; 417 u8 irisc_index; 418 u8 synd; 419 __be16 ext_sync; 420 }; 421 422 struct mlx5_init_seg { 423 __be32 fw_rev; 424 __be32 cmdif_rev_fw_sub; 425 __be32 rsvd0[2]; 426 __be32 cmdq_addr_h; 427 __be32 cmdq_addr_l_sz; 428 __be32 cmd_dbell; 429 __be32 rsvd1[121]; 430 struct health_buffer health; 431 __be32 rsvd2[884]; 432 __be32 health_counter; 433 __be32 rsvd3[1019]; 434 __be64 ieee1588_clk; 435 __be32 ieee1588_clk_type; 436 __be32 clr_intx; 437 }; 438 439 struct mlx5_eqe_comp { 440 __be32 reserved[6]; 441 __be32 cqn; 442 }; 443 444 struct mlx5_eqe_qp_srq { 445 __be32 reserved[6]; 446 __be32 qp_srq_n; 447 }; 448 449 struct mlx5_eqe_cq_err { 450 __be32 cqn; 451 u8 reserved1[7]; 452 u8 syndrome; 453 }; 454 455 struct mlx5_eqe_dropped_packet { 456 }; 457 458 struct mlx5_eqe_port_state { 459 u8 reserved0[8]; 460 u8 port; 461 }; 462 463 struct mlx5_eqe_gpio { 464 __be32 reserved0[2]; 465 __be64 gpio_event; 466 }; 467 468 struct mlx5_eqe_congestion { 469 u8 type; 470 u8 rsvd0; 471 u8 congestion_level; 472 }; 473 474 struct mlx5_eqe_stall_vl { 475 u8 rsvd0[3]; 476 u8 port_vl; 477 }; 478 479 struct mlx5_eqe_cmd { 480 __be32 vector; 481 __be32 rsvd[6]; 482 }; 483 484 struct mlx5_eqe_page_req { 485 u8 rsvd0[2]; 486 __be16 func_id; 487 __be32 num_pages; 488 __be32 rsvd1[5]; 489 }; 490 491 union ev_data { 492 __be32 raw[7]; 493 struct mlx5_eqe_cmd cmd; 494 struct mlx5_eqe_comp comp; 495 struct mlx5_eqe_qp_srq qp_srq; 496 struct mlx5_eqe_cq_err cq_err; 497 struct mlx5_eqe_dropped_packet dp; 498 struct mlx5_eqe_port_state port; 499 struct mlx5_eqe_gpio gpio; 500 struct mlx5_eqe_congestion cong; 501 struct mlx5_eqe_stall_vl stall_vl; 502 struct mlx5_eqe_page_req req_pages; 503 } __packed; 504 505 struct mlx5_eqe { 506 u8 rsvd0; 507 u8 type; 508 u8 rsvd1; 509 u8 sub_type; 510 __be32 rsvd2[7]; 511 union ev_data data; 512 __be16 rsvd3; 513 u8 signature; 514 u8 owner; 515 } __packed; 516 517 struct mlx5_cmd_prot_block { 518 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 519 u8 rsvd0[48]; 520 __be64 next; 521 __be32 block_num; 522 u8 rsvd1; 523 u8 token; 524 u8 ctrl_sig; 525 u8 sig; 526 }; 527 528 struct mlx5_err_cqe { 529 u8 rsvd0[32]; 530 __be32 srqn; 531 u8 rsvd1[18]; 532 u8 vendor_err_synd; 533 u8 syndrome; 534 __be32 s_wqe_opcode_qpn; 535 __be16 wqe_counter; 536 u8 signature; 537 u8 op_own; 538 }; 539 540 struct mlx5_cqe64 { 541 u8 rsvd0[17]; 542 u8 ml_path; 543 u8 rsvd20[4]; 544 __be16 slid; 545 __be32 flags_rqpn; 546 u8 rsvd28[4]; 547 __be32 srqn; 548 __be32 imm_inval_pkey; 549 u8 rsvd40[4]; 550 __be32 byte_cnt; 551 __be64 timestamp; 552 __be32 sop_drop_qpn; 553 __be16 wqe_counter; 554 u8 signature; 555 u8 op_own; 556 }; 557 558 struct mlx5_wqe_srq_next_seg { 559 u8 rsvd0[2]; 560 __be16 next_wqe_index; 561 u8 signature; 562 u8 rsvd1[11]; 563 }; 564 565 union mlx5_ext_cqe { 566 struct ib_grh grh; 567 u8 inl[64]; 568 }; 569 570 struct mlx5_cqe128 { 571 union mlx5_ext_cqe inl_grh; 572 struct mlx5_cqe64 cqe64; 573 }; 574 575 struct mlx5_srq_ctx { 576 u8 state_log_sz; 577 u8 rsvd0[3]; 578 __be32 flags_xrcd; 579 __be32 pgoff_cqn; 580 u8 rsvd1[4]; 581 u8 log_pg_sz; 582 u8 rsvd2[7]; 583 __be32 pd; 584 __be16 lwm; 585 __be16 wqe_cnt; 586 u8 rsvd3[8]; 587 __be64 db_record; 588 }; 589 590 struct mlx5_create_srq_mbox_in { 591 struct mlx5_inbox_hdr hdr; 592 __be32 input_srqn; 593 u8 rsvd0[4]; 594 struct mlx5_srq_ctx ctx; 595 u8 rsvd1[208]; 596 __be64 pas[0]; 597 }; 598 599 struct mlx5_create_srq_mbox_out { 600 struct mlx5_outbox_hdr hdr; 601 __be32 srqn; 602 u8 rsvd[4]; 603 }; 604 605 struct mlx5_destroy_srq_mbox_in { 606 struct mlx5_inbox_hdr hdr; 607 __be32 srqn; 608 u8 rsvd[4]; 609 }; 610 611 struct mlx5_destroy_srq_mbox_out { 612 struct mlx5_outbox_hdr hdr; 613 u8 rsvd[8]; 614 }; 615 616 struct mlx5_query_srq_mbox_in { 617 struct mlx5_inbox_hdr hdr; 618 __be32 srqn; 619 u8 rsvd0[4]; 620 }; 621 622 struct mlx5_query_srq_mbox_out { 623 struct mlx5_outbox_hdr hdr; 624 u8 rsvd0[8]; 625 struct mlx5_srq_ctx ctx; 626 u8 rsvd1[32]; 627 __be64 pas[0]; 628 }; 629 630 struct mlx5_arm_srq_mbox_in { 631 struct mlx5_inbox_hdr hdr; 632 __be32 srqn; 633 __be16 rsvd; 634 __be16 lwm; 635 }; 636 637 struct mlx5_arm_srq_mbox_out { 638 struct mlx5_outbox_hdr hdr; 639 u8 rsvd[8]; 640 }; 641 642 struct mlx5_cq_context { 643 u8 status; 644 u8 cqe_sz_flags; 645 u8 st; 646 u8 rsvd3; 647 u8 rsvd4[6]; 648 __be16 page_offset; 649 __be32 log_sz_usr_page; 650 __be16 cq_period; 651 __be16 cq_max_count; 652 __be16 rsvd20; 653 __be16 c_eqn; 654 u8 log_pg_sz; 655 u8 rsvd25[7]; 656 __be32 last_notified_index; 657 __be32 solicit_producer_index; 658 __be32 consumer_counter; 659 __be32 producer_counter; 660 u8 rsvd48[8]; 661 __be64 db_record_addr; 662 }; 663 664 struct mlx5_create_cq_mbox_in { 665 struct mlx5_inbox_hdr hdr; 666 __be32 input_cqn; 667 u8 rsvdx[4]; 668 struct mlx5_cq_context ctx; 669 u8 rsvd6[192]; 670 __be64 pas[0]; 671 }; 672 673 struct mlx5_create_cq_mbox_out { 674 struct mlx5_outbox_hdr hdr; 675 __be32 cqn; 676 u8 rsvd0[4]; 677 }; 678 679 struct mlx5_destroy_cq_mbox_in { 680 struct mlx5_inbox_hdr hdr; 681 __be32 cqn; 682 u8 rsvd0[4]; 683 }; 684 685 struct mlx5_destroy_cq_mbox_out { 686 struct mlx5_outbox_hdr hdr; 687 u8 rsvd0[8]; 688 }; 689 690 struct mlx5_query_cq_mbox_in { 691 struct mlx5_inbox_hdr hdr; 692 __be32 cqn; 693 u8 rsvd0[4]; 694 }; 695 696 struct mlx5_query_cq_mbox_out { 697 struct mlx5_outbox_hdr hdr; 698 u8 rsvd0[8]; 699 struct mlx5_cq_context ctx; 700 u8 rsvd6[16]; 701 __be64 pas[0]; 702 }; 703 704 struct mlx5_modify_cq_mbox_in { 705 struct mlx5_inbox_hdr hdr; 706 __be32 cqn; 707 __be32 field_select; 708 struct mlx5_cq_context ctx; 709 u8 rsvd[192]; 710 __be64 pas[0]; 711 }; 712 713 struct mlx5_modify_cq_mbox_out { 714 struct mlx5_outbox_hdr hdr; 715 u8 rsvd[8]; 716 }; 717 718 struct mlx5_enable_hca_mbox_in { 719 struct mlx5_inbox_hdr hdr; 720 u8 rsvd[8]; 721 }; 722 723 struct mlx5_enable_hca_mbox_out { 724 struct mlx5_outbox_hdr hdr; 725 u8 rsvd[8]; 726 }; 727 728 struct mlx5_disable_hca_mbox_in { 729 struct mlx5_inbox_hdr hdr; 730 u8 rsvd[8]; 731 }; 732 733 struct mlx5_disable_hca_mbox_out { 734 struct mlx5_outbox_hdr hdr; 735 u8 rsvd[8]; 736 }; 737 738 struct mlx5_eq_context { 739 u8 status; 740 u8 ec_oi; 741 u8 st; 742 u8 rsvd2[7]; 743 __be16 page_pffset; 744 __be32 log_sz_usr_page; 745 u8 rsvd3[7]; 746 u8 intr; 747 u8 log_page_size; 748 u8 rsvd4[15]; 749 __be32 consumer_counter; 750 __be32 produser_counter; 751 u8 rsvd5[16]; 752 }; 753 754 struct mlx5_create_eq_mbox_in { 755 struct mlx5_inbox_hdr hdr; 756 u8 rsvd0[3]; 757 u8 input_eqn; 758 u8 rsvd1[4]; 759 struct mlx5_eq_context ctx; 760 u8 rsvd2[8]; 761 __be64 events_mask; 762 u8 rsvd3[176]; 763 __be64 pas[0]; 764 }; 765 766 struct mlx5_create_eq_mbox_out { 767 struct mlx5_outbox_hdr hdr; 768 u8 rsvd0[3]; 769 u8 eq_number; 770 u8 rsvd1[4]; 771 }; 772 773 struct mlx5_destroy_eq_mbox_in { 774 struct mlx5_inbox_hdr hdr; 775 u8 rsvd0[3]; 776 u8 eqn; 777 u8 rsvd1[4]; 778 }; 779 780 struct mlx5_destroy_eq_mbox_out { 781 struct mlx5_outbox_hdr hdr; 782 u8 rsvd[8]; 783 }; 784 785 struct mlx5_map_eq_mbox_in { 786 struct mlx5_inbox_hdr hdr; 787 __be64 mask; 788 u8 mu; 789 u8 rsvd0[2]; 790 u8 eqn; 791 u8 rsvd1[24]; 792 }; 793 794 struct mlx5_map_eq_mbox_out { 795 struct mlx5_outbox_hdr hdr; 796 u8 rsvd[8]; 797 }; 798 799 struct mlx5_query_eq_mbox_in { 800 struct mlx5_inbox_hdr hdr; 801 u8 rsvd0[3]; 802 u8 eqn; 803 u8 rsvd1[4]; 804 }; 805 806 struct mlx5_query_eq_mbox_out { 807 struct mlx5_outbox_hdr hdr; 808 u8 rsvd[8]; 809 struct mlx5_eq_context ctx; 810 }; 811 812 struct mlx5_mkey_seg { 813 /* This is a two bit field occupying bits 31-30. 814 * bit 31 is always 0, 815 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 816 */ 817 u8 status; 818 u8 pcie_control; 819 u8 flags; 820 u8 version; 821 __be32 qpn_mkey7_0; 822 u8 rsvd1[4]; 823 __be32 flags_pd; 824 __be64 start_addr; 825 __be64 len; 826 __be32 bsfs_octo_size; 827 u8 rsvd2[16]; 828 __be32 xlt_oct_size; 829 u8 rsvd3[3]; 830 u8 log2_page_size; 831 u8 rsvd4[4]; 832 }; 833 834 struct mlx5_query_special_ctxs_mbox_in { 835 struct mlx5_inbox_hdr hdr; 836 u8 rsvd[8]; 837 }; 838 839 struct mlx5_query_special_ctxs_mbox_out { 840 struct mlx5_outbox_hdr hdr; 841 __be32 dump_fill_mkey; 842 __be32 reserved_lkey; 843 }; 844 845 struct mlx5_create_mkey_mbox_in { 846 struct mlx5_inbox_hdr hdr; 847 __be32 input_mkey_index; 848 u8 rsvd0[4]; 849 struct mlx5_mkey_seg seg; 850 u8 rsvd1[16]; 851 __be32 xlat_oct_act_size; 852 __be32 rsvd2; 853 u8 rsvd3[168]; 854 __be64 pas[0]; 855 }; 856 857 struct mlx5_create_mkey_mbox_out { 858 struct mlx5_outbox_hdr hdr; 859 __be32 mkey; 860 u8 rsvd[4]; 861 }; 862 863 struct mlx5_destroy_mkey_mbox_in { 864 struct mlx5_inbox_hdr hdr; 865 __be32 mkey; 866 u8 rsvd[4]; 867 }; 868 869 struct mlx5_destroy_mkey_mbox_out { 870 struct mlx5_outbox_hdr hdr; 871 u8 rsvd[8]; 872 }; 873 874 struct mlx5_query_mkey_mbox_in { 875 struct mlx5_inbox_hdr hdr; 876 __be32 mkey; 877 }; 878 879 struct mlx5_query_mkey_mbox_out { 880 struct mlx5_outbox_hdr hdr; 881 __be64 pas[0]; 882 }; 883 884 struct mlx5_modify_mkey_mbox_in { 885 struct mlx5_inbox_hdr hdr; 886 __be32 mkey; 887 __be64 pas[0]; 888 }; 889 890 struct mlx5_modify_mkey_mbox_out { 891 struct mlx5_outbox_hdr hdr; 892 u8 rsvd[8]; 893 }; 894 895 struct mlx5_dump_mkey_mbox_in { 896 struct mlx5_inbox_hdr hdr; 897 }; 898 899 struct mlx5_dump_mkey_mbox_out { 900 struct mlx5_outbox_hdr hdr; 901 __be32 mkey; 902 }; 903 904 struct mlx5_mad_ifc_mbox_in { 905 struct mlx5_inbox_hdr hdr; 906 __be16 remote_lid; 907 u8 rsvd0; 908 u8 port; 909 u8 rsvd1[4]; 910 u8 data[256]; 911 }; 912 913 struct mlx5_mad_ifc_mbox_out { 914 struct mlx5_outbox_hdr hdr; 915 u8 rsvd[8]; 916 u8 data[256]; 917 }; 918 919 struct mlx5_access_reg_mbox_in { 920 struct mlx5_inbox_hdr hdr; 921 u8 rsvd0[2]; 922 __be16 register_id; 923 __be32 arg; 924 __be32 data[0]; 925 }; 926 927 struct mlx5_access_reg_mbox_out { 928 struct mlx5_outbox_hdr hdr; 929 u8 rsvd[8]; 930 __be32 data[0]; 931 }; 932 933 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 934 935 enum { 936 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 937 }; 938 939 #endif /* MLX5_DEVICE_H */ 940