1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 58 59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 67 68 /* insert a value to a struct */ 69 #define MLX5_SET(typ, p, fld, v) do { \ 70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 74 << __mlx5_dw_bit_off(typ, fld))); \ 75 } while (0) 76 77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 82 << __mlx5_dw_bit_off(typ, fld))); \ 83 } while (0) 84 85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 87 __mlx5_mask(typ, fld)) 88 89 #define MLX5_GET_PR(typ, p, fld) ({ \ 90 u32 ___t = MLX5_GET(typ, p, fld); \ 91 pr_debug(#fld " = 0x%x\n", ___t); \ 92 ___t; \ 93 }) 94 95 #define MLX5_SET64(typ, p, fld, v) do { \ 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 99 } while (0) 100 101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 102 103 #define MLX5_GET64_PR(typ, p, fld) ({ \ 104 u64 ___t = MLX5_GET64(typ, p, fld); \ 105 pr_debug(#fld " = 0x%llx\n", ___t); \ 106 ___t; \ 107 }) 108 109 /* Big endian getters */ 110 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 111 __mlx5_64_off(typ, fld))) 112 113 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 114 type_t tmp; \ 115 switch (sizeof(tmp)) { \ 116 case sizeof(u8): \ 117 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 118 break; \ 119 case sizeof(u16): \ 120 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 121 break; \ 122 case sizeof(u32): \ 123 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 124 break; \ 125 case sizeof(u64): \ 126 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 127 break; \ 128 } \ 129 tmp; \ 130 }) 131 132 enum mlx5_inline_modes { 133 MLX5_INLINE_MODE_NONE, 134 MLX5_INLINE_MODE_L2, 135 MLX5_INLINE_MODE_IP, 136 MLX5_INLINE_MODE_TCP_UDP, 137 }; 138 139 enum { 140 MLX5_MAX_COMMANDS = 32, 141 MLX5_CMD_DATA_BLOCK_SIZE = 512, 142 MLX5_PCI_CMD_XPORT = 7, 143 MLX5_MKEY_BSF_OCTO_SIZE = 4, 144 MLX5_MAX_PSVS = 4, 145 }; 146 147 enum { 148 MLX5_EXTENDED_UD_AV = 0x80000000, 149 }; 150 151 enum { 152 MLX5_CQ_STATE_ARMED = 9, 153 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 154 MLX5_CQ_STATE_FIRED = 0xa, 155 }; 156 157 enum { 158 MLX5_STAT_RATE_OFFSET = 5, 159 }; 160 161 enum { 162 MLX5_INLINE_SEG = 0x80000000, 163 }; 164 165 enum { 166 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 167 }; 168 169 enum { 170 MLX5_MIN_PKEY_TABLE_SIZE = 128, 171 MLX5_MAX_LOG_PKEY_TABLE = 5, 172 }; 173 174 enum { 175 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 176 }; 177 178 enum { 179 MLX5_PFAULT_SUBTYPE_WQE = 0, 180 MLX5_PFAULT_SUBTYPE_RDMA = 1, 181 }; 182 183 enum { 184 MLX5_PERM_LOCAL_READ = 1 << 2, 185 MLX5_PERM_LOCAL_WRITE = 1 << 3, 186 MLX5_PERM_REMOTE_READ = 1 << 4, 187 MLX5_PERM_REMOTE_WRITE = 1 << 5, 188 MLX5_PERM_ATOMIC = 1 << 6, 189 MLX5_PERM_UMR_EN = 1 << 7, 190 }; 191 192 enum { 193 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 194 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 195 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 196 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 197 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 198 }; 199 200 enum { 201 MLX5_ACCESS_MODE_PA = 0, 202 MLX5_ACCESS_MODE_MTT = 1, 203 MLX5_ACCESS_MODE_KLM = 2 204 }; 205 206 enum { 207 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 208 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 209 MLX5_MKEY_BSF_EN = 1 << 30, 210 MLX5_MKEY_LEN64 = 1 << 31, 211 }; 212 213 enum { 214 MLX5_EN_RD = (u64)1, 215 MLX5_EN_WR = (u64)2 216 }; 217 218 enum { 219 MLX5_BF_REGS_PER_PAGE = 4, 220 MLX5_MAX_UAR_PAGES = 1 << 8, 221 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 222 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 223 }; 224 225 enum { 226 MLX5_MKEY_MASK_LEN = 1ull << 0, 227 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 228 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 229 MLX5_MKEY_MASK_PD = 1ull << 7, 230 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 231 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 232 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 233 MLX5_MKEY_MASK_KEY = 1ull << 13, 234 MLX5_MKEY_MASK_QPN = 1ull << 14, 235 MLX5_MKEY_MASK_LR = 1ull << 17, 236 MLX5_MKEY_MASK_LW = 1ull << 18, 237 MLX5_MKEY_MASK_RR = 1ull << 19, 238 MLX5_MKEY_MASK_RW = 1ull << 20, 239 MLX5_MKEY_MASK_A = 1ull << 21, 240 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 241 MLX5_MKEY_MASK_FREE = 1ull << 29, 242 }; 243 244 enum { 245 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 246 247 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 248 MLX5_UMR_CHECK_FREE = (2 << 5), 249 250 MLX5_UMR_INLINE = (1 << 7), 251 }; 252 253 #define MLX5_UMR_MTT_ALIGNMENT 0x40 254 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 255 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 256 257 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 258 259 enum { 260 MLX5_EVENT_QUEUE_TYPE_QP = 0, 261 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 262 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 263 }; 264 265 enum mlx5_event { 266 MLX5_EVENT_TYPE_COMP = 0x0, 267 268 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 269 MLX5_EVENT_TYPE_COMM_EST = 0x02, 270 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 271 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 272 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 273 274 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 275 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 276 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 277 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 278 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 279 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 280 281 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 282 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 283 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 284 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 285 286 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 287 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 288 289 MLX5_EVENT_TYPE_CMD = 0x0a, 290 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 291 292 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 293 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 294 }; 295 296 enum { 297 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 298 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 299 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 300 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 301 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 302 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 303 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 304 }; 305 306 enum { 307 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 308 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 309 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 310 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 311 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 312 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 313 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 314 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 315 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 316 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 317 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 318 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 319 }; 320 321 enum { 322 MLX5_ROCE_VERSION_1 = 0, 323 MLX5_ROCE_VERSION_2 = 2, 324 }; 325 326 enum { 327 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 328 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 329 }; 330 331 enum { 332 MLX5_ROCE_L3_TYPE_IPV4 = 0, 333 MLX5_ROCE_L3_TYPE_IPV6 = 1, 334 }; 335 336 enum { 337 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 338 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 339 }; 340 341 enum { 342 MLX5_OPCODE_NOP = 0x00, 343 MLX5_OPCODE_SEND_INVAL = 0x01, 344 MLX5_OPCODE_RDMA_WRITE = 0x08, 345 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 346 MLX5_OPCODE_SEND = 0x0a, 347 MLX5_OPCODE_SEND_IMM = 0x0b, 348 MLX5_OPCODE_LSO = 0x0e, 349 MLX5_OPCODE_RDMA_READ = 0x10, 350 MLX5_OPCODE_ATOMIC_CS = 0x11, 351 MLX5_OPCODE_ATOMIC_FA = 0x12, 352 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 353 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 354 MLX5_OPCODE_BIND_MW = 0x18, 355 MLX5_OPCODE_CONFIG_CMD = 0x1f, 356 357 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 358 MLX5_RECV_OPCODE_SEND = 0x01, 359 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 360 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 361 362 MLX5_CQE_OPCODE_ERROR = 0x1e, 363 MLX5_CQE_OPCODE_RESIZE = 0x16, 364 365 MLX5_OPCODE_SET_PSV = 0x20, 366 MLX5_OPCODE_GET_PSV = 0x21, 367 MLX5_OPCODE_CHECK_PSV = 0x22, 368 MLX5_OPCODE_RGET_PSV = 0x26, 369 MLX5_OPCODE_RCHECK_PSV = 0x27, 370 371 MLX5_OPCODE_UMR = 0x25, 372 373 }; 374 375 enum { 376 MLX5_SET_PORT_RESET_QKEY = 0, 377 MLX5_SET_PORT_GUID0 = 16, 378 MLX5_SET_PORT_NODE_GUID = 17, 379 MLX5_SET_PORT_SYS_GUID = 18, 380 MLX5_SET_PORT_GID_TABLE = 19, 381 MLX5_SET_PORT_PKEY_TABLE = 20, 382 }; 383 384 enum { 385 MLX5_BW_NO_LIMIT = 0, 386 MLX5_100_MBPS_UNIT = 3, 387 MLX5_GBPS_UNIT = 4, 388 }; 389 390 enum { 391 MLX5_MAX_PAGE_SHIFT = 31 392 }; 393 394 enum { 395 MLX5_ADAPTER_PAGE_SHIFT = 12, 396 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 397 }; 398 399 enum { 400 MLX5_CAP_OFF_CMDIF_CSUM = 46, 401 }; 402 403 enum { 404 /* 405 * Max wqe size for rdma read is 512 bytes, so this 406 * limits our max_sge_rd as the wqe needs to fit: 407 * - ctrl segment (16 bytes) 408 * - rdma segment (16 bytes) 409 * - scatter elements (16 bytes each) 410 */ 411 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 412 }; 413 414 struct mlx5_inbox_hdr { 415 __be16 opcode; 416 u8 rsvd[4]; 417 __be16 opmod; 418 }; 419 420 struct mlx5_outbox_hdr { 421 u8 status; 422 u8 rsvd[3]; 423 __be32 syndrome; 424 }; 425 426 struct mlx5_cmd_query_adapter_mbox_in { 427 struct mlx5_inbox_hdr hdr; 428 u8 rsvd[8]; 429 }; 430 431 struct mlx5_cmd_query_adapter_mbox_out { 432 struct mlx5_outbox_hdr hdr; 433 u8 rsvd0[24]; 434 u8 intapin; 435 u8 rsvd1[13]; 436 __be16 vsd_vendor_id; 437 u8 vsd[208]; 438 u8 vsd_psid[16]; 439 }; 440 441 enum mlx5_odp_transport_cap_bits { 442 MLX5_ODP_SUPPORT_SEND = 1 << 31, 443 MLX5_ODP_SUPPORT_RECV = 1 << 30, 444 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 445 MLX5_ODP_SUPPORT_READ = 1 << 28, 446 }; 447 448 struct mlx5_odp_caps { 449 char reserved[0x10]; 450 struct { 451 __be32 rc_odp_caps; 452 __be32 uc_odp_caps; 453 __be32 ud_odp_caps; 454 } per_transport_caps; 455 char reserved2[0xe4]; 456 }; 457 458 struct mlx5_cmd_init_hca_mbox_in { 459 struct mlx5_inbox_hdr hdr; 460 u8 rsvd0[2]; 461 __be16 profile; 462 u8 rsvd1[4]; 463 }; 464 465 struct mlx5_cmd_init_hca_mbox_out { 466 struct mlx5_outbox_hdr hdr; 467 u8 rsvd[8]; 468 }; 469 470 struct mlx5_cmd_teardown_hca_mbox_in { 471 struct mlx5_inbox_hdr hdr; 472 u8 rsvd0[2]; 473 __be16 profile; 474 u8 rsvd1[4]; 475 }; 476 477 struct mlx5_cmd_teardown_hca_mbox_out { 478 struct mlx5_outbox_hdr hdr; 479 u8 rsvd[8]; 480 }; 481 482 struct mlx5_cmd_layout { 483 u8 type; 484 u8 rsvd0[3]; 485 __be32 inlen; 486 __be64 in_ptr; 487 __be32 in[4]; 488 __be32 out[4]; 489 __be64 out_ptr; 490 __be32 outlen; 491 u8 token; 492 u8 sig; 493 u8 rsvd1; 494 u8 status_own; 495 }; 496 497 498 struct health_buffer { 499 __be32 assert_var[5]; 500 __be32 rsvd0[3]; 501 __be32 assert_exit_ptr; 502 __be32 assert_callra; 503 __be32 rsvd1[2]; 504 __be32 fw_ver; 505 __be32 hw_id; 506 __be32 rsvd2; 507 u8 irisc_index; 508 u8 synd; 509 __be16 ext_synd; 510 }; 511 512 struct mlx5_init_seg { 513 __be32 fw_rev; 514 __be32 cmdif_rev_fw_sub; 515 __be32 rsvd0[2]; 516 __be32 cmdq_addr_h; 517 __be32 cmdq_addr_l_sz; 518 __be32 cmd_dbell; 519 __be32 rsvd1[120]; 520 __be32 initializing; 521 struct health_buffer health; 522 __be32 rsvd2[880]; 523 __be32 internal_timer_h; 524 __be32 internal_timer_l; 525 __be32 rsvd3[2]; 526 __be32 health_counter; 527 __be32 rsvd4[1019]; 528 __be64 ieee1588_clk; 529 __be32 ieee1588_clk_type; 530 __be32 clr_intx; 531 }; 532 533 struct mlx5_eqe_comp { 534 __be32 reserved[6]; 535 __be32 cqn; 536 }; 537 538 struct mlx5_eqe_qp_srq { 539 __be32 reserved1[5]; 540 u8 type; 541 u8 reserved2[3]; 542 __be32 qp_srq_n; 543 }; 544 545 struct mlx5_eqe_cq_err { 546 __be32 cqn; 547 u8 reserved1[7]; 548 u8 syndrome; 549 }; 550 551 struct mlx5_eqe_port_state { 552 u8 reserved0[8]; 553 u8 port; 554 }; 555 556 struct mlx5_eqe_gpio { 557 __be32 reserved0[2]; 558 __be64 gpio_event; 559 }; 560 561 struct mlx5_eqe_congestion { 562 u8 type; 563 u8 rsvd0; 564 u8 congestion_level; 565 }; 566 567 struct mlx5_eqe_stall_vl { 568 u8 rsvd0[3]; 569 u8 port_vl; 570 }; 571 572 struct mlx5_eqe_cmd { 573 __be32 vector; 574 __be32 rsvd[6]; 575 }; 576 577 struct mlx5_eqe_page_req { 578 u8 rsvd0[2]; 579 __be16 func_id; 580 __be32 num_pages; 581 __be32 rsvd1[5]; 582 }; 583 584 struct mlx5_eqe_page_fault { 585 __be32 bytes_committed; 586 union { 587 struct { 588 u16 reserved1; 589 __be16 wqe_index; 590 u16 reserved2; 591 __be16 packet_length; 592 u8 reserved3[12]; 593 } __packed wqe; 594 struct { 595 __be32 r_key; 596 u16 reserved1; 597 __be16 packet_length; 598 __be32 rdma_op_len; 599 __be64 rdma_va; 600 } __packed rdma; 601 } __packed; 602 __be32 flags_qpn; 603 } __packed; 604 605 struct mlx5_eqe_vport_change { 606 u8 rsvd0[2]; 607 __be16 vport_num; 608 __be32 rsvd1[6]; 609 } __packed; 610 611 union ev_data { 612 __be32 raw[7]; 613 struct mlx5_eqe_cmd cmd; 614 struct mlx5_eqe_comp comp; 615 struct mlx5_eqe_qp_srq qp_srq; 616 struct mlx5_eqe_cq_err cq_err; 617 struct mlx5_eqe_port_state port; 618 struct mlx5_eqe_gpio gpio; 619 struct mlx5_eqe_congestion cong; 620 struct mlx5_eqe_stall_vl stall_vl; 621 struct mlx5_eqe_page_req req_pages; 622 struct mlx5_eqe_page_fault page_fault; 623 struct mlx5_eqe_vport_change vport_change; 624 } __packed; 625 626 struct mlx5_eqe { 627 u8 rsvd0; 628 u8 type; 629 u8 rsvd1; 630 u8 sub_type; 631 __be32 rsvd2[7]; 632 union ev_data data; 633 __be16 rsvd3; 634 u8 signature; 635 u8 owner; 636 } __packed; 637 638 struct mlx5_cmd_prot_block { 639 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 640 u8 rsvd0[48]; 641 __be64 next; 642 __be32 block_num; 643 u8 rsvd1; 644 u8 token; 645 u8 ctrl_sig; 646 u8 sig; 647 }; 648 649 enum { 650 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 651 }; 652 653 struct mlx5_err_cqe { 654 u8 rsvd0[32]; 655 __be32 srqn; 656 u8 rsvd1[18]; 657 u8 vendor_err_synd; 658 u8 syndrome; 659 __be32 s_wqe_opcode_qpn; 660 __be16 wqe_counter; 661 u8 signature; 662 u8 op_own; 663 }; 664 665 struct mlx5_cqe64 { 666 u8 outer_l3_tunneled; 667 u8 rsvd0; 668 __be16 wqe_id; 669 u8 lro_tcppsh_abort_dupack; 670 u8 lro_min_ttl; 671 __be16 lro_tcp_win; 672 __be32 lro_ack_seq_num; 673 __be32 rss_hash_result; 674 u8 rss_hash_type; 675 u8 ml_path; 676 u8 rsvd20[2]; 677 __be16 check_sum; 678 __be16 slid; 679 __be32 flags_rqpn; 680 u8 hds_ip_ext; 681 u8 l4_l3_hdr_type; 682 __be16 vlan_info; 683 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 684 __be32 imm_inval_pkey; 685 u8 rsvd40[4]; 686 __be32 byte_cnt; 687 __be32 timestamp_h; 688 __be32 timestamp_l; 689 __be32 sop_drop_qpn; 690 __be16 wqe_counter; 691 u8 signature; 692 u8 op_own; 693 }; 694 695 struct mlx5_mini_cqe8 { 696 union { 697 __be32 rx_hash_result; 698 struct { 699 __be16 checksum; 700 __be16 rsvd; 701 }; 702 struct { 703 __be16 wqe_counter; 704 u8 s_wqe_opcode; 705 u8 reserved; 706 } s_wqe_info; 707 }; 708 __be32 byte_cnt; 709 }; 710 711 enum { 712 MLX5_NO_INLINE_DATA, 713 MLX5_INLINE_DATA32_SEG, 714 MLX5_INLINE_DATA64_SEG, 715 MLX5_COMPRESSED, 716 }; 717 718 enum { 719 MLX5_CQE_FORMAT_CSUM = 0x1, 720 }; 721 722 #define MLX5_MINI_CQE_ARRAY_SIZE 8 723 724 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 725 { 726 return (cqe->op_own >> 2) & 0x3; 727 } 728 729 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 730 { 731 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 732 } 733 734 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 735 { 736 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 737 } 738 739 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 740 { 741 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 742 } 743 744 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe) 745 { 746 return cqe->outer_l3_tunneled & 0x1; 747 } 748 749 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) 750 { 751 return !!(cqe->l4_l3_hdr_type & 0x1); 752 } 753 754 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 755 { 756 u32 hi, lo; 757 758 hi = be32_to_cpu(cqe->timestamp_h); 759 lo = be32_to_cpu(cqe->timestamp_l); 760 761 return (u64)lo | ((u64)hi << 32); 762 } 763 764 struct mpwrq_cqe_bc { 765 __be16 filler_consumed_strides; 766 __be16 byte_cnt; 767 }; 768 769 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 770 { 771 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 772 773 return be16_to_cpu(bc->byte_cnt); 774 } 775 776 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 777 { 778 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 779 } 780 781 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 782 { 783 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 784 785 return mpwrq_get_cqe_bc_consumed_strides(bc); 786 } 787 788 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 789 { 790 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 791 792 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 793 } 794 795 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 796 { 797 return be16_to_cpu(cqe->wqe_counter); 798 } 799 800 enum { 801 CQE_L4_HDR_TYPE_NONE = 0x0, 802 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 803 CQE_L4_HDR_TYPE_UDP = 0x2, 804 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 805 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 806 }; 807 808 enum { 809 CQE_RSS_HTYPE_IP = 0x3 << 6, 810 CQE_RSS_HTYPE_L4 = 0x3 << 2, 811 }; 812 813 enum { 814 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 815 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 816 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 817 }; 818 819 enum { 820 CQE_L2_OK = 1 << 0, 821 CQE_L3_OK = 1 << 1, 822 CQE_L4_OK = 1 << 2, 823 }; 824 825 struct mlx5_sig_err_cqe { 826 u8 rsvd0[16]; 827 __be32 expected_trans_sig; 828 __be32 actual_trans_sig; 829 __be32 expected_reftag; 830 __be32 actual_reftag; 831 __be16 syndrome; 832 u8 rsvd22[2]; 833 __be32 mkey; 834 __be64 err_offset; 835 u8 rsvd30[8]; 836 __be32 qpn; 837 u8 rsvd38[2]; 838 u8 signature; 839 u8 op_own; 840 }; 841 842 struct mlx5_wqe_srq_next_seg { 843 u8 rsvd0[2]; 844 __be16 next_wqe_index; 845 u8 signature; 846 u8 rsvd1[11]; 847 }; 848 849 union mlx5_ext_cqe { 850 struct ib_grh grh; 851 u8 inl[64]; 852 }; 853 854 struct mlx5_cqe128 { 855 union mlx5_ext_cqe inl_grh; 856 struct mlx5_cqe64 cqe64; 857 }; 858 859 struct mlx5_srq_ctx { 860 u8 state_log_sz; 861 u8 rsvd0[3]; 862 __be32 flags_xrcd; 863 __be32 pgoff_cqn; 864 u8 rsvd1[4]; 865 u8 log_pg_sz; 866 u8 rsvd2[7]; 867 __be32 pd; 868 __be16 lwm; 869 __be16 wqe_cnt; 870 u8 rsvd3[8]; 871 __be64 db_record; 872 }; 873 874 struct mlx5_create_srq_mbox_in { 875 struct mlx5_inbox_hdr hdr; 876 __be32 input_srqn; 877 u8 rsvd0[4]; 878 struct mlx5_srq_ctx ctx; 879 u8 rsvd1[208]; 880 __be64 pas[0]; 881 }; 882 883 struct mlx5_create_srq_mbox_out { 884 struct mlx5_outbox_hdr hdr; 885 __be32 srqn; 886 u8 rsvd[4]; 887 }; 888 889 struct mlx5_destroy_srq_mbox_in { 890 struct mlx5_inbox_hdr hdr; 891 __be32 srqn; 892 u8 rsvd[4]; 893 }; 894 895 struct mlx5_destroy_srq_mbox_out { 896 struct mlx5_outbox_hdr hdr; 897 u8 rsvd[8]; 898 }; 899 900 struct mlx5_query_srq_mbox_in { 901 struct mlx5_inbox_hdr hdr; 902 __be32 srqn; 903 u8 rsvd0[4]; 904 }; 905 906 struct mlx5_query_srq_mbox_out { 907 struct mlx5_outbox_hdr hdr; 908 u8 rsvd0[8]; 909 struct mlx5_srq_ctx ctx; 910 u8 rsvd1[32]; 911 __be64 pas[0]; 912 }; 913 914 struct mlx5_arm_srq_mbox_in { 915 struct mlx5_inbox_hdr hdr; 916 __be32 srqn; 917 __be16 rsvd; 918 __be16 lwm; 919 }; 920 921 struct mlx5_arm_srq_mbox_out { 922 struct mlx5_outbox_hdr hdr; 923 u8 rsvd[8]; 924 }; 925 926 struct mlx5_cq_context { 927 u8 status; 928 u8 cqe_sz_flags; 929 u8 st; 930 u8 rsvd3; 931 u8 rsvd4[6]; 932 __be16 page_offset; 933 __be32 log_sz_usr_page; 934 __be16 cq_period; 935 __be16 cq_max_count; 936 __be16 rsvd20; 937 __be16 c_eqn; 938 u8 log_pg_sz; 939 u8 rsvd25[7]; 940 __be32 last_notified_index; 941 __be32 solicit_producer_index; 942 __be32 consumer_counter; 943 __be32 producer_counter; 944 u8 rsvd48[8]; 945 __be64 db_record_addr; 946 }; 947 948 struct mlx5_create_cq_mbox_in { 949 struct mlx5_inbox_hdr hdr; 950 __be32 input_cqn; 951 u8 rsvdx[4]; 952 struct mlx5_cq_context ctx; 953 u8 rsvd6[192]; 954 __be64 pas[0]; 955 }; 956 957 struct mlx5_create_cq_mbox_out { 958 struct mlx5_outbox_hdr hdr; 959 __be32 cqn; 960 u8 rsvd0[4]; 961 }; 962 963 struct mlx5_destroy_cq_mbox_in { 964 struct mlx5_inbox_hdr hdr; 965 __be32 cqn; 966 u8 rsvd0[4]; 967 }; 968 969 struct mlx5_destroy_cq_mbox_out { 970 struct mlx5_outbox_hdr hdr; 971 u8 rsvd0[8]; 972 }; 973 974 struct mlx5_query_cq_mbox_in { 975 struct mlx5_inbox_hdr hdr; 976 __be32 cqn; 977 u8 rsvd0[4]; 978 }; 979 980 struct mlx5_query_cq_mbox_out { 981 struct mlx5_outbox_hdr hdr; 982 u8 rsvd0[8]; 983 struct mlx5_cq_context ctx; 984 u8 rsvd6[16]; 985 __be64 pas[0]; 986 }; 987 988 struct mlx5_modify_cq_mbox_in { 989 struct mlx5_inbox_hdr hdr; 990 __be32 cqn; 991 __be32 field_select; 992 struct mlx5_cq_context ctx; 993 u8 rsvd[192]; 994 __be64 pas[0]; 995 }; 996 997 struct mlx5_modify_cq_mbox_out { 998 struct mlx5_outbox_hdr hdr; 999 u8 rsvd[8]; 1000 }; 1001 1002 struct mlx5_enable_hca_mbox_in { 1003 struct mlx5_inbox_hdr hdr; 1004 u8 rsvd[8]; 1005 }; 1006 1007 struct mlx5_enable_hca_mbox_out { 1008 struct mlx5_outbox_hdr hdr; 1009 u8 rsvd[8]; 1010 }; 1011 1012 struct mlx5_disable_hca_mbox_in { 1013 struct mlx5_inbox_hdr hdr; 1014 u8 rsvd[8]; 1015 }; 1016 1017 struct mlx5_disable_hca_mbox_out { 1018 struct mlx5_outbox_hdr hdr; 1019 u8 rsvd[8]; 1020 }; 1021 1022 struct mlx5_eq_context { 1023 u8 status; 1024 u8 ec_oi; 1025 u8 st; 1026 u8 rsvd2[7]; 1027 __be16 page_pffset; 1028 __be32 log_sz_usr_page; 1029 u8 rsvd3[7]; 1030 u8 intr; 1031 u8 log_page_size; 1032 u8 rsvd4[15]; 1033 __be32 consumer_counter; 1034 __be32 produser_counter; 1035 u8 rsvd5[16]; 1036 }; 1037 1038 struct mlx5_create_eq_mbox_in { 1039 struct mlx5_inbox_hdr hdr; 1040 u8 rsvd0[3]; 1041 u8 input_eqn; 1042 u8 rsvd1[4]; 1043 struct mlx5_eq_context ctx; 1044 u8 rsvd2[8]; 1045 __be64 events_mask; 1046 u8 rsvd3[176]; 1047 __be64 pas[0]; 1048 }; 1049 1050 struct mlx5_create_eq_mbox_out { 1051 struct mlx5_outbox_hdr hdr; 1052 u8 rsvd0[3]; 1053 u8 eq_number; 1054 u8 rsvd1[4]; 1055 }; 1056 1057 struct mlx5_destroy_eq_mbox_in { 1058 struct mlx5_inbox_hdr hdr; 1059 u8 rsvd0[3]; 1060 u8 eqn; 1061 u8 rsvd1[4]; 1062 }; 1063 1064 struct mlx5_destroy_eq_mbox_out { 1065 struct mlx5_outbox_hdr hdr; 1066 u8 rsvd[8]; 1067 }; 1068 1069 struct mlx5_map_eq_mbox_in { 1070 struct mlx5_inbox_hdr hdr; 1071 __be64 mask; 1072 u8 mu; 1073 u8 rsvd0[2]; 1074 u8 eqn; 1075 u8 rsvd1[24]; 1076 }; 1077 1078 struct mlx5_map_eq_mbox_out { 1079 struct mlx5_outbox_hdr hdr; 1080 u8 rsvd[8]; 1081 }; 1082 1083 struct mlx5_query_eq_mbox_in { 1084 struct mlx5_inbox_hdr hdr; 1085 u8 rsvd0[3]; 1086 u8 eqn; 1087 u8 rsvd1[4]; 1088 }; 1089 1090 struct mlx5_query_eq_mbox_out { 1091 struct mlx5_outbox_hdr hdr; 1092 u8 rsvd[8]; 1093 struct mlx5_eq_context ctx; 1094 }; 1095 1096 enum { 1097 MLX5_MKEY_STATUS_FREE = 1 << 6, 1098 }; 1099 1100 struct mlx5_mkey_seg { 1101 /* This is a two bit field occupying bits 31-30. 1102 * bit 31 is always 0, 1103 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 1104 */ 1105 u8 status; 1106 u8 pcie_control; 1107 u8 flags; 1108 u8 version; 1109 __be32 qpn_mkey7_0; 1110 u8 rsvd1[4]; 1111 __be32 flags_pd; 1112 __be64 start_addr; 1113 __be64 len; 1114 __be32 bsfs_octo_size; 1115 u8 rsvd2[16]; 1116 __be32 xlt_oct_size; 1117 u8 rsvd3[3]; 1118 u8 log2_page_size; 1119 u8 rsvd4[4]; 1120 }; 1121 1122 struct mlx5_query_special_ctxs_mbox_in { 1123 struct mlx5_inbox_hdr hdr; 1124 u8 rsvd[8]; 1125 }; 1126 1127 struct mlx5_query_special_ctxs_mbox_out { 1128 struct mlx5_outbox_hdr hdr; 1129 __be32 dump_fill_mkey; 1130 __be32 reserved_lkey; 1131 }; 1132 1133 struct mlx5_create_mkey_mbox_in { 1134 struct mlx5_inbox_hdr hdr; 1135 __be32 input_mkey_index; 1136 __be32 flags; 1137 struct mlx5_mkey_seg seg; 1138 u8 rsvd1[16]; 1139 __be32 xlat_oct_act_size; 1140 __be32 rsvd2; 1141 u8 rsvd3[168]; 1142 __be64 pas[0]; 1143 }; 1144 1145 struct mlx5_create_mkey_mbox_out { 1146 struct mlx5_outbox_hdr hdr; 1147 __be32 mkey; 1148 u8 rsvd[4]; 1149 }; 1150 1151 struct mlx5_destroy_mkey_mbox_in { 1152 struct mlx5_inbox_hdr hdr; 1153 __be32 mkey; 1154 u8 rsvd[4]; 1155 }; 1156 1157 struct mlx5_destroy_mkey_mbox_out { 1158 struct mlx5_outbox_hdr hdr; 1159 u8 rsvd[8]; 1160 }; 1161 1162 struct mlx5_query_mkey_mbox_in { 1163 struct mlx5_inbox_hdr hdr; 1164 __be32 mkey; 1165 }; 1166 1167 struct mlx5_query_mkey_mbox_out { 1168 struct mlx5_outbox_hdr hdr; 1169 __be64 pas[0]; 1170 }; 1171 1172 struct mlx5_modify_mkey_mbox_in { 1173 struct mlx5_inbox_hdr hdr; 1174 __be32 mkey; 1175 __be64 pas[0]; 1176 }; 1177 1178 struct mlx5_modify_mkey_mbox_out { 1179 struct mlx5_outbox_hdr hdr; 1180 u8 rsvd[8]; 1181 }; 1182 1183 struct mlx5_dump_mkey_mbox_in { 1184 struct mlx5_inbox_hdr hdr; 1185 }; 1186 1187 struct mlx5_dump_mkey_mbox_out { 1188 struct mlx5_outbox_hdr hdr; 1189 __be32 mkey; 1190 }; 1191 1192 struct mlx5_mad_ifc_mbox_in { 1193 struct mlx5_inbox_hdr hdr; 1194 __be16 remote_lid; 1195 u8 rsvd0; 1196 u8 port; 1197 u8 rsvd1[4]; 1198 u8 data[256]; 1199 }; 1200 1201 struct mlx5_mad_ifc_mbox_out { 1202 struct mlx5_outbox_hdr hdr; 1203 u8 rsvd[8]; 1204 u8 data[256]; 1205 }; 1206 1207 struct mlx5_access_reg_mbox_in { 1208 struct mlx5_inbox_hdr hdr; 1209 u8 rsvd0[2]; 1210 __be16 register_id; 1211 __be32 arg; 1212 __be32 data[0]; 1213 }; 1214 1215 struct mlx5_access_reg_mbox_out { 1216 struct mlx5_outbox_hdr hdr; 1217 u8 rsvd[8]; 1218 __be32 data[0]; 1219 }; 1220 1221 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1222 1223 enum { 1224 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1225 }; 1226 1227 struct mlx5_allocate_psv_in { 1228 struct mlx5_inbox_hdr hdr; 1229 __be32 npsv_pd; 1230 __be32 rsvd_psv0; 1231 }; 1232 1233 struct mlx5_allocate_psv_out { 1234 struct mlx5_outbox_hdr hdr; 1235 u8 rsvd[8]; 1236 __be32 psv_idx[4]; 1237 }; 1238 1239 struct mlx5_destroy_psv_in { 1240 struct mlx5_inbox_hdr hdr; 1241 __be32 psv_number; 1242 u8 rsvd[4]; 1243 }; 1244 1245 struct mlx5_destroy_psv_out { 1246 struct mlx5_outbox_hdr hdr; 1247 u8 rsvd[8]; 1248 }; 1249 1250 enum { 1251 VPORT_STATE_DOWN = 0x0, 1252 VPORT_STATE_UP = 0x1, 1253 }; 1254 1255 enum { 1256 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 1257 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 1258 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 1259 }; 1260 1261 enum { 1262 MLX5_L3_PROT_TYPE_IPV4 = 0, 1263 MLX5_L3_PROT_TYPE_IPV6 = 1, 1264 }; 1265 1266 enum { 1267 MLX5_L4_PROT_TYPE_TCP = 0, 1268 MLX5_L4_PROT_TYPE_UDP = 1, 1269 }; 1270 1271 enum { 1272 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1273 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1274 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1275 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1276 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1277 }; 1278 1279 enum { 1280 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1281 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1282 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1283 1284 }; 1285 1286 enum { 1287 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1288 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1289 }; 1290 1291 enum { 1292 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1293 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1294 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1295 }; 1296 1297 enum mlx5_list_type { 1298 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1299 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1300 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1301 }; 1302 1303 enum { 1304 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1305 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1306 }; 1307 1308 enum mlx5_wol_mode { 1309 MLX5_WOL_DISABLE = 0, 1310 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1311 MLX5_WOL_MAGIC = 1 << 2, 1312 MLX5_WOL_ARP = 1 << 3, 1313 MLX5_WOL_BROADCAST = 1 << 4, 1314 MLX5_WOL_MULTICAST = 1 << 5, 1315 MLX5_WOL_UNICAST = 1 << 6, 1316 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1317 }; 1318 1319 /* MLX5 DEV CAPs */ 1320 1321 /* TODO: EAT.ME */ 1322 enum mlx5_cap_mode { 1323 HCA_CAP_OPMOD_GET_MAX = 0, 1324 HCA_CAP_OPMOD_GET_CUR = 1, 1325 }; 1326 1327 enum mlx5_cap_type { 1328 MLX5_CAP_GENERAL = 0, 1329 MLX5_CAP_ETHERNET_OFFLOADS, 1330 MLX5_CAP_ODP, 1331 MLX5_CAP_ATOMIC, 1332 MLX5_CAP_ROCE, 1333 MLX5_CAP_IPOIB_OFFLOADS, 1334 MLX5_CAP_EOIB_OFFLOADS, 1335 MLX5_CAP_FLOW_TABLE, 1336 MLX5_CAP_ESWITCH_FLOW_TABLE, 1337 MLX5_CAP_ESWITCH, 1338 MLX5_CAP_RESERVED, 1339 MLX5_CAP_VECTOR_CALC, 1340 MLX5_CAP_QOS, 1341 /* NUM OF CAP Types */ 1342 MLX5_CAP_NUM 1343 }; 1344 1345 /* GET Dev Caps macros */ 1346 #define MLX5_CAP_GEN(mdev, cap) \ 1347 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1348 1349 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1350 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1351 1352 #define MLX5_CAP_ETH(mdev, cap) \ 1353 MLX5_GET(per_protocol_networking_offload_caps,\ 1354 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1355 1356 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1357 MLX5_GET(per_protocol_networking_offload_caps,\ 1358 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1359 1360 #define MLX5_CAP_ROCE(mdev, cap) \ 1361 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1362 1363 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1364 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1365 1366 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1367 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1368 1369 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1370 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1371 1372 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1373 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1374 1375 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1376 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1377 1378 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1379 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1380 1381 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1382 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1383 1384 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1385 MLX5_GET(flow_table_eswitch_cap, \ 1386 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1387 1388 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1389 MLX5_GET(flow_table_eswitch_cap, \ 1390 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1391 1392 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1393 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1394 1395 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1396 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1397 1398 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1399 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1400 1401 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1402 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1403 1404 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1405 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1406 1407 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1408 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1409 1410 #define MLX5_CAP_ESW(mdev, cap) \ 1411 MLX5_GET(e_switch_cap, \ 1412 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1413 1414 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1415 MLX5_GET(e_switch_cap, \ 1416 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1417 1418 #define MLX5_CAP_ODP(mdev, cap)\ 1419 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1420 1421 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1422 MLX5_GET(vector_calc_cap, \ 1423 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap) 1424 1425 #define MLX5_CAP_QOS(mdev, cap)\ 1426 MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1427 1428 enum { 1429 MLX5_CMD_STAT_OK = 0x0, 1430 MLX5_CMD_STAT_INT_ERR = 0x1, 1431 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1432 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1433 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1434 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1435 MLX5_CMD_STAT_RES_BUSY = 0x6, 1436 MLX5_CMD_STAT_LIM_ERR = 0x8, 1437 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1438 MLX5_CMD_STAT_IX_ERR = 0xa, 1439 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1440 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1441 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1442 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1443 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1444 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1445 }; 1446 1447 enum { 1448 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1449 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1450 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1451 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1452 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1453 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1454 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1455 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1456 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1457 }; 1458 1459 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1460 { 1461 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1462 return 0; 1463 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1464 } 1465 1466 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 1467 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 1468 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1469 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1470 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1471 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1472 1473 #endif /* MLX5_DEVICE_H */ 1474