1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 u32 _v = v; \ 75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ 83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ 84 MLX5_SET(typ, p, fld[idx], v); \ 85 } while (0) 86 87 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 92 << __mlx5_dw_bit_off(typ, fld))); \ 93 } while (0) 94 95 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 96 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 97 __mlx5_mask(typ, fld)) 98 99 #define MLX5_GET_PR(typ, p, fld) ({ \ 100 u32 ___t = MLX5_GET(typ, p, fld); \ 101 pr_debug(#fld " = 0x%x\n", ___t); \ 102 ___t; \ 103 }) 104 105 #define __MLX5_SET64(typ, p, fld, v) do { \ 106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 108 } while (0) 109 110 #define MLX5_SET64(typ, p, fld, v) do { \ 111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 112 __MLX5_SET64(typ, p, fld, v); \ 113 } while (0) 114 115 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 117 __MLX5_SET64(typ, p, fld[idx], v); \ 118 } while (0) 119 120 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 121 122 #define MLX5_GET64_PR(typ, p, fld) ({ \ 123 u64 ___t = MLX5_GET64(typ, p, fld); \ 124 pr_debug(#fld " = 0x%llx\n", ___t); \ 125 ___t; \ 126 }) 127 128 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 129 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 130 __mlx5_mask16(typ, fld)) 131 132 #define MLX5_SET16(typ, p, fld, v) do { \ 133 u16 _v = v; \ 134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 138 << __mlx5_16_bit_off(typ, fld))); \ 139 } while (0) 140 141 /* Big endian getters */ 142 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 143 __mlx5_64_off(typ, fld))) 144 145 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 146 type_t tmp; \ 147 switch (sizeof(tmp)) { \ 148 case sizeof(u8): \ 149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 150 break; \ 151 case sizeof(u16): \ 152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 153 break; \ 154 case sizeof(u32): \ 155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 156 break; \ 157 case sizeof(u64): \ 158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 159 break; \ 160 } \ 161 tmp; \ 162 }) 163 164 enum mlx5_inline_modes { 165 MLX5_INLINE_MODE_NONE, 166 MLX5_INLINE_MODE_L2, 167 MLX5_INLINE_MODE_IP, 168 MLX5_INLINE_MODE_TCP_UDP, 169 }; 170 171 enum { 172 MLX5_MAX_COMMANDS = 32, 173 MLX5_CMD_DATA_BLOCK_SIZE = 512, 174 MLX5_PCI_CMD_XPORT = 7, 175 MLX5_MKEY_BSF_OCTO_SIZE = 4, 176 MLX5_MAX_PSVS = 4, 177 }; 178 179 enum { 180 MLX5_EXTENDED_UD_AV = 0x80000000, 181 }; 182 183 enum { 184 MLX5_CQ_STATE_ARMED = 9, 185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 186 MLX5_CQ_STATE_FIRED = 0xa, 187 }; 188 189 enum { 190 MLX5_STAT_RATE_OFFSET = 5, 191 }; 192 193 enum { 194 MLX5_INLINE_SEG = 0x80000000, 195 }; 196 197 enum { 198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 199 }; 200 201 enum { 202 MLX5_MIN_PKEY_TABLE_SIZE = 128, 203 MLX5_MAX_LOG_PKEY_TABLE = 5, 204 }; 205 206 enum { 207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 208 }; 209 210 enum { 211 MLX5_PFAULT_SUBTYPE_WQE = 0, 212 MLX5_PFAULT_SUBTYPE_RDMA = 1, 213 }; 214 215 enum wqe_page_fault_type { 216 MLX5_WQE_PF_TYPE_RMP = 0, 217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, 218 MLX5_WQE_PF_TYPE_RESP = 2, 219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, 220 }; 221 222 enum { 223 MLX5_PERM_LOCAL_READ = 1 << 2, 224 MLX5_PERM_LOCAL_WRITE = 1 << 3, 225 MLX5_PERM_REMOTE_READ = 1 << 4, 226 MLX5_PERM_REMOTE_WRITE = 1 << 5, 227 MLX5_PERM_ATOMIC = 1 << 6, 228 MLX5_PERM_UMR_EN = 1 << 7, 229 }; 230 231 enum { 232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 237 }; 238 239 enum { 240 MLX5_EN_RD = (u64)1, 241 MLX5_EN_WR = (u64)2 242 }; 243 244 enum { 245 MLX5_ADAPTER_PAGE_SHIFT = 12, 246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 247 }; 248 249 enum { 250 MLX5_BFREGS_PER_UAR = 4, 251 MLX5_MAX_UARS = 1 << 8, 252 MLX5_NON_FP_BFREGS_PER_UAR = 2, 253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 254 MLX5_NON_FP_BFREGS_PER_UAR, 255 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 256 MLX5_NON_FP_BFREGS_PER_UAR, 257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 259 MLX5_MIN_DYN_BFREGS = 512, 260 MLX5_MAX_DYN_BFREGS = 1024, 261 }; 262 263 enum { 264 MLX5_MKEY_MASK_LEN = 1ull << 0, 265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 267 MLX5_MKEY_MASK_PD = 1ull << 7, 268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 271 MLX5_MKEY_MASK_KEY = 1ull << 13, 272 MLX5_MKEY_MASK_QPN = 1ull << 14, 273 MLX5_MKEY_MASK_LR = 1ull << 17, 274 MLX5_MKEY_MASK_LW = 1ull << 18, 275 MLX5_MKEY_MASK_RR = 1ull << 19, 276 MLX5_MKEY_MASK_RW = 1ull << 20, 277 MLX5_MKEY_MASK_A = 1ull << 21, 278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 279 MLX5_MKEY_MASK_FREE = 1ull << 29, 280 }; 281 282 enum { 283 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 284 285 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 286 MLX5_UMR_CHECK_FREE = (2 << 5), 287 288 MLX5_UMR_INLINE = (1 << 7), 289 }; 290 291 #define MLX5_UMR_MTT_ALIGNMENT 0x40 292 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 293 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 294 295 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 296 297 enum { 298 MLX5_EVENT_QUEUE_TYPE_QP = 0, 299 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 300 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 301 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 302 }; 303 304 /* mlx5 components can subscribe to any one of these events via 305 * mlx5_eq_notifier_register API. 306 */ 307 enum mlx5_event { 308 /* Special value to subscribe to any event */ 309 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 310 /* HW events enum start: comp events are not subscribable */ 311 MLX5_EVENT_TYPE_COMP = 0x0, 312 /* HW Async events enum start: subscribable events */ 313 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 314 MLX5_EVENT_TYPE_COMM_EST = 0x02, 315 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 316 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 317 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 318 319 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 320 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 321 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 322 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 323 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 324 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 325 326 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 327 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 328 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 329 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 330 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 331 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 332 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, 333 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, 334 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 335 336 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 337 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 338 339 MLX5_EVENT_TYPE_CMD = 0x0a, 340 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 341 342 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 343 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 344 345 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, 346 347 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 348 349 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 350 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 351 352 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, 353 354 MLX5_EVENT_TYPE_MAX = MLX5_EVENT_TYPE_DEVICE_TRACER + 1, 355 }; 356 357 enum { 358 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, 359 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, 360 }; 361 362 enum { 363 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 364 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 365 }; 366 367 enum { 368 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 369 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 370 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 371 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 372 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 373 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 374 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 375 }; 376 377 enum { 378 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 379 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 380 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 381 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 382 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 383 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 384 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 385 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 386 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 387 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 388 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 389 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 390 }; 391 392 enum { 393 MLX5_ROCE_VERSION_1 = 0, 394 MLX5_ROCE_VERSION_2 = 2, 395 }; 396 397 enum { 398 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 399 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 400 }; 401 402 enum { 403 MLX5_ROCE_L3_TYPE_IPV4 = 0, 404 MLX5_ROCE_L3_TYPE_IPV6 = 1, 405 }; 406 407 enum { 408 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 409 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 410 }; 411 412 enum { 413 MLX5_OPCODE_NOP = 0x00, 414 MLX5_OPCODE_SEND_INVAL = 0x01, 415 MLX5_OPCODE_RDMA_WRITE = 0x08, 416 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 417 MLX5_OPCODE_SEND = 0x0a, 418 MLX5_OPCODE_SEND_IMM = 0x0b, 419 MLX5_OPCODE_LSO = 0x0e, 420 MLX5_OPCODE_RDMA_READ = 0x10, 421 MLX5_OPCODE_ATOMIC_CS = 0x11, 422 MLX5_OPCODE_ATOMIC_FA = 0x12, 423 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 424 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 425 MLX5_OPCODE_BIND_MW = 0x18, 426 MLX5_OPCODE_CONFIG_CMD = 0x1f, 427 MLX5_OPCODE_ENHANCED_MPSW = 0x29, 428 429 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 430 MLX5_RECV_OPCODE_SEND = 0x01, 431 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 432 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 433 434 MLX5_CQE_OPCODE_ERROR = 0x1e, 435 MLX5_CQE_OPCODE_RESIZE = 0x16, 436 437 MLX5_OPCODE_SET_PSV = 0x20, 438 MLX5_OPCODE_GET_PSV = 0x21, 439 MLX5_OPCODE_CHECK_PSV = 0x22, 440 MLX5_OPCODE_RGET_PSV = 0x26, 441 MLX5_OPCODE_RCHECK_PSV = 0x27, 442 443 MLX5_OPCODE_UMR = 0x25, 444 445 }; 446 447 enum { 448 MLX5_SET_PORT_RESET_QKEY = 0, 449 MLX5_SET_PORT_GUID0 = 16, 450 MLX5_SET_PORT_NODE_GUID = 17, 451 MLX5_SET_PORT_SYS_GUID = 18, 452 MLX5_SET_PORT_GID_TABLE = 19, 453 MLX5_SET_PORT_PKEY_TABLE = 20, 454 }; 455 456 enum { 457 MLX5_BW_NO_LIMIT = 0, 458 MLX5_100_MBPS_UNIT = 3, 459 MLX5_GBPS_UNIT = 4, 460 }; 461 462 enum { 463 MLX5_MAX_PAGE_SHIFT = 31 464 }; 465 466 enum { 467 MLX5_CAP_OFF_CMDIF_CSUM = 46, 468 }; 469 470 enum { 471 /* 472 * Max wqe size for rdma read is 512 bytes, so this 473 * limits our max_sge_rd as the wqe needs to fit: 474 * - ctrl segment (16 bytes) 475 * - rdma segment (16 bytes) 476 * - scatter elements (16 bytes each) 477 */ 478 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 479 }; 480 481 enum mlx5_odp_transport_cap_bits { 482 MLX5_ODP_SUPPORT_SEND = 1 << 31, 483 MLX5_ODP_SUPPORT_RECV = 1 << 30, 484 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 485 MLX5_ODP_SUPPORT_READ = 1 << 28, 486 }; 487 488 struct mlx5_odp_caps { 489 char reserved[0x10]; 490 struct { 491 __be32 rc_odp_caps; 492 __be32 uc_odp_caps; 493 __be32 ud_odp_caps; 494 } per_transport_caps; 495 char reserved2[0xe4]; 496 }; 497 498 struct mlx5_cmd_layout { 499 u8 type; 500 u8 rsvd0[3]; 501 __be32 inlen; 502 __be64 in_ptr; 503 __be32 in[4]; 504 __be32 out[4]; 505 __be64 out_ptr; 506 __be32 outlen; 507 u8 token; 508 u8 sig; 509 u8 rsvd1; 510 u8 status_own; 511 }; 512 513 enum mlx5_fatal_assert_bit_offsets { 514 MLX5_RFR_OFFSET = 31, 515 }; 516 517 struct health_buffer { 518 __be32 assert_var[5]; 519 __be32 rsvd0[3]; 520 __be32 assert_exit_ptr; 521 __be32 assert_callra; 522 __be32 rsvd1[2]; 523 __be32 fw_ver; 524 __be32 hw_id; 525 __be32 rfr; 526 u8 irisc_index; 527 u8 synd; 528 __be16 ext_synd; 529 }; 530 531 enum mlx5_initializing_bit_offsets { 532 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 533 }; 534 535 enum mlx5_cmd_addr_l_sz_offset { 536 MLX5_NIC_IFC_OFFSET = 8, 537 }; 538 539 struct mlx5_init_seg { 540 __be32 fw_rev; 541 __be32 cmdif_rev_fw_sub; 542 __be32 rsvd0[2]; 543 __be32 cmdq_addr_h; 544 __be32 cmdq_addr_l_sz; 545 __be32 cmd_dbell; 546 __be32 rsvd1[120]; 547 __be32 initializing; 548 struct health_buffer health; 549 __be32 rsvd2[880]; 550 __be32 internal_timer_h; 551 __be32 internal_timer_l; 552 __be32 rsvd3[2]; 553 __be32 health_counter; 554 __be32 rsvd4[1019]; 555 __be64 ieee1588_clk; 556 __be32 ieee1588_clk_type; 557 __be32 clr_intx; 558 }; 559 560 struct mlx5_eqe_comp { 561 __be32 reserved[6]; 562 __be32 cqn; 563 }; 564 565 struct mlx5_eqe_qp_srq { 566 __be32 reserved1[5]; 567 u8 type; 568 u8 reserved2[3]; 569 __be32 qp_srq_n; 570 }; 571 572 struct mlx5_eqe_cq_err { 573 __be32 cqn; 574 u8 reserved1[7]; 575 u8 syndrome; 576 }; 577 578 struct mlx5_eqe_port_state { 579 u8 reserved0[8]; 580 u8 port; 581 }; 582 583 struct mlx5_eqe_gpio { 584 __be32 reserved0[2]; 585 __be64 gpio_event; 586 }; 587 588 struct mlx5_eqe_congestion { 589 u8 type; 590 u8 rsvd0; 591 u8 congestion_level; 592 }; 593 594 struct mlx5_eqe_stall_vl { 595 u8 rsvd0[3]; 596 u8 port_vl; 597 }; 598 599 struct mlx5_eqe_cmd { 600 __be32 vector; 601 __be32 rsvd[6]; 602 }; 603 604 struct mlx5_eqe_page_req { 605 __be16 ec_function; 606 __be16 func_id; 607 __be32 num_pages; 608 __be32 rsvd1[5]; 609 }; 610 611 struct mlx5_eqe_page_fault { 612 __be32 bytes_committed; 613 union { 614 struct { 615 u16 reserved1; 616 __be16 wqe_index; 617 u16 reserved2; 618 __be16 packet_length; 619 __be32 token; 620 u8 reserved4[8]; 621 __be32 pftype_wq; 622 } __packed wqe; 623 struct { 624 __be32 r_key; 625 u16 reserved1; 626 __be16 packet_length; 627 __be32 rdma_op_len; 628 __be64 rdma_va; 629 __be32 pftype_token; 630 } __packed rdma; 631 } __packed; 632 } __packed; 633 634 struct mlx5_eqe_vport_change { 635 u8 rsvd0[2]; 636 __be16 vport_num; 637 __be32 rsvd1[6]; 638 } __packed; 639 640 struct mlx5_eqe_port_module { 641 u8 reserved_at_0[1]; 642 u8 module; 643 u8 reserved_at_2[1]; 644 u8 module_status; 645 u8 reserved_at_4[2]; 646 u8 error_type; 647 } __packed; 648 649 struct mlx5_eqe_pps { 650 u8 rsvd0[3]; 651 u8 pin; 652 u8 rsvd1[4]; 653 union { 654 struct { 655 __be32 time_sec; 656 __be32 time_nsec; 657 }; 658 struct { 659 __be64 time_stamp; 660 }; 661 }; 662 u8 rsvd2[12]; 663 } __packed; 664 665 struct mlx5_eqe_dct { 666 __be32 reserved[6]; 667 __be32 dctn; 668 }; 669 670 struct mlx5_eqe_temp_warning { 671 __be64 sensor_warning_msb; 672 __be64 sensor_warning_lsb; 673 } __packed; 674 675 union ev_data { 676 __be32 raw[7]; 677 struct mlx5_eqe_cmd cmd; 678 struct mlx5_eqe_comp comp; 679 struct mlx5_eqe_qp_srq qp_srq; 680 struct mlx5_eqe_cq_err cq_err; 681 struct mlx5_eqe_port_state port; 682 struct mlx5_eqe_gpio gpio; 683 struct mlx5_eqe_congestion cong; 684 struct mlx5_eqe_stall_vl stall_vl; 685 struct mlx5_eqe_page_req req_pages; 686 struct mlx5_eqe_page_fault page_fault; 687 struct mlx5_eqe_vport_change vport_change; 688 struct mlx5_eqe_port_module port_module; 689 struct mlx5_eqe_pps pps; 690 struct mlx5_eqe_dct dct; 691 struct mlx5_eqe_temp_warning temp_warning; 692 } __packed; 693 694 struct mlx5_eqe { 695 u8 rsvd0; 696 u8 type; 697 u8 rsvd1; 698 u8 sub_type; 699 __be32 rsvd2[7]; 700 union ev_data data; 701 __be16 rsvd3; 702 u8 signature; 703 u8 owner; 704 } __packed; 705 706 struct mlx5_cmd_prot_block { 707 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 708 u8 rsvd0[48]; 709 __be64 next; 710 __be32 block_num; 711 u8 rsvd1; 712 u8 token; 713 u8 ctrl_sig; 714 u8 sig; 715 }; 716 717 enum { 718 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 719 }; 720 721 struct mlx5_err_cqe { 722 u8 rsvd0[32]; 723 __be32 srqn; 724 u8 rsvd1[18]; 725 u8 vendor_err_synd; 726 u8 syndrome; 727 __be32 s_wqe_opcode_qpn; 728 __be16 wqe_counter; 729 u8 signature; 730 u8 op_own; 731 }; 732 733 struct mlx5_cqe64 { 734 u8 outer_l3_tunneled; 735 u8 rsvd0; 736 __be16 wqe_id; 737 u8 lro_tcppsh_abort_dupack; 738 u8 lro_min_ttl; 739 __be16 lro_tcp_win; 740 __be32 lro_ack_seq_num; 741 __be32 rss_hash_result; 742 u8 rss_hash_type; 743 u8 ml_path; 744 u8 rsvd20[2]; 745 __be16 check_sum; 746 __be16 slid; 747 __be32 flags_rqpn; 748 u8 hds_ip_ext; 749 u8 l4_l3_hdr_type; 750 __be16 vlan_info; 751 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 752 __be32 imm_inval_pkey; 753 u8 rsvd40[4]; 754 __be32 byte_cnt; 755 __be32 timestamp_h; 756 __be32 timestamp_l; 757 __be32 sop_drop_qpn; 758 __be16 wqe_counter; 759 u8 signature; 760 u8 op_own; 761 }; 762 763 struct mlx5_mini_cqe8 { 764 union { 765 __be32 rx_hash_result; 766 struct { 767 __be16 checksum; 768 __be16 rsvd; 769 }; 770 struct { 771 __be16 wqe_counter; 772 u8 s_wqe_opcode; 773 u8 reserved; 774 } s_wqe_info; 775 }; 776 __be32 byte_cnt; 777 }; 778 779 enum { 780 MLX5_NO_INLINE_DATA, 781 MLX5_INLINE_DATA32_SEG, 782 MLX5_INLINE_DATA64_SEG, 783 MLX5_COMPRESSED, 784 }; 785 786 enum { 787 MLX5_CQE_FORMAT_CSUM = 0x1, 788 }; 789 790 #define MLX5_MINI_CQE_ARRAY_SIZE 8 791 792 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 793 { 794 return (cqe->op_own >> 2) & 0x3; 795 } 796 797 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 798 { 799 return cqe->op_own >> 4; 800 } 801 802 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 803 { 804 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 805 } 806 807 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 808 { 809 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 810 } 811 812 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 813 { 814 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 815 } 816 817 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 818 { 819 return cqe->outer_l3_tunneled & 0x1; 820 } 821 822 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 823 { 824 return cqe->l4_l3_hdr_type & 0x1; 825 } 826 827 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 828 { 829 u32 hi, lo; 830 831 hi = be32_to_cpu(cqe->timestamp_h); 832 lo = be32_to_cpu(cqe->timestamp_l); 833 834 return (u64)lo | ((u64)hi << 32); 835 } 836 837 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9) 838 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6) 839 840 struct mpwrq_cqe_bc { 841 __be16 filler_consumed_strides; 842 __be16 byte_cnt; 843 }; 844 845 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 846 { 847 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 848 849 return be16_to_cpu(bc->byte_cnt); 850 } 851 852 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 853 { 854 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 855 } 856 857 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 858 { 859 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 860 861 return mpwrq_get_cqe_bc_consumed_strides(bc); 862 } 863 864 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 865 { 866 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 867 868 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 869 } 870 871 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 872 { 873 return be16_to_cpu(cqe->wqe_counter); 874 } 875 876 enum { 877 CQE_L4_HDR_TYPE_NONE = 0x0, 878 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 879 CQE_L4_HDR_TYPE_UDP = 0x2, 880 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 881 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 882 }; 883 884 enum { 885 CQE_RSS_HTYPE_IP = 0x3 << 2, 886 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 887 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 888 */ 889 CQE_RSS_HTYPE_L4 = 0x3 << 6, 890 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 891 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 892 */ 893 }; 894 895 enum { 896 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 897 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 898 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 899 }; 900 901 enum { 902 CQE_L2_OK = 1 << 0, 903 CQE_L3_OK = 1 << 1, 904 CQE_L4_OK = 1 << 2, 905 }; 906 907 struct mlx5_sig_err_cqe { 908 u8 rsvd0[16]; 909 __be32 expected_trans_sig; 910 __be32 actual_trans_sig; 911 __be32 expected_reftag; 912 __be32 actual_reftag; 913 __be16 syndrome; 914 u8 rsvd22[2]; 915 __be32 mkey; 916 __be64 err_offset; 917 u8 rsvd30[8]; 918 __be32 qpn; 919 u8 rsvd38[2]; 920 u8 signature; 921 u8 op_own; 922 }; 923 924 struct mlx5_wqe_srq_next_seg { 925 u8 rsvd0[2]; 926 __be16 next_wqe_index; 927 u8 signature; 928 u8 rsvd1[11]; 929 }; 930 931 union mlx5_ext_cqe { 932 struct ib_grh grh; 933 u8 inl[64]; 934 }; 935 936 struct mlx5_cqe128 { 937 union mlx5_ext_cqe inl_grh; 938 struct mlx5_cqe64 cqe64; 939 }; 940 941 enum { 942 MLX5_MKEY_STATUS_FREE = 1 << 6, 943 }; 944 945 enum { 946 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 947 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 948 MLX5_MKEY_BSF_EN = 1 << 30, 949 MLX5_MKEY_LEN64 = 1 << 31, 950 }; 951 952 struct mlx5_mkey_seg { 953 /* This is a two bit field occupying bits 31-30. 954 * bit 31 is always 0, 955 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 956 */ 957 u8 status; 958 u8 pcie_control; 959 u8 flags; 960 u8 version; 961 __be32 qpn_mkey7_0; 962 u8 rsvd1[4]; 963 __be32 flags_pd; 964 __be64 start_addr; 965 __be64 len; 966 __be32 bsfs_octo_size; 967 u8 rsvd2[16]; 968 __be32 xlt_oct_size; 969 u8 rsvd3[3]; 970 u8 log2_page_size; 971 u8 rsvd4[4]; 972 }; 973 974 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 975 976 enum { 977 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 978 }; 979 980 enum { 981 VPORT_STATE_DOWN = 0x0, 982 VPORT_STATE_UP = 0x1, 983 }; 984 985 enum { 986 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, 987 MLX5_VPORT_ADMIN_STATE_UP = 0x1, 988 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, 989 }; 990 991 enum { 992 MLX5_L3_PROT_TYPE_IPV4 = 0, 993 MLX5_L3_PROT_TYPE_IPV6 = 1, 994 }; 995 996 enum { 997 MLX5_L4_PROT_TYPE_TCP = 0, 998 MLX5_L4_PROT_TYPE_UDP = 1, 999 }; 1000 1001 enum { 1002 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1003 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1004 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1005 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1006 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1007 }; 1008 1009 enum { 1010 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1011 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1012 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1013 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 1014 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, 1015 }; 1016 1017 enum { 1018 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1019 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1020 }; 1021 1022 enum { 1023 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1024 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1025 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1026 }; 1027 1028 enum mlx5_list_type { 1029 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1030 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1031 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1032 }; 1033 1034 enum { 1035 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1036 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1037 }; 1038 1039 enum mlx5_wol_mode { 1040 MLX5_WOL_DISABLE = 0, 1041 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1042 MLX5_WOL_MAGIC = 1 << 2, 1043 MLX5_WOL_ARP = 1 << 3, 1044 MLX5_WOL_BROADCAST = 1 << 4, 1045 MLX5_WOL_MULTICAST = 1 << 5, 1046 MLX5_WOL_UNICAST = 1 << 6, 1047 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1048 }; 1049 1050 enum mlx5_mpls_supported_fields { 1051 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, 1052 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, 1053 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, 1054 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 1055 }; 1056 1057 enum mlx5_flex_parser_protos { 1058 MLX5_FLEX_PROTO_GENEVE = 1 << 3, 1059 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, 1060 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, 1061 }; 1062 1063 /* MLX5 DEV CAPs */ 1064 1065 /* TODO: EAT.ME */ 1066 enum mlx5_cap_mode { 1067 HCA_CAP_OPMOD_GET_MAX = 0, 1068 HCA_CAP_OPMOD_GET_CUR = 1, 1069 }; 1070 1071 enum mlx5_cap_type { 1072 MLX5_CAP_GENERAL = 0, 1073 MLX5_CAP_ETHERNET_OFFLOADS, 1074 MLX5_CAP_ODP, 1075 MLX5_CAP_ATOMIC, 1076 MLX5_CAP_ROCE, 1077 MLX5_CAP_IPOIB_OFFLOADS, 1078 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1079 MLX5_CAP_FLOW_TABLE, 1080 MLX5_CAP_ESWITCH_FLOW_TABLE, 1081 MLX5_CAP_ESWITCH, 1082 MLX5_CAP_RESERVED, 1083 MLX5_CAP_VECTOR_CALC, 1084 MLX5_CAP_QOS, 1085 MLX5_CAP_DEBUG, 1086 MLX5_CAP_RESERVED_14, 1087 MLX5_CAP_DEV_MEM, 1088 /* NUM OF CAP Types */ 1089 MLX5_CAP_NUM 1090 }; 1091 1092 enum mlx5_pcam_reg_groups { 1093 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1094 }; 1095 1096 enum mlx5_pcam_feature_groups { 1097 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1098 }; 1099 1100 enum mlx5_mcam_reg_groups { 1101 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1102 }; 1103 1104 enum mlx5_mcam_feature_groups { 1105 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1106 }; 1107 1108 enum mlx5_qcam_reg_groups { 1109 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1110 }; 1111 1112 enum mlx5_qcam_feature_groups { 1113 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1114 }; 1115 1116 /* GET Dev Caps macros */ 1117 #define MLX5_CAP_GEN(mdev, cap) \ 1118 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1119 1120 #define MLX5_CAP_GEN_64(mdev, cap) \ 1121 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1122 1123 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1124 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap) 1125 1126 #define MLX5_CAP_ETH(mdev, cap) \ 1127 MLX5_GET(per_protocol_networking_offload_caps,\ 1128 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1129 1130 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1131 MLX5_GET(per_protocol_networking_offload_caps,\ 1132 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1133 1134 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ 1135 MLX5_GET(per_protocol_networking_offload_caps,\ 1136 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap) 1137 1138 #define MLX5_CAP_ROCE(mdev, cap) \ 1139 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap) 1140 1141 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1142 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap) 1143 1144 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1145 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap) 1146 1147 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1148 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap) 1149 1150 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1151 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1152 1153 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1154 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap) 1155 1156 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1157 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1158 1159 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1160 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1161 1162 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1163 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1164 1165 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ 1166 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap) 1167 1168 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1169 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1170 1171 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1172 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1173 1174 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1175 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1176 1177 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1178 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1179 1180 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1181 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1182 1183 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ 1184 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap) 1185 1186 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1187 MLX5_GET(flow_table_eswitch_cap, \ 1188 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1189 1190 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1191 MLX5_GET(flow_table_eswitch_cap, \ 1192 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1193 1194 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1195 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1196 1197 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1198 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1199 1200 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1201 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1202 1203 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1204 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1205 1206 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1207 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1208 1209 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1210 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1211 1212 #define MLX5_CAP_ESW(mdev, cap) \ 1213 MLX5_GET(e_switch_cap, \ 1214 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap) 1215 1216 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1217 MLX5_GET(e_switch_cap, \ 1218 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap) 1219 1220 #define MLX5_CAP_ODP(mdev, cap)\ 1221 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap) 1222 1223 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1224 MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap) 1225 1226 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1227 MLX5_GET(vector_calc_cap, \ 1228 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap) 1229 1230 #define MLX5_CAP_QOS(mdev, cap)\ 1231 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) 1232 1233 #define MLX5_CAP_DEBUG(mdev, cap)\ 1234 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap) 1235 1236 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1237 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1238 1239 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1240 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1241 1242 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1243 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1244 1245 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1246 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1247 1248 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1249 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1250 1251 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1252 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1253 1254 #define MLX5_CAP_FPGA(mdev, cap) \ 1255 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1256 1257 #define MLX5_CAP64_FPGA(mdev, cap) \ 1258 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1259 1260 #define MLX5_CAP_DEV_MEM(mdev, cap)\ 1261 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap) 1262 1263 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ 1264 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap) 1265 1266 enum { 1267 MLX5_CMD_STAT_OK = 0x0, 1268 MLX5_CMD_STAT_INT_ERR = 0x1, 1269 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1270 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1271 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1272 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1273 MLX5_CMD_STAT_RES_BUSY = 0x6, 1274 MLX5_CMD_STAT_LIM_ERR = 0x8, 1275 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1276 MLX5_CMD_STAT_IX_ERR = 0xa, 1277 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1278 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1279 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1280 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1281 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1282 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1283 }; 1284 1285 enum { 1286 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1287 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1288 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1289 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1290 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1291 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1292 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1293 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1294 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1295 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1296 }; 1297 1298 enum { 1299 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1300 }; 1301 1302 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1303 { 1304 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1305 return 0; 1306 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1307 } 1308 1309 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 1310 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 1311 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1312 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1313 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1314 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1315 1316 #endif /* MLX5_DEVICE_H */ 1317