1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 u32 _v = v; \ 75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ 83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ 84 MLX5_SET(typ, p, fld[idx], v); \ 85 } while (0) 86 87 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 92 << __mlx5_dw_bit_off(typ, fld))); \ 93 } while (0) 94 95 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 96 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 97 __mlx5_mask(typ, fld)) 98 99 #define MLX5_GET_PR(typ, p, fld) ({ \ 100 u32 ___t = MLX5_GET(typ, p, fld); \ 101 pr_debug(#fld " = 0x%x\n", ___t); \ 102 ___t; \ 103 }) 104 105 #define __MLX5_SET64(typ, p, fld, v) do { \ 106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 108 } while (0) 109 110 #define MLX5_SET64(typ, p, fld, v) do { \ 111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 112 __MLX5_SET64(typ, p, fld, v); \ 113 } while (0) 114 115 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 117 __MLX5_SET64(typ, p, fld[idx], v); \ 118 } while (0) 119 120 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 121 122 #define MLX5_GET64_PR(typ, p, fld) ({ \ 123 u64 ___t = MLX5_GET64(typ, p, fld); \ 124 pr_debug(#fld " = 0x%llx\n", ___t); \ 125 ___t; \ 126 }) 127 128 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 129 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 130 __mlx5_mask16(typ, fld)) 131 132 #define MLX5_SET16(typ, p, fld, v) do { \ 133 u16 _v = v; \ 134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 138 << __mlx5_16_bit_off(typ, fld))); \ 139 } while (0) 140 141 /* Big endian getters */ 142 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 143 __mlx5_64_off(typ, fld))) 144 145 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 146 type_t tmp; \ 147 switch (sizeof(tmp)) { \ 148 case sizeof(u8): \ 149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 150 break; \ 151 case sizeof(u16): \ 152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 153 break; \ 154 case sizeof(u32): \ 155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 156 break; \ 157 case sizeof(u64): \ 158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 159 break; \ 160 } \ 161 tmp; \ 162 }) 163 164 enum mlx5_inline_modes { 165 MLX5_INLINE_MODE_NONE, 166 MLX5_INLINE_MODE_L2, 167 MLX5_INLINE_MODE_IP, 168 MLX5_INLINE_MODE_TCP_UDP, 169 }; 170 171 enum { 172 MLX5_MAX_COMMANDS = 32, 173 MLX5_CMD_DATA_BLOCK_SIZE = 512, 174 MLX5_PCI_CMD_XPORT = 7, 175 MLX5_MKEY_BSF_OCTO_SIZE = 4, 176 MLX5_MAX_PSVS = 4, 177 }; 178 179 enum { 180 MLX5_EXTENDED_UD_AV = 0x80000000, 181 }; 182 183 enum { 184 MLX5_CQ_STATE_ARMED = 9, 185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 186 MLX5_CQ_STATE_FIRED = 0xa, 187 }; 188 189 enum { 190 MLX5_STAT_RATE_OFFSET = 5, 191 }; 192 193 enum { 194 MLX5_INLINE_SEG = 0x80000000, 195 }; 196 197 enum { 198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 199 }; 200 201 enum { 202 MLX5_MIN_PKEY_TABLE_SIZE = 128, 203 MLX5_MAX_LOG_PKEY_TABLE = 5, 204 }; 205 206 enum { 207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 208 }; 209 210 enum { 211 MLX5_PFAULT_SUBTYPE_WQE = 0, 212 MLX5_PFAULT_SUBTYPE_RDMA = 1, 213 }; 214 215 enum wqe_page_fault_type { 216 MLX5_WQE_PF_TYPE_RMP = 0, 217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, 218 MLX5_WQE_PF_TYPE_RESP = 2, 219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, 220 }; 221 222 enum { 223 MLX5_PERM_LOCAL_READ = 1 << 2, 224 MLX5_PERM_LOCAL_WRITE = 1 << 3, 225 MLX5_PERM_REMOTE_READ = 1 << 4, 226 MLX5_PERM_REMOTE_WRITE = 1 << 5, 227 MLX5_PERM_ATOMIC = 1 << 6, 228 MLX5_PERM_UMR_EN = 1 << 7, 229 }; 230 231 enum { 232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 237 }; 238 239 enum { 240 MLX5_EN_RD = (u64)1, 241 MLX5_EN_WR = (u64)2 242 }; 243 244 enum { 245 MLX5_ADAPTER_PAGE_SHIFT = 12, 246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 247 }; 248 249 enum { 250 MLX5_BFREGS_PER_UAR = 4, 251 MLX5_MAX_UARS = 1 << 8, 252 MLX5_NON_FP_BFREGS_PER_UAR = 2, 253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 254 MLX5_NON_FP_BFREGS_PER_UAR, 255 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 256 MLX5_NON_FP_BFREGS_PER_UAR, 257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 259 MLX5_MIN_DYN_BFREGS = 512, 260 MLX5_MAX_DYN_BFREGS = 1024, 261 }; 262 263 enum { 264 MLX5_MKEY_MASK_LEN = 1ull << 0, 265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 267 MLX5_MKEY_MASK_PD = 1ull << 7, 268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 271 MLX5_MKEY_MASK_KEY = 1ull << 13, 272 MLX5_MKEY_MASK_QPN = 1ull << 14, 273 MLX5_MKEY_MASK_LR = 1ull << 17, 274 MLX5_MKEY_MASK_LW = 1ull << 18, 275 MLX5_MKEY_MASK_RR = 1ull << 19, 276 MLX5_MKEY_MASK_RW = 1ull << 20, 277 MLX5_MKEY_MASK_A = 1ull << 21, 278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 279 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, 280 MLX5_MKEY_MASK_FREE = 1ull << 29, 281 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, 282 }; 283 284 enum { 285 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 286 287 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 288 MLX5_UMR_CHECK_FREE = (2 << 5), 289 290 MLX5_UMR_INLINE = (1 << 7), 291 }; 292 293 #define MLX5_UMR_KLM_ALIGNMENT 4 294 #define MLX5_UMR_MTT_ALIGNMENT 0x40 295 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 296 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 297 298 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 299 300 enum { 301 MLX5_EVENT_QUEUE_TYPE_QP = 0, 302 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 303 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 304 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 305 }; 306 307 /* mlx5 components can subscribe to any one of these events via 308 * mlx5_eq_notifier_register API. 309 */ 310 enum mlx5_event { 311 /* Special value to subscribe to any event */ 312 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 313 /* HW events enum start: comp events are not subscribable */ 314 MLX5_EVENT_TYPE_COMP = 0x0, 315 /* HW Async events enum start: subscribable events */ 316 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 317 MLX5_EVENT_TYPE_COMM_EST = 0x02, 318 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 319 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 320 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 321 322 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 323 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 324 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 325 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 326 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 327 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 328 329 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 330 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 331 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 332 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 333 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 334 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 335 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 336 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, 337 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, 338 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 339 340 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 341 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 342 343 MLX5_EVENT_TYPE_CMD = 0x0a, 344 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 345 346 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 347 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 348 349 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, 350 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf, 351 352 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 353 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 354 355 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 356 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 357 358 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, 359 360 MLX5_EVENT_TYPE_MAX = 0x100, 361 }; 362 363 enum mlx5_driver_event { 364 MLX5_DRIVER_EVENT_TYPE_TRAP = 0, 365 }; 366 367 enum { 368 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, 369 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, 370 }; 371 372 enum { 373 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 374 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 375 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7, 376 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, 377 }; 378 379 enum { 380 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 381 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 382 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 383 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 384 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 385 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 386 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 387 }; 388 389 enum { 390 MLX5_ROCE_VERSION_1 = 0, 391 MLX5_ROCE_VERSION_2 = 2, 392 }; 393 394 enum { 395 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 396 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 397 }; 398 399 enum { 400 MLX5_ROCE_L3_TYPE_IPV4 = 0, 401 MLX5_ROCE_L3_TYPE_IPV6 = 1, 402 }; 403 404 enum { 405 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 406 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 407 }; 408 409 enum { 410 MLX5_OPCODE_NOP = 0x00, 411 MLX5_OPCODE_SEND_INVAL = 0x01, 412 MLX5_OPCODE_RDMA_WRITE = 0x08, 413 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 414 MLX5_OPCODE_SEND = 0x0a, 415 MLX5_OPCODE_SEND_IMM = 0x0b, 416 MLX5_OPCODE_LSO = 0x0e, 417 MLX5_OPCODE_RDMA_READ = 0x10, 418 MLX5_OPCODE_ATOMIC_CS = 0x11, 419 MLX5_OPCODE_ATOMIC_FA = 0x12, 420 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 421 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 422 MLX5_OPCODE_BIND_MW = 0x18, 423 MLX5_OPCODE_CONFIG_CMD = 0x1f, 424 MLX5_OPCODE_ENHANCED_MPSW = 0x29, 425 426 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 427 MLX5_RECV_OPCODE_SEND = 0x01, 428 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 429 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 430 431 MLX5_CQE_OPCODE_ERROR = 0x1e, 432 MLX5_CQE_OPCODE_RESIZE = 0x16, 433 434 MLX5_OPCODE_SET_PSV = 0x20, 435 MLX5_OPCODE_GET_PSV = 0x21, 436 MLX5_OPCODE_CHECK_PSV = 0x22, 437 MLX5_OPCODE_DUMP = 0x23, 438 MLX5_OPCODE_RGET_PSV = 0x26, 439 MLX5_OPCODE_RCHECK_PSV = 0x27, 440 441 MLX5_OPCODE_UMR = 0x25, 442 443 MLX5_OPCODE_ACCESS_ASO = 0x2d, 444 }; 445 446 enum { 447 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, 448 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, 449 }; 450 451 enum { 452 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, 453 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, 454 }; 455 456 struct mlx5_wqe_tls_static_params_seg { 457 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; 458 }; 459 460 struct mlx5_wqe_tls_progress_params_seg { 461 __be32 tis_tir_num; 462 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; 463 }; 464 465 enum { 466 MLX5_SET_PORT_RESET_QKEY = 0, 467 MLX5_SET_PORT_GUID0 = 16, 468 MLX5_SET_PORT_NODE_GUID = 17, 469 MLX5_SET_PORT_SYS_GUID = 18, 470 MLX5_SET_PORT_GID_TABLE = 19, 471 MLX5_SET_PORT_PKEY_TABLE = 20, 472 }; 473 474 enum { 475 MLX5_BW_NO_LIMIT = 0, 476 MLX5_100_MBPS_UNIT = 3, 477 MLX5_GBPS_UNIT = 4, 478 }; 479 480 enum { 481 MLX5_MAX_PAGE_SHIFT = 31 482 }; 483 484 enum { 485 /* 486 * Max wqe size for rdma read is 512 bytes, so this 487 * limits our max_sge_rd as the wqe needs to fit: 488 * - ctrl segment (16 bytes) 489 * - rdma segment (16 bytes) 490 * - scatter elements (16 bytes each) 491 */ 492 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 493 }; 494 495 enum mlx5_odp_transport_cap_bits { 496 MLX5_ODP_SUPPORT_SEND = 1 << 31, 497 MLX5_ODP_SUPPORT_RECV = 1 << 30, 498 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 499 MLX5_ODP_SUPPORT_READ = 1 << 28, 500 }; 501 502 struct mlx5_odp_caps { 503 char reserved[0x10]; 504 struct { 505 __be32 rc_odp_caps; 506 __be32 uc_odp_caps; 507 __be32 ud_odp_caps; 508 } per_transport_caps; 509 char reserved2[0xe4]; 510 }; 511 512 struct mlx5_cmd_layout { 513 u8 type; 514 u8 rsvd0[3]; 515 __be32 inlen; 516 __be64 in_ptr; 517 __be32 in[4]; 518 __be32 out[4]; 519 __be64 out_ptr; 520 __be32 outlen; 521 u8 token; 522 u8 sig; 523 u8 rsvd1; 524 u8 status_own; 525 }; 526 527 enum mlx5_rfr_severity_bit_offsets { 528 MLX5_RFR_BIT_OFFSET = 0x7, 529 }; 530 531 struct health_buffer { 532 __be32 assert_var[6]; 533 __be32 rsvd0[2]; 534 __be32 assert_exit_ptr; 535 __be32 assert_callra; 536 __be32 rsvd1[1]; 537 __be32 time; 538 __be32 fw_ver; 539 __be32 hw_id; 540 u8 rfr_severity; 541 u8 rsvd2[3]; 542 u8 irisc_index; 543 u8 synd; 544 __be16 ext_synd; 545 }; 546 547 enum mlx5_initializing_bit_offsets { 548 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 549 }; 550 551 enum mlx5_cmd_addr_l_sz_offset { 552 MLX5_NIC_IFC_OFFSET = 8, 553 }; 554 555 struct mlx5_init_seg { 556 __be32 fw_rev; 557 __be32 cmdif_rev_fw_sub; 558 __be32 rsvd0[2]; 559 __be32 cmdq_addr_h; 560 __be32 cmdq_addr_l_sz; 561 __be32 cmd_dbell; 562 __be32 rsvd1[120]; 563 __be32 initializing; 564 struct health_buffer health; 565 __be32 rsvd2[878]; 566 __be32 cmd_exec_to; 567 __be32 cmd_q_init_to; 568 __be32 internal_timer_h; 569 __be32 internal_timer_l; 570 __be32 rsvd3[2]; 571 __be32 health_counter; 572 __be32 rsvd4[11]; 573 __be32 real_time_h; 574 __be32 real_time_l; 575 __be32 rsvd5[1006]; 576 __be64 ieee1588_clk; 577 __be32 ieee1588_clk_type; 578 __be32 clr_intx; 579 }; 580 581 struct mlx5_eqe_comp { 582 __be32 reserved[6]; 583 __be32 cqn; 584 }; 585 586 struct mlx5_eqe_qp_srq { 587 __be32 reserved1[5]; 588 u8 type; 589 u8 reserved2[3]; 590 __be32 qp_srq_n; 591 }; 592 593 struct mlx5_eqe_cq_err { 594 __be32 cqn; 595 u8 reserved1[7]; 596 u8 syndrome; 597 }; 598 599 struct mlx5_eqe_xrq_err { 600 __be32 reserved1[5]; 601 __be32 type_xrqn; 602 __be32 reserved2; 603 }; 604 605 struct mlx5_eqe_port_state { 606 u8 reserved0[8]; 607 u8 port; 608 }; 609 610 struct mlx5_eqe_gpio { 611 __be32 reserved0[2]; 612 __be64 gpio_event; 613 }; 614 615 struct mlx5_eqe_congestion { 616 u8 type; 617 u8 rsvd0; 618 u8 congestion_level; 619 }; 620 621 struct mlx5_eqe_stall_vl { 622 u8 rsvd0[3]; 623 u8 port_vl; 624 }; 625 626 struct mlx5_eqe_cmd { 627 __be32 vector; 628 __be32 rsvd[6]; 629 }; 630 631 struct mlx5_eqe_page_req { 632 __be16 ec_function; 633 __be16 func_id; 634 __be32 num_pages; 635 __be32 rsvd1[5]; 636 }; 637 638 struct mlx5_eqe_page_fault { 639 __be32 bytes_committed; 640 union { 641 struct { 642 u16 reserved1; 643 __be16 wqe_index; 644 u16 reserved2; 645 __be16 packet_length; 646 __be32 token; 647 u8 reserved4[8]; 648 __be32 pftype_wq; 649 } __packed wqe; 650 struct { 651 __be32 r_key; 652 u16 reserved1; 653 __be16 packet_length; 654 __be32 rdma_op_len; 655 __be64 rdma_va; 656 __be32 pftype_token; 657 } __packed rdma; 658 } __packed; 659 } __packed; 660 661 struct mlx5_eqe_vport_change { 662 u8 rsvd0[2]; 663 __be16 vport_num; 664 __be32 rsvd1[6]; 665 } __packed; 666 667 struct mlx5_eqe_port_module { 668 u8 reserved_at_0[1]; 669 u8 module; 670 u8 reserved_at_2[1]; 671 u8 module_status; 672 u8 reserved_at_4[2]; 673 u8 error_type; 674 } __packed; 675 676 struct mlx5_eqe_pps { 677 u8 rsvd0[3]; 678 u8 pin; 679 u8 rsvd1[4]; 680 union { 681 struct { 682 __be32 time_sec; 683 __be32 time_nsec; 684 }; 685 struct { 686 __be64 time_stamp; 687 }; 688 }; 689 u8 rsvd2[12]; 690 } __packed; 691 692 struct mlx5_eqe_dct { 693 __be32 reserved[6]; 694 __be32 dctn; 695 }; 696 697 struct mlx5_eqe_temp_warning { 698 __be64 sensor_warning_msb; 699 __be64 sensor_warning_lsb; 700 } __packed; 701 702 #define SYNC_RST_STATE_MASK 0xf 703 704 enum sync_rst_state_type { 705 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, 706 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, 707 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, 708 }; 709 710 struct mlx5_eqe_sync_fw_update { 711 u8 reserved_at_0[3]; 712 u8 sync_rst_state; 713 }; 714 715 struct mlx5_eqe_vhca_state { 716 __be16 ec_function; 717 __be16 function_id; 718 } __packed; 719 720 union ev_data { 721 __be32 raw[7]; 722 struct mlx5_eqe_cmd cmd; 723 struct mlx5_eqe_comp comp; 724 struct mlx5_eqe_qp_srq qp_srq; 725 struct mlx5_eqe_cq_err cq_err; 726 struct mlx5_eqe_port_state port; 727 struct mlx5_eqe_gpio gpio; 728 struct mlx5_eqe_congestion cong; 729 struct mlx5_eqe_stall_vl stall_vl; 730 struct mlx5_eqe_page_req req_pages; 731 struct mlx5_eqe_page_fault page_fault; 732 struct mlx5_eqe_vport_change vport_change; 733 struct mlx5_eqe_port_module port_module; 734 struct mlx5_eqe_pps pps; 735 struct mlx5_eqe_dct dct; 736 struct mlx5_eqe_temp_warning temp_warning; 737 struct mlx5_eqe_xrq_err xrq_err; 738 struct mlx5_eqe_sync_fw_update sync_fw_update; 739 struct mlx5_eqe_vhca_state vhca_state; 740 } __packed; 741 742 struct mlx5_eqe { 743 u8 rsvd0; 744 u8 type; 745 u8 rsvd1; 746 u8 sub_type; 747 __be32 rsvd2[7]; 748 union ev_data data; 749 __be16 rsvd3; 750 u8 signature; 751 u8 owner; 752 } __packed; 753 754 struct mlx5_cmd_prot_block { 755 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 756 u8 rsvd0[48]; 757 __be64 next; 758 __be32 block_num; 759 u8 rsvd1; 760 u8 token; 761 u8 ctrl_sig; 762 u8 sig; 763 }; 764 765 enum { 766 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 767 }; 768 769 struct mlx5_err_cqe { 770 u8 rsvd0[32]; 771 __be32 srqn; 772 u8 rsvd1[18]; 773 u8 vendor_err_synd; 774 u8 syndrome; 775 __be32 s_wqe_opcode_qpn; 776 __be16 wqe_counter; 777 u8 signature; 778 u8 op_own; 779 }; 780 781 struct mlx5_cqe64 { 782 u8 tls_outer_l3_tunneled; 783 u8 rsvd0; 784 __be16 wqe_id; 785 union { 786 struct { 787 u8 tcppsh_abort_dupack; 788 u8 min_ttl; 789 __be16 tcp_win; 790 __be32 ack_seq_num; 791 } lro; 792 struct { 793 u8 reserved0:1; 794 u8 match:1; 795 u8 flush:1; 796 u8 reserved3:5; 797 u8 header_size; 798 __be16 header_entry_index; 799 __be32 data_offset; 800 } shampo; 801 }; 802 __be32 rss_hash_result; 803 u8 rss_hash_type; 804 u8 ml_path; 805 u8 rsvd20[2]; 806 __be16 check_sum; 807 __be16 slid; 808 __be32 flags_rqpn; 809 u8 hds_ip_ext; 810 u8 l4_l3_hdr_type; 811 __be16 vlan_info; 812 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 813 union { 814 __be32 immediate; 815 __be32 inval_rkey; 816 __be32 pkey; 817 __be32 ft_metadata; 818 }; 819 u8 rsvd40[4]; 820 __be32 byte_cnt; 821 __be32 timestamp_h; 822 __be32 timestamp_l; 823 __be32 sop_drop_qpn; 824 __be16 wqe_counter; 825 union { 826 u8 signature; 827 u8 validity_iteration_count; 828 }; 829 u8 op_own; 830 }; 831 832 struct mlx5_mini_cqe8 { 833 union { 834 __be32 rx_hash_result; 835 struct { 836 __be16 checksum; 837 __be16 stridx; 838 }; 839 struct { 840 __be16 wqe_counter; 841 u8 s_wqe_opcode; 842 u8 reserved; 843 } s_wqe_info; 844 }; 845 __be32 byte_cnt; 846 }; 847 848 enum { 849 MLX5_NO_INLINE_DATA, 850 MLX5_INLINE_DATA32_SEG, 851 MLX5_INLINE_DATA64_SEG, 852 MLX5_COMPRESSED, 853 }; 854 855 enum { 856 MLX5_CQE_FORMAT_CSUM = 0x1, 857 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3, 858 }; 859 860 enum { 861 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0, 862 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1, 863 }; 864 865 #define MLX5_MINI_CQE_ARRAY_SIZE 8 866 867 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 868 { 869 return (cqe->op_own >> 2) & 0x3; 870 } 871 872 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 873 { 874 return cqe->op_own >> 4; 875 } 876 877 static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe) 878 { 879 /* num_of_mini_cqes is zero based */ 880 return get_cqe_opcode(cqe) + 1; 881 } 882 883 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 884 { 885 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1; 886 } 887 888 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 889 { 890 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 891 } 892 893 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 894 { 895 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 896 } 897 898 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 899 { 900 return cqe->tls_outer_l3_tunneled & 0x1; 901 } 902 903 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) 904 { 905 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; 906 } 907 908 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 909 { 910 return cqe->l4_l3_hdr_type & 0x1; 911 } 912 913 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 914 { 915 u32 hi, lo; 916 917 hi = be32_to_cpu(cqe->timestamp_h); 918 lo = be32_to_cpu(cqe->timestamp_l); 919 920 return (u64)lo | ((u64)hi << 32); 921 } 922 923 static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe) 924 { 925 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; 926 } 927 928 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3 929 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9 930 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16 931 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6 932 #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13 933 934 struct mpwrq_cqe_bc { 935 __be16 filler_consumed_strides; 936 __be16 byte_cnt; 937 }; 938 939 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 940 { 941 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 942 943 return be16_to_cpu(bc->byte_cnt); 944 } 945 946 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 947 { 948 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 949 } 950 951 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 952 { 953 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 954 955 return mpwrq_get_cqe_bc_consumed_strides(bc); 956 } 957 958 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 959 { 960 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 961 962 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 963 } 964 965 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 966 { 967 return be16_to_cpu(cqe->wqe_counter); 968 } 969 970 enum { 971 CQE_L4_HDR_TYPE_NONE = 0x0, 972 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 973 CQE_L4_HDR_TYPE_UDP = 0x2, 974 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 975 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 976 }; 977 978 enum { 979 CQE_RSS_HTYPE_IP = 0x3 << 2, 980 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 981 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 982 */ 983 CQE_RSS_HTYPE_L4 = 0x3 << 6, 984 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 985 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 986 */ 987 }; 988 989 enum { 990 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 991 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 992 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 993 }; 994 995 enum { 996 CQE_L2_OK = 1 << 0, 997 CQE_L3_OK = 1 << 1, 998 CQE_L4_OK = 1 << 2, 999 }; 1000 1001 enum { 1002 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, 1003 CQE_TLS_OFFLOAD_DECRYPTED = 0x1, 1004 CQE_TLS_OFFLOAD_RESYNC = 0x2, 1005 CQE_TLS_OFFLOAD_ERROR = 0x3, 1006 }; 1007 1008 struct mlx5_sig_err_cqe { 1009 u8 rsvd0[16]; 1010 __be32 expected_trans_sig; 1011 __be32 actual_trans_sig; 1012 __be32 expected_reftag; 1013 __be32 actual_reftag; 1014 __be16 syndrome; 1015 u8 rsvd22[2]; 1016 __be32 mkey; 1017 __be64 err_offset; 1018 u8 rsvd30[8]; 1019 __be32 qpn; 1020 u8 rsvd38[2]; 1021 u8 signature; 1022 u8 op_own; 1023 }; 1024 1025 struct mlx5_wqe_srq_next_seg { 1026 u8 rsvd0[2]; 1027 __be16 next_wqe_index; 1028 u8 signature; 1029 u8 rsvd1[11]; 1030 }; 1031 1032 union mlx5_ext_cqe { 1033 struct ib_grh grh; 1034 u8 inl[64]; 1035 }; 1036 1037 struct mlx5_cqe128 { 1038 union mlx5_ext_cqe inl_grh; 1039 struct mlx5_cqe64 cqe64; 1040 }; 1041 1042 enum { 1043 MLX5_MKEY_STATUS_FREE = 1 << 6, 1044 }; 1045 1046 enum { 1047 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 1048 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 1049 MLX5_MKEY_BSF_EN = 1 << 30, 1050 }; 1051 1052 struct mlx5_mkey_seg { 1053 /* This is a two bit field occupying bits 31-30. 1054 * bit 31 is always 0, 1055 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation 1056 */ 1057 u8 status; 1058 u8 pcie_control; 1059 u8 flags; 1060 u8 version; 1061 __be32 qpn_mkey7_0; 1062 u8 rsvd1[4]; 1063 __be32 flags_pd; 1064 __be64 start_addr; 1065 __be64 len; 1066 __be32 bsfs_octo_size; 1067 u8 rsvd2[16]; 1068 __be32 xlt_oct_size; 1069 u8 rsvd3[3]; 1070 u8 log2_page_size; 1071 u8 rsvd4[4]; 1072 }; 1073 1074 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1075 1076 enum { 1077 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1078 }; 1079 1080 enum { 1081 VPORT_STATE_DOWN = 0x0, 1082 VPORT_STATE_UP = 0x1, 1083 }; 1084 1085 enum { 1086 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, 1087 MLX5_VPORT_ADMIN_STATE_UP = 0x1, 1088 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, 1089 }; 1090 1091 enum { 1092 MLX5_L3_PROT_TYPE_IPV4 = 0, 1093 MLX5_L3_PROT_TYPE_IPV6 = 1, 1094 }; 1095 1096 enum { 1097 MLX5_L4_PROT_TYPE_TCP = 0, 1098 MLX5_L4_PROT_TYPE_UDP = 1, 1099 }; 1100 1101 enum { 1102 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1103 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1104 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1105 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1106 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1107 }; 1108 1109 enum { 1110 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1111 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1112 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1113 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 1114 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, 1115 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, 1116 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6, 1117 }; 1118 1119 enum { 1120 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1121 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1122 }; 1123 1124 enum { 1125 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1126 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1127 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1128 }; 1129 1130 enum mlx5_list_type { 1131 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1132 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1133 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1134 }; 1135 1136 enum { 1137 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1138 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1139 }; 1140 1141 enum mlx5_wol_mode { 1142 MLX5_WOL_DISABLE = 0, 1143 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1144 MLX5_WOL_MAGIC = 1 << 2, 1145 MLX5_WOL_ARP = 1 << 3, 1146 MLX5_WOL_BROADCAST = 1 << 4, 1147 MLX5_WOL_MULTICAST = 1 << 5, 1148 MLX5_WOL_UNICAST = 1 << 6, 1149 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1150 }; 1151 1152 enum mlx5_mpls_supported_fields { 1153 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, 1154 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, 1155 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, 1156 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 1157 }; 1158 1159 enum mlx5_flex_parser_protos { 1160 MLX5_FLEX_PROTO_GENEVE = 1 << 3, 1161 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, 1162 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, 1163 MLX5_FLEX_PROTO_ICMP = 1 << 8, 1164 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9, 1165 }; 1166 1167 /* MLX5 DEV CAPs */ 1168 1169 /* TODO: EAT.ME */ 1170 enum mlx5_cap_mode { 1171 HCA_CAP_OPMOD_GET_MAX = 0, 1172 HCA_CAP_OPMOD_GET_CUR = 1, 1173 }; 1174 1175 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate 1176 * capability memory. 1177 */ 1178 enum mlx5_cap_type { 1179 MLX5_CAP_GENERAL = 0, 1180 MLX5_CAP_ETHERNET_OFFLOADS, 1181 MLX5_CAP_ODP, 1182 MLX5_CAP_ATOMIC, 1183 MLX5_CAP_ROCE, 1184 MLX5_CAP_IPOIB_OFFLOADS, 1185 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1186 MLX5_CAP_FLOW_TABLE, 1187 MLX5_CAP_ESWITCH_FLOW_TABLE, 1188 MLX5_CAP_ESWITCH, 1189 MLX5_CAP_RESERVED, 1190 MLX5_CAP_VECTOR_CALC, 1191 MLX5_CAP_QOS, 1192 MLX5_CAP_DEBUG, 1193 MLX5_CAP_RESERVED_14, 1194 MLX5_CAP_DEV_MEM, 1195 MLX5_CAP_RESERVED_16, 1196 MLX5_CAP_TLS, 1197 MLX5_CAP_VDPA_EMULATION = 0x13, 1198 MLX5_CAP_DEV_EVENT = 0x14, 1199 MLX5_CAP_IPSEC, 1200 MLX5_CAP_DEV_SHAMPO = 0x1d, 1201 MLX5_CAP_GENERAL_2 = 0x20, 1202 MLX5_CAP_PORT_SELECTION = 0x25, 1203 /* NUM OF CAP Types */ 1204 MLX5_CAP_NUM 1205 }; 1206 1207 enum mlx5_pcam_reg_groups { 1208 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1209 }; 1210 1211 enum mlx5_pcam_feature_groups { 1212 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1213 }; 1214 1215 enum mlx5_mcam_reg_groups { 1216 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1217 MLX5_MCAM_REGS_0x9080_0x90FF = 0x1, 1218 MLX5_MCAM_REGS_0x9100_0x917F = 0x2, 1219 MLX5_MCAM_REGS_NUM = 0x3, 1220 }; 1221 1222 enum mlx5_mcam_feature_groups { 1223 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1224 }; 1225 1226 enum mlx5_qcam_reg_groups { 1227 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1228 }; 1229 1230 enum mlx5_qcam_feature_groups { 1231 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1232 }; 1233 1234 /* GET Dev Caps macros */ 1235 #define MLX5_CAP_GEN(mdev, cap) \ 1236 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) 1237 1238 #define MLX5_CAP_GEN_64(mdev, cap) \ 1239 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) 1240 1241 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1242 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap) 1243 1244 #define MLX5_CAP_GEN_2(mdev, cap) \ 1245 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) 1246 1247 #define MLX5_CAP_GEN_2_64(mdev, cap) \ 1248 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) 1249 1250 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \ 1251 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap) 1252 1253 #define MLX5_CAP_ETH(mdev, cap) \ 1254 MLX5_GET(per_protocol_networking_offload_caps,\ 1255 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap) 1256 1257 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1258 MLX5_GET(per_protocol_networking_offload_caps,\ 1259 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap) 1260 1261 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ 1262 MLX5_GET(per_protocol_networking_offload_caps,\ 1263 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap) 1264 1265 #define MLX5_CAP_ROCE(mdev, cap) \ 1266 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap) 1267 1268 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1269 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap) 1270 1271 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1272 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap) 1273 1274 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1275 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap) 1276 1277 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1278 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) 1279 1280 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ 1281 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) 1282 1283 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1284 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap) 1285 1286 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1287 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1288 1289 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1290 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1291 1292 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1293 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1294 1295 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ 1296 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap) 1297 1298 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1299 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1300 1301 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1302 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1303 1304 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1305 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1306 1307 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1308 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1309 1310 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1311 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1312 1313 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ 1314 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap) 1315 1316 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ 1317 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) 1318 1319 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \ 1320 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap) 1321 1322 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1323 MLX5_GET(flow_table_eswitch_cap, \ 1324 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) 1325 1326 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1327 MLX5_GET(flow_table_eswitch_cap, \ 1328 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap) 1329 1330 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1331 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1332 1333 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1334 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1335 1336 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1337 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1338 1339 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1340 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1341 1342 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1343 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1344 1345 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1346 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1347 1348 #define MLX5_CAP_ESW(mdev, cap) \ 1349 MLX5_GET(e_switch_cap, \ 1350 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap) 1351 1352 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ 1353 MLX5_GET64(flow_table_eswitch_cap, \ 1354 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) 1355 1356 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1357 MLX5_GET(e_switch_cap, \ 1358 mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap) 1359 1360 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \ 1361 MLX5_GET(port_selection_cap, \ 1362 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap) 1363 1364 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \ 1365 MLX5_GET(port_selection_cap, \ 1366 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap) 1367 1368 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ 1369 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) 1370 1371 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION_MAX(mdev, cap) \ 1372 MLX5_CAP_PORT_SELECTION_MAX(mdev, flow_table_properties_port_selection.cap) 1373 1374 #define MLX5_CAP_ODP(mdev, cap)\ 1375 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap) 1376 1377 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1378 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap) 1379 1380 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1381 MLX5_GET(vector_calc_cap, \ 1382 mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap) 1383 1384 #define MLX5_CAP_QOS(mdev, cap)\ 1385 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap) 1386 1387 #define MLX5_CAP_DEBUG(mdev, cap)\ 1388 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap) 1389 1390 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1391 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1392 1393 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1394 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1395 1396 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1397 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ 1398 mng_access_reg_cap_mask.access_regs.reg) 1399 1400 #define MLX5_CAP_MCAM_REG1(mdev, reg) \ 1401 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \ 1402 mng_access_reg_cap_mask.access_regs1.reg) 1403 1404 #define MLX5_CAP_MCAM_REG2(mdev, reg) \ 1405 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ 1406 mng_access_reg_cap_mask.access_regs2.reg) 1407 1408 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1409 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1410 1411 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1412 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1413 1414 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1415 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1416 1417 #define MLX5_CAP_FPGA(mdev, cap) \ 1418 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1419 1420 #define MLX5_CAP64_FPGA(mdev, cap) \ 1421 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1422 1423 #define MLX5_CAP_DEV_MEM(mdev, cap)\ 1424 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) 1425 1426 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ 1427 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) 1428 1429 #define MLX5_CAP_TLS(mdev, cap) \ 1430 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap) 1431 1432 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1433 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap) 1434 1435 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ 1436 MLX5_GET(virtio_emulation_cap, \ 1437 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) 1438 1439 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ 1440 MLX5_GET64(virtio_emulation_cap, \ 1441 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) 1442 1443 #define MLX5_CAP_IPSEC(mdev, cap)\ 1444 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap) 1445 1446 #define MLX5_CAP_DEV_SHAMPO(mdev, cap)\ 1447 MLX5_GET(shampo_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_SHAMPO], cap) 1448 1449 enum { 1450 MLX5_CMD_STAT_OK = 0x0, 1451 MLX5_CMD_STAT_INT_ERR = 0x1, 1452 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1453 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1454 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1455 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1456 MLX5_CMD_STAT_RES_BUSY = 0x6, 1457 MLX5_CMD_STAT_LIM_ERR = 0x8, 1458 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1459 MLX5_CMD_STAT_IX_ERR = 0xa, 1460 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1461 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1462 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1463 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1464 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1465 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1466 }; 1467 1468 enum { 1469 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1470 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1471 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1472 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1473 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1474 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1475 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1476 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1477 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, 1478 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1479 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1480 }; 1481 1482 enum { 1483 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1484 }; 1485 1486 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1487 { 1488 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1489 return 0; 1490 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1491 } 1492 1493 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2 1494 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1 1495 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 1496 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 1497 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1498 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1499 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1500 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1501 1502 #endif /* MLX5_DEVICE_H */ 1503