1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) 52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62 63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) 71 72 /* insert a value to a struct */ 73 #define MLX5_SET(typ, p, fld, v) do { \ 74 u32 _v = v; \ 75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ 79 << __mlx5_dw_bit_off(typ, fld))); \ 80 } while (0) 81 82 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ 83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ 84 MLX5_SET(typ, p, fld[idx], v); \ 85 } while (0) 86 87 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 92 << __mlx5_dw_bit_off(typ, fld))); \ 93 } while (0) 94 95 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 96 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 97 __mlx5_mask(typ, fld)) 98 99 #define MLX5_GET_PR(typ, p, fld) ({ \ 100 u32 ___t = MLX5_GET(typ, p, fld); \ 101 pr_debug(#fld " = 0x%x\n", ___t); \ 102 ___t; \ 103 }) 104 105 #define __MLX5_SET64(typ, p, fld, v) do { \ 106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 108 } while (0) 109 110 #define MLX5_SET64(typ, p, fld, v) do { \ 111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 112 __MLX5_SET64(typ, p, fld, v); \ 113 } while (0) 114 115 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 117 __MLX5_SET64(typ, p, fld[idx], v); \ 118 } while (0) 119 120 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 121 122 #define MLX5_GET64_PR(typ, p, fld) ({ \ 123 u64 ___t = MLX5_GET64(typ, p, fld); \ 124 pr_debug(#fld " = 0x%llx\n", ___t); \ 125 ___t; \ 126 }) 127 128 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 129 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 130 __mlx5_mask16(typ, fld)) 131 132 #define MLX5_SET16(typ, p, fld, v) do { \ 133 u16 _v = v; \ 134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 138 << __mlx5_16_bit_off(typ, fld))); \ 139 } while (0) 140 141 /* Big endian getters */ 142 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 143 __mlx5_64_off(typ, fld))) 144 145 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 146 type_t tmp; \ 147 switch (sizeof(tmp)) { \ 148 case sizeof(u8): \ 149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 150 break; \ 151 case sizeof(u16): \ 152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 153 break; \ 154 case sizeof(u32): \ 155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 156 break; \ 157 case sizeof(u64): \ 158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 159 break; \ 160 } \ 161 tmp; \ 162 }) 163 164 enum mlx5_inline_modes { 165 MLX5_INLINE_MODE_NONE, 166 MLX5_INLINE_MODE_L2, 167 MLX5_INLINE_MODE_IP, 168 MLX5_INLINE_MODE_TCP_UDP, 169 }; 170 171 enum { 172 MLX5_MAX_COMMANDS = 32, 173 MLX5_CMD_DATA_BLOCK_SIZE = 512, 174 MLX5_PCI_CMD_XPORT = 7, 175 MLX5_MKEY_BSF_OCTO_SIZE = 4, 176 MLX5_MAX_PSVS = 4, 177 }; 178 179 enum { 180 MLX5_EXTENDED_UD_AV = 0x80000000, 181 }; 182 183 enum { 184 MLX5_CQ_STATE_ARMED = 9, 185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 186 MLX5_CQ_STATE_FIRED = 0xa, 187 }; 188 189 enum { 190 MLX5_STAT_RATE_OFFSET = 5, 191 }; 192 193 enum { 194 MLX5_INLINE_SEG = 0x80000000, 195 }; 196 197 enum { 198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 199 }; 200 201 enum { 202 MLX5_MIN_PKEY_TABLE_SIZE = 128, 203 MLX5_MAX_LOG_PKEY_TABLE = 5, 204 }; 205 206 enum { 207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 208 }; 209 210 enum { 211 MLX5_PFAULT_SUBTYPE_WQE = 0, 212 MLX5_PFAULT_SUBTYPE_RDMA = 1, 213 }; 214 215 enum wqe_page_fault_type { 216 MLX5_WQE_PF_TYPE_RMP = 0, 217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, 218 MLX5_WQE_PF_TYPE_RESP = 2, 219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, 220 }; 221 222 enum { 223 MLX5_PERM_LOCAL_READ = 1 << 2, 224 MLX5_PERM_LOCAL_WRITE = 1 << 3, 225 MLX5_PERM_REMOTE_READ = 1 << 4, 226 MLX5_PERM_REMOTE_WRITE = 1 << 5, 227 MLX5_PERM_ATOMIC = 1 << 6, 228 MLX5_PERM_UMR_EN = 1 << 7, 229 }; 230 231 enum { 232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 237 }; 238 239 enum { 240 MLX5_EN_RD = (u64)1, 241 MLX5_EN_WR = (u64)2 242 }; 243 244 enum { 245 MLX5_ADAPTER_PAGE_SHIFT = 12, 246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 247 }; 248 249 enum { 250 MLX5_BFREGS_PER_UAR = 4, 251 MLX5_MAX_UARS = 1 << 8, 252 MLX5_NON_FP_BFREGS_PER_UAR = 2, 253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 254 MLX5_NON_FP_BFREGS_PER_UAR, 255 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 256 MLX5_NON_FP_BFREGS_PER_UAR, 257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 259 MLX5_MIN_DYN_BFREGS = 512, 260 MLX5_MAX_DYN_BFREGS = 1024, 261 }; 262 263 enum { 264 MLX5_MKEY_MASK_LEN = 1ull << 0, 265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 267 MLX5_MKEY_MASK_PD = 1ull << 7, 268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 271 MLX5_MKEY_MASK_KEY = 1ull << 13, 272 MLX5_MKEY_MASK_QPN = 1ull << 14, 273 MLX5_MKEY_MASK_LR = 1ull << 17, 274 MLX5_MKEY_MASK_LW = 1ull << 18, 275 MLX5_MKEY_MASK_RR = 1ull << 19, 276 MLX5_MKEY_MASK_RW = 1ull << 20, 277 MLX5_MKEY_MASK_A = 1ull << 21, 278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 279 MLX5_MKEY_MASK_FREE = 1ull << 29, 280 }; 281 282 enum { 283 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 284 285 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 286 MLX5_UMR_CHECK_FREE = (2 << 5), 287 288 MLX5_UMR_INLINE = (1 << 7), 289 }; 290 291 #define MLX5_UMR_MTT_ALIGNMENT 0x40 292 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 293 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 294 295 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 296 297 enum { 298 MLX5_EVENT_QUEUE_TYPE_QP = 0, 299 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 300 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 301 MLX5_EVENT_QUEUE_TYPE_DCT = 6, 302 }; 303 304 /* mlx5 components can subscribe to any one of these events via 305 * mlx5_eq_notifier_register API. 306 */ 307 enum mlx5_event { 308 /* Special value to subscribe to any event */ 309 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 310 /* HW events enum start: comp events are not subscribable */ 311 MLX5_EVENT_TYPE_COMP = 0x0, 312 /* HW Async events enum start: subscribable events */ 313 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 314 MLX5_EVENT_TYPE_COMM_EST = 0x02, 315 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 316 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 317 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 318 319 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 320 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 321 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 322 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 323 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 324 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 325 326 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 327 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 328 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 329 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 330 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 331 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 332 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 333 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, 334 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, 335 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 336 337 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 338 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 339 340 MLX5_EVENT_TYPE_CMD = 0x0a, 341 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 342 343 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 344 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 345 346 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, 347 348 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 349 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 350 351 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 352 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 353 354 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, 355 356 MLX5_EVENT_TYPE_MAX = 0x100, 357 }; 358 359 enum { 360 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, 361 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, 362 }; 363 364 enum { 365 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 366 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 367 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, 368 }; 369 370 enum { 371 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 372 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 373 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 374 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 375 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 376 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 377 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 378 }; 379 380 enum { 381 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 382 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 383 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 384 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 385 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 386 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 387 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 388 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 389 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 390 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 391 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 392 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 393 }; 394 395 enum { 396 MLX5_ROCE_VERSION_1 = 0, 397 MLX5_ROCE_VERSION_2 = 2, 398 }; 399 400 enum { 401 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 402 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 403 }; 404 405 enum { 406 MLX5_ROCE_L3_TYPE_IPV4 = 0, 407 MLX5_ROCE_L3_TYPE_IPV6 = 1, 408 }; 409 410 enum { 411 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 412 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 413 }; 414 415 enum { 416 MLX5_OPCODE_NOP = 0x00, 417 MLX5_OPCODE_SEND_INVAL = 0x01, 418 MLX5_OPCODE_RDMA_WRITE = 0x08, 419 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 420 MLX5_OPCODE_SEND = 0x0a, 421 MLX5_OPCODE_SEND_IMM = 0x0b, 422 MLX5_OPCODE_LSO = 0x0e, 423 MLX5_OPCODE_RDMA_READ = 0x10, 424 MLX5_OPCODE_ATOMIC_CS = 0x11, 425 MLX5_OPCODE_ATOMIC_FA = 0x12, 426 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 427 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 428 MLX5_OPCODE_BIND_MW = 0x18, 429 MLX5_OPCODE_CONFIG_CMD = 0x1f, 430 MLX5_OPCODE_ENHANCED_MPSW = 0x29, 431 432 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 433 MLX5_RECV_OPCODE_SEND = 0x01, 434 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 435 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 436 437 MLX5_CQE_OPCODE_ERROR = 0x1e, 438 MLX5_CQE_OPCODE_RESIZE = 0x16, 439 440 MLX5_OPCODE_SET_PSV = 0x20, 441 MLX5_OPCODE_GET_PSV = 0x21, 442 MLX5_OPCODE_CHECK_PSV = 0x22, 443 MLX5_OPCODE_DUMP = 0x23, 444 MLX5_OPCODE_RGET_PSV = 0x26, 445 MLX5_OPCODE_RCHECK_PSV = 0x27, 446 447 MLX5_OPCODE_UMR = 0x25, 448 449 }; 450 451 enum { 452 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, 453 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, 454 }; 455 456 enum { 457 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, 458 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, 459 }; 460 461 struct mlx5_wqe_tls_static_params_seg { 462 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; 463 }; 464 465 struct mlx5_wqe_tls_progress_params_seg { 466 __be32 tis_tir_num; 467 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; 468 }; 469 470 enum { 471 MLX5_SET_PORT_RESET_QKEY = 0, 472 MLX5_SET_PORT_GUID0 = 16, 473 MLX5_SET_PORT_NODE_GUID = 17, 474 MLX5_SET_PORT_SYS_GUID = 18, 475 MLX5_SET_PORT_GID_TABLE = 19, 476 MLX5_SET_PORT_PKEY_TABLE = 20, 477 }; 478 479 enum { 480 MLX5_BW_NO_LIMIT = 0, 481 MLX5_100_MBPS_UNIT = 3, 482 MLX5_GBPS_UNIT = 4, 483 }; 484 485 enum { 486 MLX5_MAX_PAGE_SHIFT = 31 487 }; 488 489 enum { 490 MLX5_CAP_OFF_CMDIF_CSUM = 46, 491 }; 492 493 enum { 494 /* 495 * Max wqe size for rdma read is 512 bytes, so this 496 * limits our max_sge_rd as the wqe needs to fit: 497 * - ctrl segment (16 bytes) 498 * - rdma segment (16 bytes) 499 * - scatter elements (16 bytes each) 500 */ 501 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 502 }; 503 504 enum mlx5_odp_transport_cap_bits { 505 MLX5_ODP_SUPPORT_SEND = 1 << 31, 506 MLX5_ODP_SUPPORT_RECV = 1 << 30, 507 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 508 MLX5_ODP_SUPPORT_READ = 1 << 28, 509 }; 510 511 struct mlx5_odp_caps { 512 char reserved[0x10]; 513 struct { 514 __be32 rc_odp_caps; 515 __be32 uc_odp_caps; 516 __be32 ud_odp_caps; 517 } per_transport_caps; 518 char reserved2[0xe4]; 519 }; 520 521 struct mlx5_cmd_layout { 522 u8 type; 523 u8 rsvd0[3]; 524 __be32 inlen; 525 __be64 in_ptr; 526 __be32 in[4]; 527 __be32 out[4]; 528 __be64 out_ptr; 529 __be32 outlen; 530 u8 token; 531 u8 sig; 532 u8 rsvd1; 533 u8 status_own; 534 }; 535 536 enum mlx5_fatal_assert_bit_offsets { 537 MLX5_RFR_OFFSET = 31, 538 }; 539 540 struct health_buffer { 541 __be32 assert_var[5]; 542 __be32 rsvd0[3]; 543 __be32 assert_exit_ptr; 544 __be32 assert_callra; 545 __be32 rsvd1[2]; 546 __be32 fw_ver; 547 __be32 hw_id; 548 __be32 rfr; 549 u8 irisc_index; 550 u8 synd; 551 __be16 ext_synd; 552 }; 553 554 enum mlx5_initializing_bit_offsets { 555 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 556 }; 557 558 enum mlx5_cmd_addr_l_sz_offset { 559 MLX5_NIC_IFC_OFFSET = 8, 560 }; 561 562 struct mlx5_init_seg { 563 __be32 fw_rev; 564 __be32 cmdif_rev_fw_sub; 565 __be32 rsvd0[2]; 566 __be32 cmdq_addr_h; 567 __be32 cmdq_addr_l_sz; 568 __be32 cmd_dbell; 569 __be32 rsvd1[120]; 570 __be32 initializing; 571 struct health_buffer health; 572 __be32 rsvd2[880]; 573 __be32 internal_timer_h; 574 __be32 internal_timer_l; 575 __be32 rsvd3[2]; 576 __be32 health_counter; 577 __be32 rsvd4[1019]; 578 __be64 ieee1588_clk; 579 __be32 ieee1588_clk_type; 580 __be32 clr_intx; 581 }; 582 583 struct mlx5_eqe_comp { 584 __be32 reserved[6]; 585 __be32 cqn; 586 }; 587 588 struct mlx5_eqe_qp_srq { 589 __be32 reserved1[5]; 590 u8 type; 591 u8 reserved2[3]; 592 __be32 qp_srq_n; 593 }; 594 595 struct mlx5_eqe_cq_err { 596 __be32 cqn; 597 u8 reserved1[7]; 598 u8 syndrome; 599 }; 600 601 struct mlx5_eqe_xrq_err { 602 __be32 reserved1[5]; 603 __be32 type_xrqn; 604 __be32 reserved2; 605 }; 606 607 struct mlx5_eqe_port_state { 608 u8 reserved0[8]; 609 u8 port; 610 }; 611 612 struct mlx5_eqe_gpio { 613 __be32 reserved0[2]; 614 __be64 gpio_event; 615 }; 616 617 struct mlx5_eqe_congestion { 618 u8 type; 619 u8 rsvd0; 620 u8 congestion_level; 621 }; 622 623 struct mlx5_eqe_stall_vl { 624 u8 rsvd0[3]; 625 u8 port_vl; 626 }; 627 628 struct mlx5_eqe_cmd { 629 __be32 vector; 630 __be32 rsvd[6]; 631 }; 632 633 struct mlx5_eqe_page_req { 634 __be16 ec_function; 635 __be16 func_id; 636 __be32 num_pages; 637 __be32 rsvd1[5]; 638 }; 639 640 struct mlx5_eqe_page_fault { 641 __be32 bytes_committed; 642 union { 643 struct { 644 u16 reserved1; 645 __be16 wqe_index; 646 u16 reserved2; 647 __be16 packet_length; 648 __be32 token; 649 u8 reserved4[8]; 650 __be32 pftype_wq; 651 } __packed wqe; 652 struct { 653 __be32 r_key; 654 u16 reserved1; 655 __be16 packet_length; 656 __be32 rdma_op_len; 657 __be64 rdma_va; 658 __be32 pftype_token; 659 } __packed rdma; 660 } __packed; 661 } __packed; 662 663 struct mlx5_eqe_vport_change { 664 u8 rsvd0[2]; 665 __be16 vport_num; 666 __be32 rsvd1[6]; 667 } __packed; 668 669 struct mlx5_eqe_port_module { 670 u8 reserved_at_0[1]; 671 u8 module; 672 u8 reserved_at_2[1]; 673 u8 module_status; 674 u8 reserved_at_4[2]; 675 u8 error_type; 676 } __packed; 677 678 struct mlx5_eqe_pps { 679 u8 rsvd0[3]; 680 u8 pin; 681 u8 rsvd1[4]; 682 union { 683 struct { 684 __be32 time_sec; 685 __be32 time_nsec; 686 }; 687 struct { 688 __be64 time_stamp; 689 }; 690 }; 691 u8 rsvd2[12]; 692 } __packed; 693 694 struct mlx5_eqe_dct { 695 __be32 reserved[6]; 696 __be32 dctn; 697 }; 698 699 struct mlx5_eqe_temp_warning { 700 __be64 sensor_warning_msb; 701 __be64 sensor_warning_lsb; 702 } __packed; 703 704 #define SYNC_RST_STATE_MASK 0xf 705 706 enum sync_rst_state_type { 707 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, 708 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, 709 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, 710 }; 711 712 struct mlx5_eqe_sync_fw_update { 713 u8 reserved_at_0[3]; 714 u8 sync_rst_state; 715 }; 716 717 union ev_data { 718 __be32 raw[7]; 719 struct mlx5_eqe_cmd cmd; 720 struct mlx5_eqe_comp comp; 721 struct mlx5_eqe_qp_srq qp_srq; 722 struct mlx5_eqe_cq_err cq_err; 723 struct mlx5_eqe_port_state port; 724 struct mlx5_eqe_gpio gpio; 725 struct mlx5_eqe_congestion cong; 726 struct mlx5_eqe_stall_vl stall_vl; 727 struct mlx5_eqe_page_req req_pages; 728 struct mlx5_eqe_page_fault page_fault; 729 struct mlx5_eqe_vport_change vport_change; 730 struct mlx5_eqe_port_module port_module; 731 struct mlx5_eqe_pps pps; 732 struct mlx5_eqe_dct dct; 733 struct mlx5_eqe_temp_warning temp_warning; 734 struct mlx5_eqe_xrq_err xrq_err; 735 struct mlx5_eqe_sync_fw_update sync_fw_update; 736 } __packed; 737 738 struct mlx5_eqe { 739 u8 rsvd0; 740 u8 type; 741 u8 rsvd1; 742 u8 sub_type; 743 __be32 rsvd2[7]; 744 union ev_data data; 745 __be16 rsvd3; 746 u8 signature; 747 u8 owner; 748 } __packed; 749 750 struct mlx5_cmd_prot_block { 751 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 752 u8 rsvd0[48]; 753 __be64 next; 754 __be32 block_num; 755 u8 rsvd1; 756 u8 token; 757 u8 ctrl_sig; 758 u8 sig; 759 }; 760 761 enum { 762 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 763 }; 764 765 struct mlx5_err_cqe { 766 u8 rsvd0[32]; 767 __be32 srqn; 768 u8 rsvd1[18]; 769 u8 vendor_err_synd; 770 u8 syndrome; 771 __be32 s_wqe_opcode_qpn; 772 __be16 wqe_counter; 773 u8 signature; 774 u8 op_own; 775 }; 776 777 struct mlx5_cqe64 { 778 u8 tls_outer_l3_tunneled; 779 u8 rsvd0; 780 __be16 wqe_id; 781 u8 lro_tcppsh_abort_dupack; 782 u8 lro_min_ttl; 783 __be16 lro_tcp_win; 784 __be32 lro_ack_seq_num; 785 __be32 rss_hash_result; 786 u8 rss_hash_type; 787 u8 ml_path; 788 u8 rsvd20[2]; 789 __be16 check_sum; 790 __be16 slid; 791 __be32 flags_rqpn; 792 u8 hds_ip_ext; 793 u8 l4_l3_hdr_type; 794 __be16 vlan_info; 795 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 796 union { 797 __be32 immediate; 798 __be32 inval_rkey; 799 __be32 pkey; 800 __be32 ft_metadata; 801 }; 802 u8 rsvd40[4]; 803 __be32 byte_cnt; 804 __be32 timestamp_h; 805 __be32 timestamp_l; 806 __be32 sop_drop_qpn; 807 __be16 wqe_counter; 808 u8 signature; 809 u8 op_own; 810 }; 811 812 struct mlx5_mini_cqe8 { 813 union { 814 __be32 rx_hash_result; 815 struct { 816 __be16 checksum; 817 __be16 rsvd; 818 }; 819 struct { 820 __be16 wqe_counter; 821 u8 s_wqe_opcode; 822 u8 reserved; 823 } s_wqe_info; 824 }; 825 __be32 byte_cnt; 826 }; 827 828 enum { 829 MLX5_NO_INLINE_DATA, 830 MLX5_INLINE_DATA32_SEG, 831 MLX5_INLINE_DATA64_SEG, 832 MLX5_COMPRESSED, 833 }; 834 835 enum { 836 MLX5_CQE_FORMAT_CSUM = 0x1, 837 }; 838 839 #define MLX5_MINI_CQE_ARRAY_SIZE 8 840 841 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 842 { 843 return (cqe->op_own >> 2) & 0x3; 844 } 845 846 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) 847 { 848 return cqe->op_own >> 4; 849 } 850 851 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 852 { 853 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 854 } 855 856 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 857 { 858 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 859 } 860 861 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 862 { 863 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 864 } 865 866 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 867 { 868 return cqe->tls_outer_l3_tunneled & 0x1; 869 } 870 871 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) 872 { 873 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; 874 } 875 876 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 877 { 878 return cqe->l4_l3_hdr_type & 0x1; 879 } 880 881 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 882 { 883 u32 hi, lo; 884 885 hi = be32_to_cpu(cqe->timestamp_h); 886 lo = be32_to_cpu(cqe->timestamp_l); 887 888 return (u64)lo | ((u64)hi << 32); 889 } 890 891 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9) 892 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6) 893 894 struct mpwrq_cqe_bc { 895 __be16 filler_consumed_strides; 896 __be16 byte_cnt; 897 }; 898 899 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 900 { 901 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 902 903 return be16_to_cpu(bc->byte_cnt); 904 } 905 906 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 907 { 908 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 909 } 910 911 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 912 { 913 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 914 915 return mpwrq_get_cqe_bc_consumed_strides(bc); 916 } 917 918 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 919 { 920 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 921 922 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 923 } 924 925 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 926 { 927 return be16_to_cpu(cqe->wqe_counter); 928 } 929 930 enum { 931 CQE_L4_HDR_TYPE_NONE = 0x0, 932 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 933 CQE_L4_HDR_TYPE_UDP = 0x2, 934 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 935 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 936 }; 937 938 enum { 939 CQE_RSS_HTYPE_IP = 0x3 << 2, 940 /* cqe->rss_hash_type[3:2] - IP destination selected for hash 941 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) 942 */ 943 CQE_RSS_HTYPE_L4 = 0x3 << 6, 944 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash 945 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI 946 */ 947 }; 948 949 enum { 950 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 951 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 952 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 953 }; 954 955 enum { 956 CQE_L2_OK = 1 << 0, 957 CQE_L3_OK = 1 << 1, 958 CQE_L4_OK = 1 << 2, 959 }; 960 961 enum { 962 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, 963 CQE_TLS_OFFLOAD_DECRYPTED = 0x1, 964 CQE_TLS_OFFLOAD_RESYNC = 0x2, 965 CQE_TLS_OFFLOAD_ERROR = 0x3, 966 }; 967 968 struct mlx5_sig_err_cqe { 969 u8 rsvd0[16]; 970 __be32 expected_trans_sig; 971 __be32 actual_trans_sig; 972 __be32 expected_reftag; 973 __be32 actual_reftag; 974 __be16 syndrome; 975 u8 rsvd22[2]; 976 __be32 mkey; 977 __be64 err_offset; 978 u8 rsvd30[8]; 979 __be32 qpn; 980 u8 rsvd38[2]; 981 u8 signature; 982 u8 op_own; 983 }; 984 985 struct mlx5_wqe_srq_next_seg { 986 u8 rsvd0[2]; 987 __be16 next_wqe_index; 988 u8 signature; 989 u8 rsvd1[11]; 990 }; 991 992 union mlx5_ext_cqe { 993 struct ib_grh grh; 994 u8 inl[64]; 995 }; 996 997 struct mlx5_cqe128 { 998 union mlx5_ext_cqe inl_grh; 999 struct mlx5_cqe64 cqe64; 1000 }; 1001 1002 enum { 1003 MLX5_MKEY_STATUS_FREE = 1 << 6, 1004 }; 1005 1006 enum { 1007 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 1008 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 1009 MLX5_MKEY_BSF_EN = 1 << 30, 1010 MLX5_MKEY_LEN64 = 1 << 31, 1011 }; 1012 1013 struct mlx5_mkey_seg { 1014 /* This is a two bit field occupying bits 31-30. 1015 * bit 31 is always 0, 1016 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 1017 */ 1018 u8 status; 1019 u8 pcie_control; 1020 u8 flags; 1021 u8 version; 1022 __be32 qpn_mkey7_0; 1023 u8 rsvd1[4]; 1024 __be32 flags_pd; 1025 __be64 start_addr; 1026 __be64 len; 1027 __be32 bsfs_octo_size; 1028 u8 rsvd2[16]; 1029 __be32 xlt_oct_size; 1030 u8 rsvd3[3]; 1031 u8 log2_page_size; 1032 u8 rsvd4[4]; 1033 }; 1034 1035 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1036 1037 enum { 1038 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1039 }; 1040 1041 enum { 1042 VPORT_STATE_DOWN = 0x0, 1043 VPORT_STATE_UP = 0x1, 1044 }; 1045 1046 enum { 1047 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, 1048 MLX5_VPORT_ADMIN_STATE_UP = 0x1, 1049 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, 1050 }; 1051 1052 enum { 1053 MLX5_L3_PROT_TYPE_IPV4 = 0, 1054 MLX5_L3_PROT_TYPE_IPV6 = 1, 1055 }; 1056 1057 enum { 1058 MLX5_L4_PROT_TYPE_TCP = 0, 1059 MLX5_L4_PROT_TYPE_UDP = 1, 1060 }; 1061 1062 enum { 1063 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1064 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1065 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1066 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1067 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1068 }; 1069 1070 enum { 1071 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1072 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1073 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1074 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, 1075 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, 1076 }; 1077 1078 enum { 1079 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1080 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1081 }; 1082 1083 enum { 1084 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1085 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1086 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1087 }; 1088 1089 enum mlx5_list_type { 1090 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1091 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1092 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1093 }; 1094 1095 enum { 1096 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1097 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1098 }; 1099 1100 enum mlx5_wol_mode { 1101 MLX5_WOL_DISABLE = 0, 1102 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1103 MLX5_WOL_MAGIC = 1 << 2, 1104 MLX5_WOL_ARP = 1 << 3, 1105 MLX5_WOL_BROADCAST = 1 << 4, 1106 MLX5_WOL_MULTICAST = 1 << 5, 1107 MLX5_WOL_UNICAST = 1 << 6, 1108 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1109 }; 1110 1111 enum mlx5_mpls_supported_fields { 1112 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, 1113 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, 1114 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, 1115 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 1116 }; 1117 1118 enum mlx5_flex_parser_protos { 1119 MLX5_FLEX_PROTO_GENEVE = 1 << 3, 1120 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, 1121 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, 1122 }; 1123 1124 /* MLX5 DEV CAPs */ 1125 1126 /* TODO: EAT.ME */ 1127 enum mlx5_cap_mode { 1128 HCA_CAP_OPMOD_GET_MAX = 0, 1129 HCA_CAP_OPMOD_GET_CUR = 1, 1130 }; 1131 1132 enum mlx5_cap_type { 1133 MLX5_CAP_GENERAL = 0, 1134 MLX5_CAP_ETHERNET_OFFLOADS, 1135 MLX5_CAP_ODP, 1136 MLX5_CAP_ATOMIC, 1137 MLX5_CAP_ROCE, 1138 MLX5_CAP_IPOIB_OFFLOADS, 1139 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, 1140 MLX5_CAP_FLOW_TABLE, 1141 MLX5_CAP_ESWITCH_FLOW_TABLE, 1142 MLX5_CAP_ESWITCH, 1143 MLX5_CAP_RESERVED, 1144 MLX5_CAP_VECTOR_CALC, 1145 MLX5_CAP_QOS, 1146 MLX5_CAP_DEBUG, 1147 MLX5_CAP_RESERVED_14, 1148 MLX5_CAP_DEV_MEM, 1149 MLX5_CAP_RESERVED_16, 1150 MLX5_CAP_TLS, 1151 MLX5_CAP_VDPA_EMULATION = 0x13, 1152 MLX5_CAP_DEV_EVENT = 0x14, 1153 MLX5_CAP_IPSEC, 1154 /* NUM OF CAP Types */ 1155 MLX5_CAP_NUM 1156 }; 1157 1158 enum mlx5_pcam_reg_groups { 1159 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 1160 }; 1161 1162 enum mlx5_pcam_feature_groups { 1163 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1164 }; 1165 1166 enum mlx5_mcam_reg_groups { 1167 MLX5_MCAM_REGS_FIRST_128 = 0x0, 1168 MLX5_MCAM_REGS_0x9080_0x90FF = 0x1, 1169 MLX5_MCAM_REGS_0x9100_0x917F = 0x2, 1170 MLX5_MCAM_REGS_NUM = 0x3, 1171 }; 1172 1173 enum mlx5_mcam_feature_groups { 1174 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1175 }; 1176 1177 enum mlx5_qcam_reg_groups { 1178 MLX5_QCAM_REGS_FIRST_128 = 0x0, 1179 }; 1180 1181 enum mlx5_qcam_feature_groups { 1182 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 1183 }; 1184 1185 /* GET Dev Caps macros */ 1186 #define MLX5_CAP_GEN(mdev, cap) \ 1187 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1188 1189 #define MLX5_CAP_GEN_64(mdev, cap) \ 1190 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 1191 1192 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1193 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap) 1194 1195 #define MLX5_CAP_ETH(mdev, cap) \ 1196 MLX5_GET(per_protocol_networking_offload_caps,\ 1197 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1198 1199 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1200 MLX5_GET(per_protocol_networking_offload_caps,\ 1201 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1202 1203 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ 1204 MLX5_GET(per_protocol_networking_offload_caps,\ 1205 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap) 1206 1207 #define MLX5_CAP_ROCE(mdev, cap) \ 1208 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap) 1209 1210 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1211 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap) 1212 1213 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1214 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap) 1215 1216 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1217 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap) 1218 1219 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1220 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1221 1222 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ 1223 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1224 1225 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1226 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap) 1227 1228 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1229 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1230 1231 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1232 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1233 1234 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ 1235 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) 1236 1237 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \ 1238 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap) 1239 1240 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1241 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1242 1243 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1244 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1245 1246 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1247 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1248 1249 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1250 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1251 1252 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ 1253 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) 1254 1255 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \ 1256 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap) 1257 1258 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ 1259 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) 1260 1261 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \ 1262 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap) 1263 1264 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1265 MLX5_GET(flow_table_eswitch_cap, \ 1266 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1267 1268 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1269 MLX5_GET(flow_table_eswitch_cap, \ 1270 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1271 1272 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1273 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1274 1275 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1276 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1277 1278 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1279 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1280 1281 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1282 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1283 1284 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1285 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1286 1287 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1288 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1289 1290 #define MLX5_CAP_ESW(mdev, cap) \ 1291 MLX5_GET(e_switch_cap, \ 1292 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap) 1293 1294 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ 1295 MLX5_GET64(flow_table_eswitch_cap, \ 1296 (mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1297 1298 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1299 MLX5_GET(e_switch_cap, \ 1300 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap) 1301 1302 #define MLX5_CAP_ODP(mdev, cap)\ 1303 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap) 1304 1305 #define MLX5_CAP_ODP_MAX(mdev, cap)\ 1306 MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap) 1307 1308 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1309 MLX5_GET(vector_calc_cap, \ 1310 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap) 1311 1312 #define MLX5_CAP_QOS(mdev, cap)\ 1313 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) 1314 1315 #define MLX5_CAP_DEBUG(mdev, cap)\ 1316 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap) 1317 1318 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1319 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1320 1321 #define MLX5_CAP_PCAM_REG(mdev, reg) \ 1322 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1323 1324 #define MLX5_CAP_MCAM_REG(mdev, reg) \ 1325 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ 1326 mng_access_reg_cap_mask.access_regs.reg) 1327 1328 #define MLX5_CAP_MCAM_REG1(mdev, reg) \ 1329 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \ 1330 mng_access_reg_cap_mask.access_regs1.reg) 1331 1332 #define MLX5_CAP_MCAM_REG2(mdev, reg) \ 1333 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ 1334 mng_access_reg_cap_mask.access_regs2.reg) 1335 1336 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1337 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1338 1339 #define MLX5_CAP_QCAM_REG(mdev, fld) \ 1340 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1341 1342 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1343 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1344 1345 #define MLX5_CAP_FPGA(mdev, cap) \ 1346 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1347 1348 #define MLX5_CAP64_FPGA(mdev, cap) \ 1349 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1350 1351 #define MLX5_CAP_DEV_MEM(mdev, cap)\ 1352 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap) 1353 1354 #define MLX5_CAP64_DEV_MEM(mdev, cap)\ 1355 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap) 1356 1357 #define MLX5_CAP_TLS(mdev, cap) \ 1358 MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap) 1359 1360 #define MLX5_CAP_DEV_EVENT(mdev, cap)\ 1361 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap) 1362 1363 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ 1364 MLX5_GET(device_virtio_emulation_cap, \ 1365 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap) 1366 1367 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ 1368 MLX5_GET64(device_virtio_emulation_cap, \ 1369 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap) 1370 1371 #define MLX5_CAP_IPSEC(mdev, cap)\ 1372 MLX5_GET(ipsec_cap, (mdev)->caps.hca_cur[MLX5_CAP_IPSEC], cap) 1373 1374 enum { 1375 MLX5_CMD_STAT_OK = 0x0, 1376 MLX5_CMD_STAT_INT_ERR = 0x1, 1377 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1378 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1379 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1380 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1381 MLX5_CMD_STAT_RES_BUSY = 0x6, 1382 MLX5_CMD_STAT_LIM_ERR = 0x8, 1383 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1384 MLX5_CMD_STAT_IX_ERR = 0xa, 1385 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1386 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1387 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1388 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1389 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1390 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1391 }; 1392 1393 enum { 1394 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1395 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1396 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1397 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1398 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1399 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1400 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1401 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1402 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, 1403 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1404 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1405 }; 1406 1407 enum { 1408 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1409 }; 1410 1411 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1412 { 1413 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1414 return 0; 1415 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1416 } 1417 1418 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 1419 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 1420 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1421 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1422 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1423 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1424 1425 #endif /* MLX5_DEVICE_H */ 1426