1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 58 59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 66 67 /* insert a value to a struct */ 68 #define MLX5_SET(typ, p, fld, v) do { \ 69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73 << __mlx5_dw_bit_off(typ, fld))); \ 74 } while (0) 75 76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 81 << __mlx5_dw_bit_off(typ, fld))); \ 82 } while (0) 83 84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 86 __mlx5_mask(typ, fld)) 87 88 #define MLX5_GET_PR(typ, p, fld) ({ \ 89 u32 ___t = MLX5_GET(typ, p, fld); \ 90 pr_debug(#fld " = 0x%x\n", ___t); \ 91 ___t; \ 92 }) 93 94 #define MLX5_SET64(typ, p, fld, v) do { \ 95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 98 } while (0) 99 100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 101 102 #define MLX5_GET64_PR(typ, p, fld) ({ \ 103 u64 ___t = MLX5_GET64(typ, p, fld); \ 104 pr_debug(#fld " = 0x%llx\n", ___t); \ 105 ___t; \ 106 }) 107 108 enum { 109 MLX5_MAX_COMMANDS = 32, 110 MLX5_CMD_DATA_BLOCK_SIZE = 512, 111 MLX5_PCI_CMD_XPORT = 7, 112 MLX5_MKEY_BSF_OCTO_SIZE = 4, 113 MLX5_MAX_PSVS = 4, 114 }; 115 116 enum { 117 MLX5_EXTENDED_UD_AV = 0x80000000, 118 }; 119 120 enum { 121 MLX5_CQ_STATE_ARMED = 9, 122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 123 MLX5_CQ_STATE_FIRED = 0xa, 124 }; 125 126 enum { 127 MLX5_STAT_RATE_OFFSET = 5, 128 }; 129 130 enum { 131 MLX5_INLINE_SEG = 0x80000000, 132 }; 133 134 enum { 135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 136 }; 137 138 enum { 139 MLX5_MIN_PKEY_TABLE_SIZE = 128, 140 MLX5_MAX_LOG_PKEY_TABLE = 5, 141 }; 142 143 enum { 144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 145 }; 146 147 enum { 148 MLX5_PFAULT_SUBTYPE_WQE = 0, 149 MLX5_PFAULT_SUBTYPE_RDMA = 1, 150 }; 151 152 enum { 153 MLX5_PERM_LOCAL_READ = 1 << 2, 154 MLX5_PERM_LOCAL_WRITE = 1 << 3, 155 MLX5_PERM_REMOTE_READ = 1 << 4, 156 MLX5_PERM_REMOTE_WRITE = 1 << 5, 157 MLX5_PERM_ATOMIC = 1 << 6, 158 MLX5_PERM_UMR_EN = 1 << 7, 159 }; 160 161 enum { 162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 167 }; 168 169 enum { 170 MLX5_ACCESS_MODE_PA = 0, 171 MLX5_ACCESS_MODE_MTT = 1, 172 MLX5_ACCESS_MODE_KLM = 2 173 }; 174 175 enum { 176 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 178 MLX5_MKEY_BSF_EN = 1 << 30, 179 MLX5_MKEY_LEN64 = 1 << 31, 180 }; 181 182 enum { 183 MLX5_EN_RD = (u64)1, 184 MLX5_EN_WR = (u64)2 185 }; 186 187 enum { 188 MLX5_BF_REGS_PER_PAGE = 4, 189 MLX5_MAX_UAR_PAGES = 1 << 8, 190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 192 }; 193 194 enum { 195 MLX5_MKEY_MASK_LEN = 1ull << 0, 196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 198 MLX5_MKEY_MASK_PD = 1ull << 7, 199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 202 MLX5_MKEY_MASK_KEY = 1ull << 13, 203 MLX5_MKEY_MASK_QPN = 1ull << 14, 204 MLX5_MKEY_MASK_LR = 1ull << 17, 205 MLX5_MKEY_MASK_LW = 1ull << 18, 206 MLX5_MKEY_MASK_RR = 1ull << 19, 207 MLX5_MKEY_MASK_RW = 1ull << 20, 208 MLX5_MKEY_MASK_A = 1ull << 21, 209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 210 MLX5_MKEY_MASK_FREE = 1ull << 29, 211 }; 212 213 enum { 214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 215 216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 217 MLX5_UMR_CHECK_FREE = (2 << 5), 218 219 MLX5_UMR_INLINE = (1 << 7), 220 }; 221 222 #define MLX5_UMR_MTT_ALIGNMENT 0x40 223 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 224 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 225 226 enum mlx5_event { 227 MLX5_EVENT_TYPE_COMP = 0x0, 228 229 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 230 MLX5_EVENT_TYPE_COMM_EST = 0x02, 231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 234 235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 241 242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 246 247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 249 250 MLX5_EVENT_TYPE_CMD = 0x0a, 251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 252 253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 254 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 255 }; 256 257 enum { 258 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 259 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 260 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 261 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 262 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 263 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 264 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 265 }; 266 267 enum { 268 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 269 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 270 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 271 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 272 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 273 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 274 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 275 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 276 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 277 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 278 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 279 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 280 }; 281 282 enum { 283 MLX5_OPCODE_NOP = 0x00, 284 MLX5_OPCODE_SEND_INVAL = 0x01, 285 MLX5_OPCODE_RDMA_WRITE = 0x08, 286 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 287 MLX5_OPCODE_SEND = 0x0a, 288 MLX5_OPCODE_SEND_IMM = 0x0b, 289 MLX5_OPCODE_LSO = 0x0e, 290 MLX5_OPCODE_RDMA_READ = 0x10, 291 MLX5_OPCODE_ATOMIC_CS = 0x11, 292 MLX5_OPCODE_ATOMIC_FA = 0x12, 293 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 294 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 295 MLX5_OPCODE_BIND_MW = 0x18, 296 MLX5_OPCODE_CONFIG_CMD = 0x1f, 297 298 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 299 MLX5_RECV_OPCODE_SEND = 0x01, 300 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 301 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 302 303 MLX5_CQE_OPCODE_ERROR = 0x1e, 304 MLX5_CQE_OPCODE_RESIZE = 0x16, 305 306 MLX5_OPCODE_SET_PSV = 0x20, 307 MLX5_OPCODE_GET_PSV = 0x21, 308 MLX5_OPCODE_CHECK_PSV = 0x22, 309 MLX5_OPCODE_RGET_PSV = 0x26, 310 MLX5_OPCODE_RCHECK_PSV = 0x27, 311 312 MLX5_OPCODE_UMR = 0x25, 313 314 }; 315 316 enum { 317 MLX5_SET_PORT_RESET_QKEY = 0, 318 MLX5_SET_PORT_GUID0 = 16, 319 MLX5_SET_PORT_NODE_GUID = 17, 320 MLX5_SET_PORT_SYS_GUID = 18, 321 MLX5_SET_PORT_GID_TABLE = 19, 322 MLX5_SET_PORT_PKEY_TABLE = 20, 323 }; 324 325 enum { 326 MLX5_MAX_PAGE_SHIFT = 31 327 }; 328 329 enum { 330 MLX5_ADAPTER_PAGE_SHIFT = 12, 331 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 332 }; 333 334 enum { 335 MLX5_CAP_OFF_CMDIF_CSUM = 46, 336 }; 337 338 struct mlx5_inbox_hdr { 339 __be16 opcode; 340 u8 rsvd[4]; 341 __be16 opmod; 342 }; 343 344 struct mlx5_outbox_hdr { 345 u8 status; 346 u8 rsvd[3]; 347 __be32 syndrome; 348 }; 349 350 struct mlx5_cmd_query_adapter_mbox_in { 351 struct mlx5_inbox_hdr hdr; 352 u8 rsvd[8]; 353 }; 354 355 struct mlx5_cmd_query_adapter_mbox_out { 356 struct mlx5_outbox_hdr hdr; 357 u8 rsvd0[24]; 358 u8 intapin; 359 u8 rsvd1[13]; 360 __be16 vsd_vendor_id; 361 u8 vsd[208]; 362 u8 vsd_psid[16]; 363 }; 364 365 enum mlx5_odp_transport_cap_bits { 366 MLX5_ODP_SUPPORT_SEND = 1 << 31, 367 MLX5_ODP_SUPPORT_RECV = 1 << 30, 368 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 369 MLX5_ODP_SUPPORT_READ = 1 << 28, 370 }; 371 372 struct mlx5_odp_caps { 373 char reserved[0x10]; 374 struct { 375 __be32 rc_odp_caps; 376 __be32 uc_odp_caps; 377 __be32 ud_odp_caps; 378 } per_transport_caps; 379 char reserved2[0xe4]; 380 }; 381 382 struct mlx5_cmd_init_hca_mbox_in { 383 struct mlx5_inbox_hdr hdr; 384 u8 rsvd0[2]; 385 __be16 profile; 386 u8 rsvd1[4]; 387 }; 388 389 struct mlx5_cmd_init_hca_mbox_out { 390 struct mlx5_outbox_hdr hdr; 391 u8 rsvd[8]; 392 }; 393 394 struct mlx5_cmd_teardown_hca_mbox_in { 395 struct mlx5_inbox_hdr hdr; 396 u8 rsvd0[2]; 397 __be16 profile; 398 u8 rsvd1[4]; 399 }; 400 401 struct mlx5_cmd_teardown_hca_mbox_out { 402 struct mlx5_outbox_hdr hdr; 403 u8 rsvd[8]; 404 }; 405 406 struct mlx5_cmd_layout { 407 u8 type; 408 u8 rsvd0[3]; 409 __be32 inlen; 410 __be64 in_ptr; 411 __be32 in[4]; 412 __be32 out[4]; 413 __be64 out_ptr; 414 __be32 outlen; 415 u8 token; 416 u8 sig; 417 u8 rsvd1; 418 u8 status_own; 419 }; 420 421 422 struct health_buffer { 423 __be32 assert_var[5]; 424 __be32 rsvd0[3]; 425 __be32 assert_exit_ptr; 426 __be32 assert_callra; 427 __be32 rsvd1[2]; 428 __be32 fw_ver; 429 __be32 hw_id; 430 __be32 rsvd2; 431 u8 irisc_index; 432 u8 synd; 433 __be16 ext_synd; 434 }; 435 436 struct mlx5_init_seg { 437 __be32 fw_rev; 438 __be32 cmdif_rev_fw_sub; 439 __be32 rsvd0[2]; 440 __be32 cmdq_addr_h; 441 __be32 cmdq_addr_l_sz; 442 __be32 cmd_dbell; 443 __be32 rsvd1[120]; 444 __be32 initializing; 445 struct health_buffer health; 446 __be32 rsvd2[880]; 447 __be32 internal_timer_h; 448 __be32 internal_timer_l; 449 __be32 rsrv3[2]; 450 __be32 health_counter; 451 __be32 rsvd4[1019]; 452 __be64 ieee1588_clk; 453 __be32 ieee1588_clk_type; 454 __be32 clr_intx; 455 }; 456 457 struct mlx5_eqe_comp { 458 __be32 reserved[6]; 459 __be32 cqn; 460 }; 461 462 struct mlx5_eqe_qp_srq { 463 __be32 reserved[6]; 464 __be32 qp_srq_n; 465 }; 466 467 struct mlx5_eqe_cq_err { 468 __be32 cqn; 469 u8 reserved1[7]; 470 u8 syndrome; 471 }; 472 473 struct mlx5_eqe_port_state { 474 u8 reserved0[8]; 475 u8 port; 476 }; 477 478 struct mlx5_eqe_gpio { 479 __be32 reserved0[2]; 480 __be64 gpio_event; 481 }; 482 483 struct mlx5_eqe_congestion { 484 u8 type; 485 u8 rsvd0; 486 u8 congestion_level; 487 }; 488 489 struct mlx5_eqe_stall_vl { 490 u8 rsvd0[3]; 491 u8 port_vl; 492 }; 493 494 struct mlx5_eqe_cmd { 495 __be32 vector; 496 __be32 rsvd[6]; 497 }; 498 499 struct mlx5_eqe_page_req { 500 u8 rsvd0[2]; 501 __be16 func_id; 502 __be32 num_pages; 503 __be32 rsvd1[5]; 504 }; 505 506 struct mlx5_eqe_page_fault { 507 __be32 bytes_committed; 508 union { 509 struct { 510 u16 reserved1; 511 __be16 wqe_index; 512 u16 reserved2; 513 __be16 packet_length; 514 u8 reserved3[12]; 515 } __packed wqe; 516 struct { 517 __be32 r_key; 518 u16 reserved1; 519 __be16 packet_length; 520 __be32 rdma_op_len; 521 __be64 rdma_va; 522 } __packed rdma; 523 } __packed; 524 __be32 flags_qpn; 525 } __packed; 526 527 struct mlx5_eqe_vport_change { 528 u8 rsvd0[2]; 529 __be16 vport_num; 530 __be32 rsvd1[6]; 531 } __packed; 532 533 union ev_data { 534 __be32 raw[7]; 535 struct mlx5_eqe_cmd cmd; 536 struct mlx5_eqe_comp comp; 537 struct mlx5_eqe_qp_srq qp_srq; 538 struct mlx5_eqe_cq_err cq_err; 539 struct mlx5_eqe_port_state port; 540 struct mlx5_eqe_gpio gpio; 541 struct mlx5_eqe_congestion cong; 542 struct mlx5_eqe_stall_vl stall_vl; 543 struct mlx5_eqe_page_req req_pages; 544 struct mlx5_eqe_page_fault page_fault; 545 struct mlx5_eqe_vport_change vport_change; 546 } __packed; 547 548 struct mlx5_eqe { 549 u8 rsvd0; 550 u8 type; 551 u8 rsvd1; 552 u8 sub_type; 553 __be32 rsvd2[7]; 554 union ev_data data; 555 __be16 rsvd3; 556 u8 signature; 557 u8 owner; 558 } __packed; 559 560 struct mlx5_cmd_prot_block { 561 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 562 u8 rsvd0[48]; 563 __be64 next; 564 __be32 block_num; 565 u8 rsvd1; 566 u8 token; 567 u8 ctrl_sig; 568 u8 sig; 569 }; 570 571 enum { 572 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 573 }; 574 575 struct mlx5_err_cqe { 576 u8 rsvd0[32]; 577 __be32 srqn; 578 u8 rsvd1[18]; 579 u8 vendor_err_synd; 580 u8 syndrome; 581 __be32 s_wqe_opcode_qpn; 582 __be16 wqe_counter; 583 u8 signature; 584 u8 op_own; 585 }; 586 587 struct mlx5_cqe64 { 588 u8 rsvd0[4]; 589 u8 lro_tcppsh_abort_dupack; 590 u8 lro_min_ttl; 591 __be16 lro_tcp_win; 592 __be32 lro_ack_seq_num; 593 __be32 rss_hash_result; 594 u8 rss_hash_type; 595 u8 ml_path; 596 u8 rsvd20[2]; 597 __be16 check_sum; 598 __be16 slid; 599 __be32 flags_rqpn; 600 u8 hds_ip_ext; 601 u8 l4_hdr_type_etc; 602 __be16 vlan_info; 603 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 604 __be32 imm_inval_pkey; 605 u8 rsvd40[4]; 606 __be32 byte_cnt; 607 __be32 timestamp_h; 608 __be32 timestamp_l; 609 __be32 sop_drop_qpn; 610 __be16 wqe_counter; 611 u8 signature; 612 u8 op_own; 613 }; 614 615 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 616 { 617 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 618 } 619 620 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 621 { 622 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 623 } 624 625 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) 626 { 627 return !!(cqe->l4_hdr_type_etc & 0x1); 628 } 629 630 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 631 { 632 u32 hi, lo; 633 634 hi = be32_to_cpu(cqe->timestamp_h); 635 lo = be32_to_cpu(cqe->timestamp_l); 636 637 return (u64)lo | ((u64)hi << 32); 638 } 639 640 enum { 641 CQE_L4_HDR_TYPE_NONE = 0x0, 642 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 643 CQE_L4_HDR_TYPE_UDP = 0x2, 644 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 645 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 646 }; 647 648 enum { 649 CQE_RSS_HTYPE_IP = 0x3 << 6, 650 CQE_RSS_HTYPE_L4 = 0x3 << 2, 651 }; 652 653 enum { 654 CQE_L2_OK = 1 << 0, 655 CQE_L3_OK = 1 << 1, 656 CQE_L4_OK = 1 << 2, 657 }; 658 659 struct mlx5_sig_err_cqe { 660 u8 rsvd0[16]; 661 __be32 expected_trans_sig; 662 __be32 actual_trans_sig; 663 __be32 expected_reftag; 664 __be32 actual_reftag; 665 __be16 syndrome; 666 u8 rsvd22[2]; 667 __be32 mkey; 668 __be64 err_offset; 669 u8 rsvd30[8]; 670 __be32 qpn; 671 u8 rsvd38[2]; 672 u8 signature; 673 u8 op_own; 674 }; 675 676 struct mlx5_wqe_srq_next_seg { 677 u8 rsvd0[2]; 678 __be16 next_wqe_index; 679 u8 signature; 680 u8 rsvd1[11]; 681 }; 682 683 union mlx5_ext_cqe { 684 struct ib_grh grh; 685 u8 inl[64]; 686 }; 687 688 struct mlx5_cqe128 { 689 union mlx5_ext_cqe inl_grh; 690 struct mlx5_cqe64 cqe64; 691 }; 692 693 struct mlx5_srq_ctx { 694 u8 state_log_sz; 695 u8 rsvd0[3]; 696 __be32 flags_xrcd; 697 __be32 pgoff_cqn; 698 u8 rsvd1[4]; 699 u8 log_pg_sz; 700 u8 rsvd2[7]; 701 __be32 pd; 702 __be16 lwm; 703 __be16 wqe_cnt; 704 u8 rsvd3[8]; 705 __be64 db_record; 706 }; 707 708 struct mlx5_create_srq_mbox_in { 709 struct mlx5_inbox_hdr hdr; 710 __be32 input_srqn; 711 u8 rsvd0[4]; 712 struct mlx5_srq_ctx ctx; 713 u8 rsvd1[208]; 714 __be64 pas[0]; 715 }; 716 717 struct mlx5_create_srq_mbox_out { 718 struct mlx5_outbox_hdr hdr; 719 __be32 srqn; 720 u8 rsvd[4]; 721 }; 722 723 struct mlx5_destroy_srq_mbox_in { 724 struct mlx5_inbox_hdr hdr; 725 __be32 srqn; 726 u8 rsvd[4]; 727 }; 728 729 struct mlx5_destroy_srq_mbox_out { 730 struct mlx5_outbox_hdr hdr; 731 u8 rsvd[8]; 732 }; 733 734 struct mlx5_query_srq_mbox_in { 735 struct mlx5_inbox_hdr hdr; 736 __be32 srqn; 737 u8 rsvd0[4]; 738 }; 739 740 struct mlx5_query_srq_mbox_out { 741 struct mlx5_outbox_hdr hdr; 742 u8 rsvd0[8]; 743 struct mlx5_srq_ctx ctx; 744 u8 rsvd1[32]; 745 __be64 pas[0]; 746 }; 747 748 struct mlx5_arm_srq_mbox_in { 749 struct mlx5_inbox_hdr hdr; 750 __be32 srqn; 751 __be16 rsvd; 752 __be16 lwm; 753 }; 754 755 struct mlx5_arm_srq_mbox_out { 756 struct mlx5_outbox_hdr hdr; 757 u8 rsvd[8]; 758 }; 759 760 struct mlx5_cq_context { 761 u8 status; 762 u8 cqe_sz_flags; 763 u8 st; 764 u8 rsvd3; 765 u8 rsvd4[6]; 766 __be16 page_offset; 767 __be32 log_sz_usr_page; 768 __be16 cq_period; 769 __be16 cq_max_count; 770 __be16 rsvd20; 771 __be16 c_eqn; 772 u8 log_pg_sz; 773 u8 rsvd25[7]; 774 __be32 last_notified_index; 775 __be32 solicit_producer_index; 776 __be32 consumer_counter; 777 __be32 producer_counter; 778 u8 rsvd48[8]; 779 __be64 db_record_addr; 780 }; 781 782 struct mlx5_create_cq_mbox_in { 783 struct mlx5_inbox_hdr hdr; 784 __be32 input_cqn; 785 u8 rsvdx[4]; 786 struct mlx5_cq_context ctx; 787 u8 rsvd6[192]; 788 __be64 pas[0]; 789 }; 790 791 struct mlx5_create_cq_mbox_out { 792 struct mlx5_outbox_hdr hdr; 793 __be32 cqn; 794 u8 rsvd0[4]; 795 }; 796 797 struct mlx5_destroy_cq_mbox_in { 798 struct mlx5_inbox_hdr hdr; 799 __be32 cqn; 800 u8 rsvd0[4]; 801 }; 802 803 struct mlx5_destroy_cq_mbox_out { 804 struct mlx5_outbox_hdr hdr; 805 u8 rsvd0[8]; 806 }; 807 808 struct mlx5_query_cq_mbox_in { 809 struct mlx5_inbox_hdr hdr; 810 __be32 cqn; 811 u8 rsvd0[4]; 812 }; 813 814 struct mlx5_query_cq_mbox_out { 815 struct mlx5_outbox_hdr hdr; 816 u8 rsvd0[8]; 817 struct mlx5_cq_context ctx; 818 u8 rsvd6[16]; 819 __be64 pas[0]; 820 }; 821 822 struct mlx5_modify_cq_mbox_in { 823 struct mlx5_inbox_hdr hdr; 824 __be32 cqn; 825 __be32 field_select; 826 struct mlx5_cq_context ctx; 827 u8 rsvd[192]; 828 __be64 pas[0]; 829 }; 830 831 struct mlx5_modify_cq_mbox_out { 832 struct mlx5_outbox_hdr hdr; 833 u8 rsvd[8]; 834 }; 835 836 struct mlx5_enable_hca_mbox_in { 837 struct mlx5_inbox_hdr hdr; 838 u8 rsvd[8]; 839 }; 840 841 struct mlx5_enable_hca_mbox_out { 842 struct mlx5_outbox_hdr hdr; 843 u8 rsvd[8]; 844 }; 845 846 struct mlx5_disable_hca_mbox_in { 847 struct mlx5_inbox_hdr hdr; 848 u8 rsvd[8]; 849 }; 850 851 struct mlx5_disable_hca_mbox_out { 852 struct mlx5_outbox_hdr hdr; 853 u8 rsvd[8]; 854 }; 855 856 struct mlx5_eq_context { 857 u8 status; 858 u8 ec_oi; 859 u8 st; 860 u8 rsvd2[7]; 861 __be16 page_pffset; 862 __be32 log_sz_usr_page; 863 u8 rsvd3[7]; 864 u8 intr; 865 u8 log_page_size; 866 u8 rsvd4[15]; 867 __be32 consumer_counter; 868 __be32 produser_counter; 869 u8 rsvd5[16]; 870 }; 871 872 struct mlx5_create_eq_mbox_in { 873 struct mlx5_inbox_hdr hdr; 874 u8 rsvd0[3]; 875 u8 input_eqn; 876 u8 rsvd1[4]; 877 struct mlx5_eq_context ctx; 878 u8 rsvd2[8]; 879 __be64 events_mask; 880 u8 rsvd3[176]; 881 __be64 pas[0]; 882 }; 883 884 struct mlx5_create_eq_mbox_out { 885 struct mlx5_outbox_hdr hdr; 886 u8 rsvd0[3]; 887 u8 eq_number; 888 u8 rsvd1[4]; 889 }; 890 891 struct mlx5_destroy_eq_mbox_in { 892 struct mlx5_inbox_hdr hdr; 893 u8 rsvd0[3]; 894 u8 eqn; 895 u8 rsvd1[4]; 896 }; 897 898 struct mlx5_destroy_eq_mbox_out { 899 struct mlx5_outbox_hdr hdr; 900 u8 rsvd[8]; 901 }; 902 903 struct mlx5_map_eq_mbox_in { 904 struct mlx5_inbox_hdr hdr; 905 __be64 mask; 906 u8 mu; 907 u8 rsvd0[2]; 908 u8 eqn; 909 u8 rsvd1[24]; 910 }; 911 912 struct mlx5_map_eq_mbox_out { 913 struct mlx5_outbox_hdr hdr; 914 u8 rsvd[8]; 915 }; 916 917 struct mlx5_query_eq_mbox_in { 918 struct mlx5_inbox_hdr hdr; 919 u8 rsvd0[3]; 920 u8 eqn; 921 u8 rsvd1[4]; 922 }; 923 924 struct mlx5_query_eq_mbox_out { 925 struct mlx5_outbox_hdr hdr; 926 u8 rsvd[8]; 927 struct mlx5_eq_context ctx; 928 }; 929 930 enum { 931 MLX5_MKEY_STATUS_FREE = 1 << 6, 932 }; 933 934 struct mlx5_mkey_seg { 935 /* This is a two bit field occupying bits 31-30. 936 * bit 31 is always 0, 937 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 938 */ 939 u8 status; 940 u8 pcie_control; 941 u8 flags; 942 u8 version; 943 __be32 qpn_mkey7_0; 944 u8 rsvd1[4]; 945 __be32 flags_pd; 946 __be64 start_addr; 947 __be64 len; 948 __be32 bsfs_octo_size; 949 u8 rsvd2[16]; 950 __be32 xlt_oct_size; 951 u8 rsvd3[3]; 952 u8 log2_page_size; 953 u8 rsvd4[4]; 954 }; 955 956 struct mlx5_query_special_ctxs_mbox_in { 957 struct mlx5_inbox_hdr hdr; 958 u8 rsvd[8]; 959 }; 960 961 struct mlx5_query_special_ctxs_mbox_out { 962 struct mlx5_outbox_hdr hdr; 963 __be32 dump_fill_mkey; 964 __be32 reserved_lkey; 965 }; 966 967 struct mlx5_create_mkey_mbox_in { 968 struct mlx5_inbox_hdr hdr; 969 __be32 input_mkey_index; 970 __be32 flags; 971 struct mlx5_mkey_seg seg; 972 u8 rsvd1[16]; 973 __be32 xlat_oct_act_size; 974 __be32 rsvd2; 975 u8 rsvd3[168]; 976 __be64 pas[0]; 977 }; 978 979 struct mlx5_create_mkey_mbox_out { 980 struct mlx5_outbox_hdr hdr; 981 __be32 mkey; 982 u8 rsvd[4]; 983 }; 984 985 struct mlx5_destroy_mkey_mbox_in { 986 struct mlx5_inbox_hdr hdr; 987 __be32 mkey; 988 u8 rsvd[4]; 989 }; 990 991 struct mlx5_destroy_mkey_mbox_out { 992 struct mlx5_outbox_hdr hdr; 993 u8 rsvd[8]; 994 }; 995 996 struct mlx5_query_mkey_mbox_in { 997 struct mlx5_inbox_hdr hdr; 998 __be32 mkey; 999 }; 1000 1001 struct mlx5_query_mkey_mbox_out { 1002 struct mlx5_outbox_hdr hdr; 1003 __be64 pas[0]; 1004 }; 1005 1006 struct mlx5_modify_mkey_mbox_in { 1007 struct mlx5_inbox_hdr hdr; 1008 __be32 mkey; 1009 __be64 pas[0]; 1010 }; 1011 1012 struct mlx5_modify_mkey_mbox_out { 1013 struct mlx5_outbox_hdr hdr; 1014 u8 rsvd[8]; 1015 }; 1016 1017 struct mlx5_dump_mkey_mbox_in { 1018 struct mlx5_inbox_hdr hdr; 1019 }; 1020 1021 struct mlx5_dump_mkey_mbox_out { 1022 struct mlx5_outbox_hdr hdr; 1023 __be32 mkey; 1024 }; 1025 1026 struct mlx5_mad_ifc_mbox_in { 1027 struct mlx5_inbox_hdr hdr; 1028 __be16 remote_lid; 1029 u8 rsvd0; 1030 u8 port; 1031 u8 rsvd1[4]; 1032 u8 data[256]; 1033 }; 1034 1035 struct mlx5_mad_ifc_mbox_out { 1036 struct mlx5_outbox_hdr hdr; 1037 u8 rsvd[8]; 1038 u8 data[256]; 1039 }; 1040 1041 struct mlx5_access_reg_mbox_in { 1042 struct mlx5_inbox_hdr hdr; 1043 u8 rsvd0[2]; 1044 __be16 register_id; 1045 __be32 arg; 1046 __be32 data[0]; 1047 }; 1048 1049 struct mlx5_access_reg_mbox_out { 1050 struct mlx5_outbox_hdr hdr; 1051 u8 rsvd[8]; 1052 __be32 data[0]; 1053 }; 1054 1055 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1056 1057 enum { 1058 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1059 }; 1060 1061 struct mlx5_allocate_psv_in { 1062 struct mlx5_inbox_hdr hdr; 1063 __be32 npsv_pd; 1064 __be32 rsvd_psv0; 1065 }; 1066 1067 struct mlx5_allocate_psv_out { 1068 struct mlx5_outbox_hdr hdr; 1069 u8 rsvd[8]; 1070 __be32 psv_idx[4]; 1071 }; 1072 1073 struct mlx5_destroy_psv_in { 1074 struct mlx5_inbox_hdr hdr; 1075 __be32 psv_number; 1076 u8 rsvd[4]; 1077 }; 1078 1079 struct mlx5_destroy_psv_out { 1080 struct mlx5_outbox_hdr hdr; 1081 u8 rsvd[8]; 1082 }; 1083 1084 #define MLX5_CMD_OP_MAX 0x920 1085 1086 enum { 1087 VPORT_STATE_DOWN = 0x0, 1088 VPORT_STATE_UP = 0x1, 1089 }; 1090 1091 enum { 1092 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 1093 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 1094 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 1095 }; 1096 1097 enum { 1098 MLX5_L3_PROT_TYPE_IPV4 = 0, 1099 MLX5_L3_PROT_TYPE_IPV6 = 1, 1100 }; 1101 1102 enum { 1103 MLX5_L4_PROT_TYPE_TCP = 0, 1104 MLX5_L4_PROT_TYPE_UDP = 1, 1105 }; 1106 1107 enum { 1108 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1109 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1110 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1111 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1112 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1113 }; 1114 1115 enum { 1116 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1117 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1118 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1119 1120 }; 1121 1122 enum { 1123 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1124 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1125 }; 1126 1127 enum { 1128 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1129 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1130 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1131 }; 1132 1133 enum mlx5_list_type { 1134 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1135 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1136 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1137 }; 1138 1139 enum { 1140 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1141 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1142 }; 1143 1144 /* MLX5 DEV CAPs */ 1145 1146 /* TODO: EAT.ME */ 1147 enum mlx5_cap_mode { 1148 HCA_CAP_OPMOD_GET_MAX = 0, 1149 HCA_CAP_OPMOD_GET_CUR = 1, 1150 }; 1151 1152 enum mlx5_cap_type { 1153 MLX5_CAP_GENERAL = 0, 1154 MLX5_CAP_ETHERNET_OFFLOADS, 1155 MLX5_CAP_ODP, 1156 MLX5_CAP_ATOMIC, 1157 MLX5_CAP_ROCE, 1158 MLX5_CAP_IPOIB_OFFLOADS, 1159 MLX5_CAP_EOIB_OFFLOADS, 1160 MLX5_CAP_FLOW_TABLE, 1161 MLX5_CAP_ESWITCH_FLOW_TABLE, 1162 MLX5_CAP_ESWITCH, 1163 /* NUM OF CAP Types */ 1164 MLX5_CAP_NUM 1165 }; 1166 1167 /* GET Dev Caps macros */ 1168 #define MLX5_CAP_GEN(mdev, cap) \ 1169 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1170 1171 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1172 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1173 1174 #define MLX5_CAP_ETH(mdev, cap) \ 1175 MLX5_GET(per_protocol_networking_offload_caps,\ 1176 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1177 1178 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1179 MLX5_GET(per_protocol_networking_offload_caps,\ 1180 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1181 1182 #define MLX5_CAP_ROCE(mdev, cap) \ 1183 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1184 1185 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1186 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1187 1188 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1189 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1190 1191 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1192 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1193 1194 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1195 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1196 1197 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1198 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1199 1200 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1201 MLX5_GET(flow_table_eswitch_cap, \ 1202 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1203 1204 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1205 MLX5_GET(flow_table_eswitch_cap, \ 1206 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1207 1208 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1209 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1210 1211 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1212 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1213 1214 #define MLX5_CAP_ESW(mdev, cap) \ 1215 MLX5_GET(e_switch_cap, \ 1216 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1217 1218 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1219 MLX5_GET(e_switch_cap, \ 1220 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1221 1222 #define MLX5_CAP_ODP(mdev, cap)\ 1223 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1224 1225 enum { 1226 MLX5_CMD_STAT_OK = 0x0, 1227 MLX5_CMD_STAT_INT_ERR = 0x1, 1228 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1229 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1230 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1231 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1232 MLX5_CMD_STAT_RES_BUSY = 0x6, 1233 MLX5_CMD_STAT_LIM_ERR = 0x8, 1234 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1235 MLX5_CMD_STAT_IX_ERR = 0xa, 1236 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1237 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1238 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1239 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1240 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1241 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1242 }; 1243 1244 enum { 1245 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1246 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1247 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1248 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1249 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1250 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1251 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11 1252 }; 1253 1254 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1255 { 1256 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1257 return 0; 1258 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1259 } 1260 1261 #define MLX5_BY_PASS_NUM_PRIOS 9 1262 1263 #endif /* MLX5_DEVICE_H */ 1264