1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 58 59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 67 68 /* insert a value to a struct */ 69 #define MLX5_SET(typ, p, fld, v) do { \ 70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 74 << __mlx5_dw_bit_off(typ, fld))); \ 75 } while (0) 76 77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 82 << __mlx5_dw_bit_off(typ, fld))); \ 83 } while (0) 84 85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 87 __mlx5_mask(typ, fld)) 88 89 #define MLX5_GET_PR(typ, p, fld) ({ \ 90 u32 ___t = MLX5_GET(typ, p, fld); \ 91 pr_debug(#fld " = 0x%x\n", ___t); \ 92 ___t; \ 93 }) 94 95 #define __MLX5_SET64(typ, p, fld, v) do { \ 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 98 } while (0) 99 100 #define MLX5_SET64(typ, p, fld, v) do { \ 101 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 102 __MLX5_SET64(typ, p, fld, v); \ 103 } while (0) 104 105 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 107 __MLX5_SET64(typ, p, fld[idx], v); \ 108 } while (0) 109 110 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 111 112 #define MLX5_GET64_PR(typ, p, fld) ({ \ 113 u64 ___t = MLX5_GET64(typ, p, fld); \ 114 pr_debug(#fld " = 0x%llx\n", ___t); \ 115 ___t; \ 116 }) 117 118 /* Big endian getters */ 119 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 120 __mlx5_64_off(typ, fld))) 121 122 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 123 type_t tmp; \ 124 switch (sizeof(tmp)) { \ 125 case sizeof(u8): \ 126 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 127 break; \ 128 case sizeof(u16): \ 129 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 130 break; \ 131 case sizeof(u32): \ 132 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 133 break; \ 134 case sizeof(u64): \ 135 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 136 break; \ 137 } \ 138 tmp; \ 139 }) 140 141 enum mlx5_inline_modes { 142 MLX5_INLINE_MODE_NONE, 143 MLX5_INLINE_MODE_L2, 144 MLX5_INLINE_MODE_IP, 145 MLX5_INLINE_MODE_TCP_UDP, 146 }; 147 148 enum { 149 MLX5_MAX_COMMANDS = 32, 150 MLX5_CMD_DATA_BLOCK_SIZE = 512, 151 MLX5_PCI_CMD_XPORT = 7, 152 MLX5_MKEY_BSF_OCTO_SIZE = 4, 153 MLX5_MAX_PSVS = 4, 154 }; 155 156 enum { 157 MLX5_EXTENDED_UD_AV = 0x80000000, 158 }; 159 160 enum { 161 MLX5_CQ_STATE_ARMED = 9, 162 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 163 MLX5_CQ_STATE_FIRED = 0xa, 164 }; 165 166 enum { 167 MLX5_STAT_RATE_OFFSET = 5, 168 }; 169 170 enum { 171 MLX5_INLINE_SEG = 0x80000000, 172 }; 173 174 enum { 175 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 176 }; 177 178 enum { 179 MLX5_MIN_PKEY_TABLE_SIZE = 128, 180 MLX5_MAX_LOG_PKEY_TABLE = 5, 181 }; 182 183 enum { 184 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 185 }; 186 187 enum { 188 MLX5_PFAULT_SUBTYPE_WQE = 0, 189 MLX5_PFAULT_SUBTYPE_RDMA = 1, 190 }; 191 192 enum { 193 MLX5_PERM_LOCAL_READ = 1 << 2, 194 MLX5_PERM_LOCAL_WRITE = 1 << 3, 195 MLX5_PERM_REMOTE_READ = 1 << 4, 196 MLX5_PERM_REMOTE_WRITE = 1 << 5, 197 MLX5_PERM_ATOMIC = 1 << 6, 198 MLX5_PERM_UMR_EN = 1 << 7, 199 }; 200 201 enum { 202 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 203 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 204 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 205 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 206 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 207 }; 208 209 enum { 210 MLX5_EN_RD = (u64)1, 211 MLX5_EN_WR = (u64)2 212 }; 213 214 enum { 215 MLX5_ADAPTER_PAGE_SHIFT = 12, 216 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 217 }; 218 219 enum { 220 MLX5_BFREGS_PER_UAR = 4, 221 MLX5_MAX_UARS = 1 << 8, 222 MLX5_NON_FP_BFREGS_PER_UAR = 2, 223 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - 224 MLX5_NON_FP_BFREGS_PER_UAR, 225 MLX5_MAX_BFREGS = MLX5_MAX_UARS * 226 MLX5_NON_FP_BFREGS_PER_UAR, 227 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, 228 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, 229 }; 230 231 enum { 232 MLX5_MKEY_MASK_LEN = 1ull << 0, 233 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 234 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 235 MLX5_MKEY_MASK_PD = 1ull << 7, 236 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 237 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 238 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 239 MLX5_MKEY_MASK_KEY = 1ull << 13, 240 MLX5_MKEY_MASK_QPN = 1ull << 14, 241 MLX5_MKEY_MASK_LR = 1ull << 17, 242 MLX5_MKEY_MASK_LW = 1ull << 18, 243 MLX5_MKEY_MASK_RR = 1ull << 19, 244 MLX5_MKEY_MASK_RW = 1ull << 20, 245 MLX5_MKEY_MASK_A = 1ull << 21, 246 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 247 MLX5_MKEY_MASK_FREE = 1ull << 29, 248 }; 249 250 enum { 251 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 252 253 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 254 MLX5_UMR_CHECK_FREE = (2 << 5), 255 256 MLX5_UMR_INLINE = (1 << 7), 257 }; 258 259 #define MLX5_UMR_MTT_ALIGNMENT 0x40 260 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 261 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 262 263 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 264 265 enum { 266 MLX5_EVENT_QUEUE_TYPE_QP = 0, 267 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 268 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 269 }; 270 271 enum mlx5_event { 272 MLX5_EVENT_TYPE_COMP = 0x0, 273 274 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 275 MLX5_EVENT_TYPE_COMM_EST = 0x02, 276 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 277 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 278 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 279 280 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 281 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 282 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 283 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 284 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 285 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 286 287 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 288 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 289 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 290 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, 291 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 292 MLX5_EVENT_TYPE_PPS_EVENT = 0x25, 293 294 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 295 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 296 297 MLX5_EVENT_TYPE_CMD = 0x0a, 298 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 299 300 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 301 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 302 }; 303 304 enum { 305 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 306 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 307 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 308 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 309 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 310 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 311 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 312 }; 313 314 enum { 315 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 316 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 317 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 318 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 319 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 320 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 321 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 322 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 323 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 324 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 325 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 326 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 327 }; 328 329 enum { 330 MLX5_ROCE_VERSION_1 = 0, 331 MLX5_ROCE_VERSION_2 = 2, 332 }; 333 334 enum { 335 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 336 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 337 }; 338 339 enum { 340 MLX5_ROCE_L3_TYPE_IPV4 = 0, 341 MLX5_ROCE_L3_TYPE_IPV6 = 1, 342 }; 343 344 enum { 345 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 346 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 347 }; 348 349 enum { 350 MLX5_OPCODE_NOP = 0x00, 351 MLX5_OPCODE_SEND_INVAL = 0x01, 352 MLX5_OPCODE_RDMA_WRITE = 0x08, 353 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 354 MLX5_OPCODE_SEND = 0x0a, 355 MLX5_OPCODE_SEND_IMM = 0x0b, 356 MLX5_OPCODE_LSO = 0x0e, 357 MLX5_OPCODE_RDMA_READ = 0x10, 358 MLX5_OPCODE_ATOMIC_CS = 0x11, 359 MLX5_OPCODE_ATOMIC_FA = 0x12, 360 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 361 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 362 MLX5_OPCODE_BIND_MW = 0x18, 363 MLX5_OPCODE_CONFIG_CMD = 0x1f, 364 365 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 366 MLX5_RECV_OPCODE_SEND = 0x01, 367 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 368 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 369 370 MLX5_CQE_OPCODE_ERROR = 0x1e, 371 MLX5_CQE_OPCODE_RESIZE = 0x16, 372 373 MLX5_OPCODE_SET_PSV = 0x20, 374 MLX5_OPCODE_GET_PSV = 0x21, 375 MLX5_OPCODE_CHECK_PSV = 0x22, 376 MLX5_OPCODE_RGET_PSV = 0x26, 377 MLX5_OPCODE_RCHECK_PSV = 0x27, 378 379 MLX5_OPCODE_UMR = 0x25, 380 381 }; 382 383 enum { 384 MLX5_SET_PORT_RESET_QKEY = 0, 385 MLX5_SET_PORT_GUID0 = 16, 386 MLX5_SET_PORT_NODE_GUID = 17, 387 MLX5_SET_PORT_SYS_GUID = 18, 388 MLX5_SET_PORT_GID_TABLE = 19, 389 MLX5_SET_PORT_PKEY_TABLE = 20, 390 }; 391 392 enum { 393 MLX5_BW_NO_LIMIT = 0, 394 MLX5_100_MBPS_UNIT = 3, 395 MLX5_GBPS_UNIT = 4, 396 }; 397 398 enum { 399 MLX5_MAX_PAGE_SHIFT = 31 400 }; 401 402 enum { 403 MLX5_CAP_OFF_CMDIF_CSUM = 46, 404 }; 405 406 enum { 407 /* 408 * Max wqe size for rdma read is 512 bytes, so this 409 * limits our max_sge_rd as the wqe needs to fit: 410 * - ctrl segment (16 bytes) 411 * - rdma segment (16 bytes) 412 * - scatter elements (16 bytes each) 413 */ 414 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 415 }; 416 417 enum mlx5_odp_transport_cap_bits { 418 MLX5_ODP_SUPPORT_SEND = 1 << 31, 419 MLX5_ODP_SUPPORT_RECV = 1 << 30, 420 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 421 MLX5_ODP_SUPPORT_READ = 1 << 28, 422 }; 423 424 struct mlx5_odp_caps { 425 char reserved[0x10]; 426 struct { 427 __be32 rc_odp_caps; 428 __be32 uc_odp_caps; 429 __be32 ud_odp_caps; 430 } per_transport_caps; 431 char reserved2[0xe4]; 432 }; 433 434 struct mlx5_cmd_layout { 435 u8 type; 436 u8 rsvd0[3]; 437 __be32 inlen; 438 __be64 in_ptr; 439 __be32 in[4]; 440 __be32 out[4]; 441 __be64 out_ptr; 442 __be32 outlen; 443 u8 token; 444 u8 sig; 445 u8 rsvd1; 446 u8 status_own; 447 }; 448 449 struct health_buffer { 450 __be32 assert_var[5]; 451 __be32 rsvd0[3]; 452 __be32 assert_exit_ptr; 453 __be32 assert_callra; 454 __be32 rsvd1[2]; 455 __be32 fw_ver; 456 __be32 hw_id; 457 __be32 rsvd2; 458 u8 irisc_index; 459 u8 synd; 460 __be16 ext_synd; 461 }; 462 463 struct mlx5_init_seg { 464 __be32 fw_rev; 465 __be32 cmdif_rev_fw_sub; 466 __be32 rsvd0[2]; 467 __be32 cmdq_addr_h; 468 __be32 cmdq_addr_l_sz; 469 __be32 cmd_dbell; 470 __be32 rsvd1[120]; 471 __be32 initializing; 472 struct health_buffer health; 473 __be32 rsvd2[880]; 474 __be32 internal_timer_h; 475 __be32 internal_timer_l; 476 __be32 rsvd3[2]; 477 __be32 health_counter; 478 __be32 rsvd4[1019]; 479 __be64 ieee1588_clk; 480 __be32 ieee1588_clk_type; 481 __be32 clr_intx; 482 }; 483 484 struct mlx5_eqe_comp { 485 __be32 reserved[6]; 486 __be32 cqn; 487 }; 488 489 struct mlx5_eqe_qp_srq { 490 __be32 reserved1[5]; 491 u8 type; 492 u8 reserved2[3]; 493 __be32 qp_srq_n; 494 }; 495 496 struct mlx5_eqe_cq_err { 497 __be32 cqn; 498 u8 reserved1[7]; 499 u8 syndrome; 500 }; 501 502 struct mlx5_eqe_port_state { 503 u8 reserved0[8]; 504 u8 port; 505 }; 506 507 struct mlx5_eqe_gpio { 508 __be32 reserved0[2]; 509 __be64 gpio_event; 510 }; 511 512 struct mlx5_eqe_congestion { 513 u8 type; 514 u8 rsvd0; 515 u8 congestion_level; 516 }; 517 518 struct mlx5_eqe_stall_vl { 519 u8 rsvd0[3]; 520 u8 port_vl; 521 }; 522 523 struct mlx5_eqe_cmd { 524 __be32 vector; 525 __be32 rsvd[6]; 526 }; 527 528 struct mlx5_eqe_page_req { 529 u8 rsvd0[2]; 530 __be16 func_id; 531 __be32 num_pages; 532 __be32 rsvd1[5]; 533 }; 534 535 struct mlx5_eqe_page_fault { 536 __be32 bytes_committed; 537 union { 538 struct { 539 u16 reserved1; 540 __be16 wqe_index; 541 u16 reserved2; 542 __be16 packet_length; 543 __be32 token; 544 u8 reserved4[8]; 545 __be32 pftype_wq; 546 } __packed wqe; 547 struct { 548 __be32 r_key; 549 u16 reserved1; 550 __be16 packet_length; 551 __be32 rdma_op_len; 552 __be64 rdma_va; 553 __be32 pftype_token; 554 } __packed rdma; 555 } __packed; 556 } __packed; 557 558 struct mlx5_eqe_vport_change { 559 u8 rsvd0[2]; 560 __be16 vport_num; 561 __be32 rsvd1[6]; 562 } __packed; 563 564 struct mlx5_eqe_port_module { 565 u8 reserved_at_0[1]; 566 u8 module; 567 u8 reserved_at_2[1]; 568 u8 module_status; 569 u8 reserved_at_4[2]; 570 u8 error_type; 571 } __packed; 572 573 struct mlx5_eqe_pps { 574 u8 rsvd0[3]; 575 u8 pin; 576 u8 rsvd1[4]; 577 union { 578 struct { 579 __be32 time_sec; 580 __be32 time_nsec; 581 }; 582 struct { 583 __be64 time_stamp; 584 }; 585 }; 586 u8 rsvd2[12]; 587 } __packed; 588 589 union ev_data { 590 __be32 raw[7]; 591 struct mlx5_eqe_cmd cmd; 592 struct mlx5_eqe_comp comp; 593 struct mlx5_eqe_qp_srq qp_srq; 594 struct mlx5_eqe_cq_err cq_err; 595 struct mlx5_eqe_port_state port; 596 struct mlx5_eqe_gpio gpio; 597 struct mlx5_eqe_congestion cong; 598 struct mlx5_eqe_stall_vl stall_vl; 599 struct mlx5_eqe_page_req req_pages; 600 struct mlx5_eqe_page_fault page_fault; 601 struct mlx5_eqe_vport_change vport_change; 602 struct mlx5_eqe_port_module port_module; 603 struct mlx5_eqe_pps pps; 604 } __packed; 605 606 struct mlx5_eqe { 607 u8 rsvd0; 608 u8 type; 609 u8 rsvd1; 610 u8 sub_type; 611 __be32 rsvd2[7]; 612 union ev_data data; 613 __be16 rsvd3; 614 u8 signature; 615 u8 owner; 616 } __packed; 617 618 struct mlx5_cmd_prot_block { 619 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 620 u8 rsvd0[48]; 621 __be64 next; 622 __be32 block_num; 623 u8 rsvd1; 624 u8 token; 625 u8 ctrl_sig; 626 u8 sig; 627 }; 628 629 enum { 630 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 631 }; 632 633 struct mlx5_err_cqe { 634 u8 rsvd0[32]; 635 __be32 srqn; 636 u8 rsvd1[18]; 637 u8 vendor_err_synd; 638 u8 syndrome; 639 __be32 s_wqe_opcode_qpn; 640 __be16 wqe_counter; 641 u8 signature; 642 u8 op_own; 643 }; 644 645 struct mlx5_cqe64 { 646 u8 outer_l3_tunneled; 647 u8 rsvd0; 648 __be16 wqe_id; 649 u8 lro_tcppsh_abort_dupack; 650 u8 lro_min_ttl; 651 __be16 lro_tcp_win; 652 __be32 lro_ack_seq_num; 653 __be32 rss_hash_result; 654 u8 rss_hash_type; 655 u8 ml_path; 656 u8 rsvd20[2]; 657 __be16 check_sum; 658 __be16 slid; 659 __be32 flags_rqpn; 660 u8 hds_ip_ext; 661 u8 l4_l3_hdr_type; 662 __be16 vlan_info; 663 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 664 __be32 imm_inval_pkey; 665 u8 rsvd40[4]; 666 __be32 byte_cnt; 667 __be32 timestamp_h; 668 __be32 timestamp_l; 669 __be32 sop_drop_qpn; 670 __be16 wqe_counter; 671 u8 signature; 672 u8 op_own; 673 }; 674 675 struct mlx5_mini_cqe8 { 676 union { 677 __be32 rx_hash_result; 678 struct { 679 __be16 checksum; 680 __be16 rsvd; 681 }; 682 struct { 683 __be16 wqe_counter; 684 u8 s_wqe_opcode; 685 u8 reserved; 686 } s_wqe_info; 687 }; 688 __be32 byte_cnt; 689 }; 690 691 enum { 692 MLX5_NO_INLINE_DATA, 693 MLX5_INLINE_DATA32_SEG, 694 MLX5_INLINE_DATA64_SEG, 695 MLX5_COMPRESSED, 696 }; 697 698 enum { 699 MLX5_CQE_FORMAT_CSUM = 0x1, 700 }; 701 702 #define MLX5_MINI_CQE_ARRAY_SIZE 8 703 704 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) 705 { 706 return (cqe->op_own >> 2) & 0x3; 707 } 708 709 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 710 { 711 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 712 } 713 714 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 715 { 716 return (cqe->l4_l3_hdr_type >> 4) & 0x7; 717 } 718 719 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe) 720 { 721 return (cqe->l4_l3_hdr_type >> 2) & 0x3; 722 } 723 724 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe) 725 { 726 return cqe->outer_l3_tunneled & 0x1; 727 } 728 729 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) 730 { 731 return !!(cqe->l4_l3_hdr_type & 0x1); 732 } 733 734 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 735 { 736 u32 hi, lo; 737 738 hi = be32_to_cpu(cqe->timestamp_h); 739 lo = be32_to_cpu(cqe->timestamp_l); 740 741 return (u64)lo | ((u64)hi << 32); 742 } 743 744 struct mpwrq_cqe_bc { 745 __be16 filler_consumed_strides; 746 __be16 byte_cnt; 747 }; 748 749 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) 750 { 751 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 752 753 return be16_to_cpu(bc->byte_cnt); 754 } 755 756 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) 757 { 758 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); 759 } 760 761 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) 762 { 763 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 764 765 return mpwrq_get_cqe_bc_consumed_strides(bc); 766 } 767 768 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) 769 { 770 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; 771 772 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); 773 } 774 775 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) 776 { 777 return be16_to_cpu(cqe->wqe_counter); 778 } 779 780 enum { 781 CQE_L4_HDR_TYPE_NONE = 0x0, 782 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 783 CQE_L4_HDR_TYPE_UDP = 0x2, 784 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 785 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 786 }; 787 788 enum { 789 CQE_RSS_HTYPE_IP = 0x3 << 6, 790 CQE_RSS_HTYPE_L4 = 0x3 << 2, 791 }; 792 793 enum { 794 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 795 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 796 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 797 }; 798 799 enum { 800 CQE_L2_OK = 1 << 0, 801 CQE_L3_OK = 1 << 1, 802 CQE_L4_OK = 1 << 2, 803 }; 804 805 struct mlx5_sig_err_cqe { 806 u8 rsvd0[16]; 807 __be32 expected_trans_sig; 808 __be32 actual_trans_sig; 809 __be32 expected_reftag; 810 __be32 actual_reftag; 811 __be16 syndrome; 812 u8 rsvd22[2]; 813 __be32 mkey; 814 __be64 err_offset; 815 u8 rsvd30[8]; 816 __be32 qpn; 817 u8 rsvd38[2]; 818 u8 signature; 819 u8 op_own; 820 }; 821 822 struct mlx5_wqe_srq_next_seg { 823 u8 rsvd0[2]; 824 __be16 next_wqe_index; 825 u8 signature; 826 u8 rsvd1[11]; 827 }; 828 829 union mlx5_ext_cqe { 830 struct ib_grh grh; 831 u8 inl[64]; 832 }; 833 834 struct mlx5_cqe128 { 835 union mlx5_ext_cqe inl_grh; 836 struct mlx5_cqe64 cqe64; 837 }; 838 839 enum { 840 MLX5_MKEY_STATUS_FREE = 1 << 6, 841 }; 842 843 enum { 844 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 845 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 846 MLX5_MKEY_BSF_EN = 1 << 30, 847 MLX5_MKEY_LEN64 = 1 << 31, 848 }; 849 850 struct mlx5_mkey_seg { 851 /* This is a two bit field occupying bits 31-30. 852 * bit 31 is always 0, 853 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 854 */ 855 u8 status; 856 u8 pcie_control; 857 u8 flags; 858 u8 version; 859 __be32 qpn_mkey7_0; 860 u8 rsvd1[4]; 861 __be32 flags_pd; 862 __be64 start_addr; 863 __be64 len; 864 __be32 bsfs_octo_size; 865 u8 rsvd2[16]; 866 __be32 xlt_oct_size; 867 u8 rsvd3[3]; 868 u8 log2_page_size; 869 u8 rsvd4[4]; 870 }; 871 872 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 873 874 enum { 875 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 876 }; 877 878 enum { 879 VPORT_STATE_DOWN = 0x0, 880 VPORT_STATE_UP = 0x1, 881 }; 882 883 enum { 884 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 885 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 886 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 887 }; 888 889 enum { 890 MLX5_L3_PROT_TYPE_IPV4 = 0, 891 MLX5_L3_PROT_TYPE_IPV6 = 1, 892 }; 893 894 enum { 895 MLX5_L4_PROT_TYPE_TCP = 0, 896 MLX5_L4_PROT_TYPE_UDP = 1, 897 }; 898 899 enum { 900 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 901 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 902 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 903 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 904 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 905 }; 906 907 enum { 908 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 909 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 910 MLX5_MATCH_INNER_HEADERS = 1 << 2, 911 912 }; 913 914 enum { 915 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 916 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 917 }; 918 919 enum { 920 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 921 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 922 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 923 }; 924 925 enum mlx5_list_type { 926 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 927 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 928 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 929 }; 930 931 enum { 932 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 933 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 934 }; 935 936 enum mlx5_wol_mode { 937 MLX5_WOL_DISABLE = 0, 938 MLX5_WOL_SECURED_MAGIC = 1 << 1, 939 MLX5_WOL_MAGIC = 1 << 2, 940 MLX5_WOL_ARP = 1 << 3, 941 MLX5_WOL_BROADCAST = 1 << 4, 942 MLX5_WOL_MULTICAST = 1 << 5, 943 MLX5_WOL_UNICAST = 1 << 6, 944 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 945 }; 946 947 /* MLX5 DEV CAPs */ 948 949 /* TODO: EAT.ME */ 950 enum mlx5_cap_mode { 951 HCA_CAP_OPMOD_GET_MAX = 0, 952 HCA_CAP_OPMOD_GET_CUR = 1, 953 }; 954 955 enum mlx5_cap_type { 956 MLX5_CAP_GENERAL = 0, 957 MLX5_CAP_ETHERNET_OFFLOADS, 958 MLX5_CAP_ODP, 959 MLX5_CAP_ATOMIC, 960 MLX5_CAP_ROCE, 961 MLX5_CAP_IPOIB_OFFLOADS, 962 MLX5_CAP_EOIB_OFFLOADS, 963 MLX5_CAP_FLOW_TABLE, 964 MLX5_CAP_ESWITCH_FLOW_TABLE, 965 MLX5_CAP_ESWITCH, 966 MLX5_CAP_RESERVED, 967 MLX5_CAP_VECTOR_CALC, 968 MLX5_CAP_QOS, 969 /* NUM OF CAP Types */ 970 MLX5_CAP_NUM 971 }; 972 973 enum mlx5_pcam_reg_groups { 974 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 975 }; 976 977 enum mlx5_pcam_feature_groups { 978 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 979 }; 980 981 enum mlx5_mcam_reg_groups { 982 MLX5_MCAM_REGS_FIRST_128 = 0x0, 983 }; 984 985 enum mlx5_mcam_feature_groups { 986 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 987 }; 988 989 /* GET Dev Caps macros */ 990 #define MLX5_CAP_GEN(mdev, cap) \ 991 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap) 992 993 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 994 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap) 995 996 #define MLX5_CAP_ETH(mdev, cap) \ 997 MLX5_GET(per_protocol_networking_offload_caps,\ 998 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 999 1000 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1001 MLX5_GET(per_protocol_networking_offload_caps,\ 1002 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1003 1004 #define MLX5_CAP_ROCE(mdev, cap) \ 1005 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap) 1006 1007 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1008 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap) 1009 1010 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1011 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap) 1012 1013 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1014 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap) 1015 1016 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1017 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap) 1018 1019 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1020 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap) 1021 1022 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ 1023 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) 1024 1025 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 1026 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 1027 1028 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ 1029 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) 1030 1031 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \ 1032 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap) 1033 1034 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ 1035 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1036 1037 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \ 1038 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap) 1039 1040 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1041 MLX5_GET(flow_table_eswitch_cap, \ 1042 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1043 1044 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1045 MLX5_GET(flow_table_eswitch_cap, \ 1046 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1047 1048 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1049 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1050 1051 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1052 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1053 1054 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1055 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1056 1057 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1058 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1059 1060 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1061 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1062 1063 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1064 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1065 1066 #define MLX5_CAP_ESW(mdev, cap) \ 1067 MLX5_GET(e_switch_cap, \ 1068 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap) 1069 1070 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1071 MLX5_GET(e_switch_cap, \ 1072 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap) 1073 1074 #define MLX5_CAP_ODP(mdev, cap)\ 1075 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap) 1076 1077 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \ 1078 MLX5_GET(vector_calc_cap, \ 1079 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap) 1080 1081 #define MLX5_CAP_QOS(mdev, cap)\ 1082 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap) 1083 1084 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1085 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1086 1087 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1088 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1089 1090 enum { 1091 MLX5_CMD_STAT_OK = 0x0, 1092 MLX5_CMD_STAT_INT_ERR = 0x1, 1093 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1094 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1095 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1096 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1097 MLX5_CMD_STAT_RES_BUSY = 0x6, 1098 MLX5_CMD_STAT_LIM_ERR = 0x8, 1099 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1100 MLX5_CMD_STAT_IX_ERR = 0xa, 1101 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1102 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1103 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1104 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1105 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1106 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1107 }; 1108 1109 enum { 1110 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1111 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1112 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1113 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1114 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1115 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1116 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1117 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1118 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1119 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1120 }; 1121 1122 enum { 1123 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1124 }; 1125 1126 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1127 { 1128 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1129 return 0; 1130 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1131 } 1132 1133 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 1134 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 1135 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 1136 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 1137 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 1138 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 1139 1140 #endif /* MLX5_DEVICE_H */ 1141