1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 58 59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 66 67 /* insert a value to a struct */ 68 #define MLX5_SET(typ, p, fld, v) do { \ 69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73 << __mlx5_dw_bit_off(typ, fld))); \ 74 } while (0) 75 76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 81 << __mlx5_dw_bit_off(typ, fld))); \ 82 } while (0) 83 84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 86 __mlx5_mask(typ, fld)) 87 88 #define MLX5_GET_PR(typ, p, fld) ({ \ 89 u32 ___t = MLX5_GET(typ, p, fld); \ 90 pr_debug(#fld " = 0x%x\n", ___t); \ 91 ___t; \ 92 }) 93 94 #define MLX5_SET64(typ, p, fld, v) do { \ 95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 98 } while (0) 99 100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 101 102 #define MLX5_GET64_PR(typ, p, fld) ({ \ 103 u64 ___t = MLX5_GET64(typ, p, fld); \ 104 pr_debug(#fld " = 0x%llx\n", ___t); \ 105 ___t; \ 106 }) 107 108 enum { 109 MLX5_MAX_COMMANDS = 32, 110 MLX5_CMD_DATA_BLOCK_SIZE = 512, 111 MLX5_PCI_CMD_XPORT = 7, 112 MLX5_MKEY_BSF_OCTO_SIZE = 4, 113 MLX5_MAX_PSVS = 4, 114 }; 115 116 enum { 117 MLX5_EXTENDED_UD_AV = 0x80000000, 118 }; 119 120 enum { 121 MLX5_CQ_STATE_ARMED = 9, 122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 123 MLX5_CQ_STATE_FIRED = 0xa, 124 }; 125 126 enum { 127 MLX5_STAT_RATE_OFFSET = 5, 128 }; 129 130 enum { 131 MLX5_INLINE_SEG = 0x80000000, 132 }; 133 134 enum { 135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 136 }; 137 138 enum { 139 MLX5_MIN_PKEY_TABLE_SIZE = 128, 140 MLX5_MAX_LOG_PKEY_TABLE = 5, 141 }; 142 143 enum { 144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 145 }; 146 147 enum { 148 MLX5_PFAULT_SUBTYPE_WQE = 0, 149 MLX5_PFAULT_SUBTYPE_RDMA = 1, 150 }; 151 152 enum { 153 MLX5_PERM_LOCAL_READ = 1 << 2, 154 MLX5_PERM_LOCAL_WRITE = 1 << 3, 155 MLX5_PERM_REMOTE_READ = 1 << 4, 156 MLX5_PERM_REMOTE_WRITE = 1 << 5, 157 MLX5_PERM_ATOMIC = 1 << 6, 158 MLX5_PERM_UMR_EN = 1 << 7, 159 }; 160 161 enum { 162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 167 }; 168 169 enum { 170 MLX5_ACCESS_MODE_PA = 0, 171 MLX5_ACCESS_MODE_MTT = 1, 172 MLX5_ACCESS_MODE_KLM = 2 173 }; 174 175 enum { 176 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 178 MLX5_MKEY_BSF_EN = 1 << 30, 179 MLX5_MKEY_LEN64 = 1 << 31, 180 }; 181 182 enum { 183 MLX5_EN_RD = (u64)1, 184 MLX5_EN_WR = (u64)2 185 }; 186 187 enum { 188 MLX5_BF_REGS_PER_PAGE = 4, 189 MLX5_MAX_UAR_PAGES = 1 << 8, 190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 192 }; 193 194 enum { 195 MLX5_MKEY_MASK_LEN = 1ull << 0, 196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 198 MLX5_MKEY_MASK_PD = 1ull << 7, 199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 202 MLX5_MKEY_MASK_KEY = 1ull << 13, 203 MLX5_MKEY_MASK_QPN = 1ull << 14, 204 MLX5_MKEY_MASK_LR = 1ull << 17, 205 MLX5_MKEY_MASK_LW = 1ull << 18, 206 MLX5_MKEY_MASK_RR = 1ull << 19, 207 MLX5_MKEY_MASK_RW = 1ull << 20, 208 MLX5_MKEY_MASK_A = 1ull << 21, 209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 210 MLX5_MKEY_MASK_FREE = 1ull << 29, 211 }; 212 213 enum { 214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 215 216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 217 MLX5_UMR_CHECK_FREE = (2 << 5), 218 219 MLX5_UMR_INLINE = (1 << 7), 220 }; 221 222 #define MLX5_UMR_MTT_ALIGNMENT 0x40 223 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 224 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 225 226 enum mlx5_event { 227 MLX5_EVENT_TYPE_COMP = 0x0, 228 229 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 230 MLX5_EVENT_TYPE_COMM_EST = 0x02, 231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 234 235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 241 242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 246 247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 249 250 MLX5_EVENT_TYPE_CMD = 0x0a, 251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 252 253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 254 }; 255 256 enum { 257 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 258 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 259 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 260 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 261 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 262 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 263 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 264 }; 265 266 enum { 267 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 268 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 269 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 270 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 272 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 273 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 274 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 275 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 276 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 277 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 278 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 279 }; 280 281 enum { 282 MLX5_OPCODE_NOP = 0x00, 283 MLX5_OPCODE_SEND_INVAL = 0x01, 284 MLX5_OPCODE_RDMA_WRITE = 0x08, 285 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 286 MLX5_OPCODE_SEND = 0x0a, 287 MLX5_OPCODE_SEND_IMM = 0x0b, 288 MLX5_OPCODE_LSO = 0x0e, 289 MLX5_OPCODE_RDMA_READ = 0x10, 290 MLX5_OPCODE_ATOMIC_CS = 0x11, 291 MLX5_OPCODE_ATOMIC_FA = 0x12, 292 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 293 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 294 MLX5_OPCODE_BIND_MW = 0x18, 295 MLX5_OPCODE_CONFIG_CMD = 0x1f, 296 297 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 298 MLX5_RECV_OPCODE_SEND = 0x01, 299 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 300 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 301 302 MLX5_CQE_OPCODE_ERROR = 0x1e, 303 MLX5_CQE_OPCODE_RESIZE = 0x16, 304 305 MLX5_OPCODE_SET_PSV = 0x20, 306 MLX5_OPCODE_GET_PSV = 0x21, 307 MLX5_OPCODE_CHECK_PSV = 0x22, 308 MLX5_OPCODE_RGET_PSV = 0x26, 309 MLX5_OPCODE_RCHECK_PSV = 0x27, 310 311 MLX5_OPCODE_UMR = 0x25, 312 313 }; 314 315 enum { 316 MLX5_SET_PORT_RESET_QKEY = 0, 317 MLX5_SET_PORT_GUID0 = 16, 318 MLX5_SET_PORT_NODE_GUID = 17, 319 MLX5_SET_PORT_SYS_GUID = 18, 320 MLX5_SET_PORT_GID_TABLE = 19, 321 MLX5_SET_PORT_PKEY_TABLE = 20, 322 }; 323 324 enum { 325 MLX5_MAX_PAGE_SHIFT = 31 326 }; 327 328 enum { 329 MLX5_ADAPTER_PAGE_SHIFT = 12, 330 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 331 }; 332 333 enum { 334 MLX5_CAP_OFF_CMDIF_CSUM = 46, 335 }; 336 337 struct mlx5_inbox_hdr { 338 __be16 opcode; 339 u8 rsvd[4]; 340 __be16 opmod; 341 }; 342 343 struct mlx5_outbox_hdr { 344 u8 status; 345 u8 rsvd[3]; 346 __be32 syndrome; 347 }; 348 349 struct mlx5_cmd_query_adapter_mbox_in { 350 struct mlx5_inbox_hdr hdr; 351 u8 rsvd[8]; 352 }; 353 354 struct mlx5_cmd_query_adapter_mbox_out { 355 struct mlx5_outbox_hdr hdr; 356 u8 rsvd0[24]; 357 u8 intapin; 358 u8 rsvd1[13]; 359 __be16 vsd_vendor_id; 360 u8 vsd[208]; 361 u8 vsd_psid[16]; 362 }; 363 364 enum mlx5_odp_transport_cap_bits { 365 MLX5_ODP_SUPPORT_SEND = 1 << 31, 366 MLX5_ODP_SUPPORT_RECV = 1 << 30, 367 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 368 MLX5_ODP_SUPPORT_READ = 1 << 28, 369 }; 370 371 struct mlx5_odp_caps { 372 char reserved[0x10]; 373 struct { 374 __be32 rc_odp_caps; 375 __be32 uc_odp_caps; 376 __be32 ud_odp_caps; 377 } per_transport_caps; 378 char reserved2[0xe4]; 379 }; 380 381 struct mlx5_cmd_init_hca_mbox_in { 382 struct mlx5_inbox_hdr hdr; 383 u8 rsvd0[2]; 384 __be16 profile; 385 u8 rsvd1[4]; 386 }; 387 388 struct mlx5_cmd_init_hca_mbox_out { 389 struct mlx5_outbox_hdr hdr; 390 u8 rsvd[8]; 391 }; 392 393 struct mlx5_cmd_teardown_hca_mbox_in { 394 struct mlx5_inbox_hdr hdr; 395 u8 rsvd0[2]; 396 __be16 profile; 397 u8 rsvd1[4]; 398 }; 399 400 struct mlx5_cmd_teardown_hca_mbox_out { 401 struct mlx5_outbox_hdr hdr; 402 u8 rsvd[8]; 403 }; 404 405 struct mlx5_cmd_layout { 406 u8 type; 407 u8 rsvd0[3]; 408 __be32 inlen; 409 __be64 in_ptr; 410 __be32 in[4]; 411 __be32 out[4]; 412 __be64 out_ptr; 413 __be32 outlen; 414 u8 token; 415 u8 sig; 416 u8 rsvd1; 417 u8 status_own; 418 }; 419 420 421 struct health_buffer { 422 __be32 assert_var[5]; 423 __be32 rsvd0[3]; 424 __be32 assert_exit_ptr; 425 __be32 assert_callra; 426 __be32 rsvd1[2]; 427 __be32 fw_ver; 428 __be32 hw_id; 429 __be32 rsvd2; 430 u8 irisc_index; 431 u8 synd; 432 __be16 ext_sync; 433 }; 434 435 struct mlx5_init_seg { 436 __be32 fw_rev; 437 __be32 cmdif_rev_fw_sub; 438 __be32 rsvd0[2]; 439 __be32 cmdq_addr_h; 440 __be32 cmdq_addr_l_sz; 441 __be32 cmd_dbell; 442 __be32 rsvd1[121]; 443 struct health_buffer health; 444 __be32 rsvd2[884]; 445 __be32 health_counter; 446 __be32 rsvd3[1019]; 447 __be64 ieee1588_clk; 448 __be32 ieee1588_clk_type; 449 __be32 clr_intx; 450 }; 451 452 struct mlx5_eqe_comp { 453 __be32 reserved[6]; 454 __be32 cqn; 455 }; 456 457 struct mlx5_eqe_qp_srq { 458 __be32 reserved[6]; 459 __be32 qp_srq_n; 460 }; 461 462 struct mlx5_eqe_cq_err { 463 __be32 cqn; 464 u8 reserved1[7]; 465 u8 syndrome; 466 }; 467 468 struct mlx5_eqe_port_state { 469 u8 reserved0[8]; 470 u8 port; 471 }; 472 473 struct mlx5_eqe_gpio { 474 __be32 reserved0[2]; 475 __be64 gpio_event; 476 }; 477 478 struct mlx5_eqe_congestion { 479 u8 type; 480 u8 rsvd0; 481 u8 congestion_level; 482 }; 483 484 struct mlx5_eqe_stall_vl { 485 u8 rsvd0[3]; 486 u8 port_vl; 487 }; 488 489 struct mlx5_eqe_cmd { 490 __be32 vector; 491 __be32 rsvd[6]; 492 }; 493 494 struct mlx5_eqe_page_req { 495 u8 rsvd0[2]; 496 __be16 func_id; 497 __be32 num_pages; 498 __be32 rsvd1[5]; 499 }; 500 501 struct mlx5_eqe_page_fault { 502 __be32 bytes_committed; 503 union { 504 struct { 505 u16 reserved1; 506 __be16 wqe_index; 507 u16 reserved2; 508 __be16 packet_length; 509 u8 reserved3[12]; 510 } __packed wqe; 511 struct { 512 __be32 r_key; 513 u16 reserved1; 514 __be16 packet_length; 515 __be32 rdma_op_len; 516 __be64 rdma_va; 517 } __packed rdma; 518 } __packed; 519 __be32 flags_qpn; 520 } __packed; 521 522 union ev_data { 523 __be32 raw[7]; 524 struct mlx5_eqe_cmd cmd; 525 struct mlx5_eqe_comp comp; 526 struct mlx5_eqe_qp_srq qp_srq; 527 struct mlx5_eqe_cq_err cq_err; 528 struct mlx5_eqe_port_state port; 529 struct mlx5_eqe_gpio gpio; 530 struct mlx5_eqe_congestion cong; 531 struct mlx5_eqe_stall_vl stall_vl; 532 struct mlx5_eqe_page_req req_pages; 533 struct mlx5_eqe_page_fault page_fault; 534 } __packed; 535 536 struct mlx5_eqe { 537 u8 rsvd0; 538 u8 type; 539 u8 rsvd1; 540 u8 sub_type; 541 __be32 rsvd2[7]; 542 union ev_data data; 543 __be16 rsvd3; 544 u8 signature; 545 u8 owner; 546 } __packed; 547 548 struct mlx5_cmd_prot_block { 549 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 550 u8 rsvd0[48]; 551 __be64 next; 552 __be32 block_num; 553 u8 rsvd1; 554 u8 token; 555 u8 ctrl_sig; 556 u8 sig; 557 }; 558 559 enum { 560 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 561 }; 562 563 struct mlx5_err_cqe { 564 u8 rsvd0[32]; 565 __be32 srqn; 566 u8 rsvd1[18]; 567 u8 vendor_err_synd; 568 u8 syndrome; 569 __be32 s_wqe_opcode_qpn; 570 __be16 wqe_counter; 571 u8 signature; 572 u8 op_own; 573 }; 574 575 struct mlx5_cqe64 { 576 u8 rsvd0[4]; 577 u8 lro_tcppsh_abort_dupack; 578 u8 lro_min_ttl; 579 __be16 lro_tcp_win; 580 __be32 lro_ack_seq_num; 581 __be32 rss_hash_result; 582 u8 rss_hash_type; 583 u8 ml_path; 584 u8 rsvd20[2]; 585 __be16 check_sum; 586 __be16 slid; 587 __be32 flags_rqpn; 588 u8 hds_ip_ext; 589 u8 l4_hdr_type_etc; 590 __be16 vlan_info; 591 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 592 __be32 imm_inval_pkey; 593 u8 rsvd40[4]; 594 __be32 byte_cnt; 595 __be64 timestamp; 596 __be32 sop_drop_qpn; 597 __be16 wqe_counter; 598 u8 signature; 599 u8 op_own; 600 }; 601 602 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 603 { 604 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 605 } 606 607 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 608 { 609 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 610 } 611 612 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) 613 { 614 return !!(cqe->l4_hdr_type_etc & 0x1); 615 } 616 617 enum { 618 CQE_L4_HDR_TYPE_NONE = 0x0, 619 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 620 CQE_L4_HDR_TYPE_UDP = 0x2, 621 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 622 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 623 }; 624 625 enum { 626 CQE_RSS_HTYPE_IP = 0x3 << 6, 627 CQE_RSS_HTYPE_L4 = 0x3 << 2, 628 }; 629 630 enum { 631 CQE_L2_OK = 1 << 0, 632 CQE_L3_OK = 1 << 1, 633 CQE_L4_OK = 1 << 2, 634 }; 635 636 struct mlx5_sig_err_cqe { 637 u8 rsvd0[16]; 638 __be32 expected_trans_sig; 639 __be32 actual_trans_sig; 640 __be32 expected_reftag; 641 __be32 actual_reftag; 642 __be16 syndrome; 643 u8 rsvd22[2]; 644 __be32 mkey; 645 __be64 err_offset; 646 u8 rsvd30[8]; 647 __be32 qpn; 648 u8 rsvd38[2]; 649 u8 signature; 650 u8 op_own; 651 }; 652 653 struct mlx5_wqe_srq_next_seg { 654 u8 rsvd0[2]; 655 __be16 next_wqe_index; 656 u8 signature; 657 u8 rsvd1[11]; 658 }; 659 660 union mlx5_ext_cqe { 661 struct ib_grh grh; 662 u8 inl[64]; 663 }; 664 665 struct mlx5_cqe128 { 666 union mlx5_ext_cqe inl_grh; 667 struct mlx5_cqe64 cqe64; 668 }; 669 670 struct mlx5_srq_ctx { 671 u8 state_log_sz; 672 u8 rsvd0[3]; 673 __be32 flags_xrcd; 674 __be32 pgoff_cqn; 675 u8 rsvd1[4]; 676 u8 log_pg_sz; 677 u8 rsvd2[7]; 678 __be32 pd; 679 __be16 lwm; 680 __be16 wqe_cnt; 681 u8 rsvd3[8]; 682 __be64 db_record; 683 }; 684 685 struct mlx5_create_srq_mbox_in { 686 struct mlx5_inbox_hdr hdr; 687 __be32 input_srqn; 688 u8 rsvd0[4]; 689 struct mlx5_srq_ctx ctx; 690 u8 rsvd1[208]; 691 __be64 pas[0]; 692 }; 693 694 struct mlx5_create_srq_mbox_out { 695 struct mlx5_outbox_hdr hdr; 696 __be32 srqn; 697 u8 rsvd[4]; 698 }; 699 700 struct mlx5_destroy_srq_mbox_in { 701 struct mlx5_inbox_hdr hdr; 702 __be32 srqn; 703 u8 rsvd[4]; 704 }; 705 706 struct mlx5_destroy_srq_mbox_out { 707 struct mlx5_outbox_hdr hdr; 708 u8 rsvd[8]; 709 }; 710 711 struct mlx5_query_srq_mbox_in { 712 struct mlx5_inbox_hdr hdr; 713 __be32 srqn; 714 u8 rsvd0[4]; 715 }; 716 717 struct mlx5_query_srq_mbox_out { 718 struct mlx5_outbox_hdr hdr; 719 u8 rsvd0[8]; 720 struct mlx5_srq_ctx ctx; 721 u8 rsvd1[32]; 722 __be64 pas[0]; 723 }; 724 725 struct mlx5_arm_srq_mbox_in { 726 struct mlx5_inbox_hdr hdr; 727 __be32 srqn; 728 __be16 rsvd; 729 __be16 lwm; 730 }; 731 732 struct mlx5_arm_srq_mbox_out { 733 struct mlx5_outbox_hdr hdr; 734 u8 rsvd[8]; 735 }; 736 737 struct mlx5_cq_context { 738 u8 status; 739 u8 cqe_sz_flags; 740 u8 st; 741 u8 rsvd3; 742 u8 rsvd4[6]; 743 __be16 page_offset; 744 __be32 log_sz_usr_page; 745 __be16 cq_period; 746 __be16 cq_max_count; 747 __be16 rsvd20; 748 __be16 c_eqn; 749 u8 log_pg_sz; 750 u8 rsvd25[7]; 751 __be32 last_notified_index; 752 __be32 solicit_producer_index; 753 __be32 consumer_counter; 754 __be32 producer_counter; 755 u8 rsvd48[8]; 756 __be64 db_record_addr; 757 }; 758 759 struct mlx5_create_cq_mbox_in { 760 struct mlx5_inbox_hdr hdr; 761 __be32 input_cqn; 762 u8 rsvdx[4]; 763 struct mlx5_cq_context ctx; 764 u8 rsvd6[192]; 765 __be64 pas[0]; 766 }; 767 768 struct mlx5_create_cq_mbox_out { 769 struct mlx5_outbox_hdr hdr; 770 __be32 cqn; 771 u8 rsvd0[4]; 772 }; 773 774 struct mlx5_destroy_cq_mbox_in { 775 struct mlx5_inbox_hdr hdr; 776 __be32 cqn; 777 u8 rsvd0[4]; 778 }; 779 780 struct mlx5_destroy_cq_mbox_out { 781 struct mlx5_outbox_hdr hdr; 782 u8 rsvd0[8]; 783 }; 784 785 struct mlx5_query_cq_mbox_in { 786 struct mlx5_inbox_hdr hdr; 787 __be32 cqn; 788 u8 rsvd0[4]; 789 }; 790 791 struct mlx5_query_cq_mbox_out { 792 struct mlx5_outbox_hdr hdr; 793 u8 rsvd0[8]; 794 struct mlx5_cq_context ctx; 795 u8 rsvd6[16]; 796 __be64 pas[0]; 797 }; 798 799 struct mlx5_modify_cq_mbox_in { 800 struct mlx5_inbox_hdr hdr; 801 __be32 cqn; 802 __be32 field_select; 803 struct mlx5_cq_context ctx; 804 u8 rsvd[192]; 805 __be64 pas[0]; 806 }; 807 808 struct mlx5_modify_cq_mbox_out { 809 struct mlx5_outbox_hdr hdr; 810 u8 rsvd[8]; 811 }; 812 813 struct mlx5_enable_hca_mbox_in { 814 struct mlx5_inbox_hdr hdr; 815 u8 rsvd[8]; 816 }; 817 818 struct mlx5_enable_hca_mbox_out { 819 struct mlx5_outbox_hdr hdr; 820 u8 rsvd[8]; 821 }; 822 823 struct mlx5_disable_hca_mbox_in { 824 struct mlx5_inbox_hdr hdr; 825 u8 rsvd[8]; 826 }; 827 828 struct mlx5_disable_hca_mbox_out { 829 struct mlx5_outbox_hdr hdr; 830 u8 rsvd[8]; 831 }; 832 833 struct mlx5_eq_context { 834 u8 status; 835 u8 ec_oi; 836 u8 st; 837 u8 rsvd2[7]; 838 __be16 page_pffset; 839 __be32 log_sz_usr_page; 840 u8 rsvd3[7]; 841 u8 intr; 842 u8 log_page_size; 843 u8 rsvd4[15]; 844 __be32 consumer_counter; 845 __be32 produser_counter; 846 u8 rsvd5[16]; 847 }; 848 849 struct mlx5_create_eq_mbox_in { 850 struct mlx5_inbox_hdr hdr; 851 u8 rsvd0[3]; 852 u8 input_eqn; 853 u8 rsvd1[4]; 854 struct mlx5_eq_context ctx; 855 u8 rsvd2[8]; 856 __be64 events_mask; 857 u8 rsvd3[176]; 858 __be64 pas[0]; 859 }; 860 861 struct mlx5_create_eq_mbox_out { 862 struct mlx5_outbox_hdr hdr; 863 u8 rsvd0[3]; 864 u8 eq_number; 865 u8 rsvd1[4]; 866 }; 867 868 struct mlx5_destroy_eq_mbox_in { 869 struct mlx5_inbox_hdr hdr; 870 u8 rsvd0[3]; 871 u8 eqn; 872 u8 rsvd1[4]; 873 }; 874 875 struct mlx5_destroy_eq_mbox_out { 876 struct mlx5_outbox_hdr hdr; 877 u8 rsvd[8]; 878 }; 879 880 struct mlx5_map_eq_mbox_in { 881 struct mlx5_inbox_hdr hdr; 882 __be64 mask; 883 u8 mu; 884 u8 rsvd0[2]; 885 u8 eqn; 886 u8 rsvd1[24]; 887 }; 888 889 struct mlx5_map_eq_mbox_out { 890 struct mlx5_outbox_hdr hdr; 891 u8 rsvd[8]; 892 }; 893 894 struct mlx5_query_eq_mbox_in { 895 struct mlx5_inbox_hdr hdr; 896 u8 rsvd0[3]; 897 u8 eqn; 898 u8 rsvd1[4]; 899 }; 900 901 struct mlx5_query_eq_mbox_out { 902 struct mlx5_outbox_hdr hdr; 903 u8 rsvd[8]; 904 struct mlx5_eq_context ctx; 905 }; 906 907 enum { 908 MLX5_MKEY_STATUS_FREE = 1 << 6, 909 }; 910 911 struct mlx5_mkey_seg { 912 /* This is a two bit field occupying bits 31-30. 913 * bit 31 is always 0, 914 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 915 */ 916 u8 status; 917 u8 pcie_control; 918 u8 flags; 919 u8 version; 920 __be32 qpn_mkey7_0; 921 u8 rsvd1[4]; 922 __be32 flags_pd; 923 __be64 start_addr; 924 __be64 len; 925 __be32 bsfs_octo_size; 926 u8 rsvd2[16]; 927 __be32 xlt_oct_size; 928 u8 rsvd3[3]; 929 u8 log2_page_size; 930 u8 rsvd4[4]; 931 }; 932 933 struct mlx5_query_special_ctxs_mbox_in { 934 struct mlx5_inbox_hdr hdr; 935 u8 rsvd[8]; 936 }; 937 938 struct mlx5_query_special_ctxs_mbox_out { 939 struct mlx5_outbox_hdr hdr; 940 __be32 dump_fill_mkey; 941 __be32 reserved_lkey; 942 }; 943 944 struct mlx5_create_mkey_mbox_in { 945 struct mlx5_inbox_hdr hdr; 946 __be32 input_mkey_index; 947 __be32 flags; 948 struct mlx5_mkey_seg seg; 949 u8 rsvd1[16]; 950 __be32 xlat_oct_act_size; 951 __be32 rsvd2; 952 u8 rsvd3[168]; 953 __be64 pas[0]; 954 }; 955 956 struct mlx5_create_mkey_mbox_out { 957 struct mlx5_outbox_hdr hdr; 958 __be32 mkey; 959 u8 rsvd[4]; 960 }; 961 962 struct mlx5_destroy_mkey_mbox_in { 963 struct mlx5_inbox_hdr hdr; 964 __be32 mkey; 965 u8 rsvd[4]; 966 }; 967 968 struct mlx5_destroy_mkey_mbox_out { 969 struct mlx5_outbox_hdr hdr; 970 u8 rsvd[8]; 971 }; 972 973 struct mlx5_query_mkey_mbox_in { 974 struct mlx5_inbox_hdr hdr; 975 __be32 mkey; 976 }; 977 978 struct mlx5_query_mkey_mbox_out { 979 struct mlx5_outbox_hdr hdr; 980 __be64 pas[0]; 981 }; 982 983 struct mlx5_modify_mkey_mbox_in { 984 struct mlx5_inbox_hdr hdr; 985 __be32 mkey; 986 __be64 pas[0]; 987 }; 988 989 struct mlx5_modify_mkey_mbox_out { 990 struct mlx5_outbox_hdr hdr; 991 u8 rsvd[8]; 992 }; 993 994 struct mlx5_dump_mkey_mbox_in { 995 struct mlx5_inbox_hdr hdr; 996 }; 997 998 struct mlx5_dump_mkey_mbox_out { 999 struct mlx5_outbox_hdr hdr; 1000 __be32 mkey; 1001 }; 1002 1003 struct mlx5_mad_ifc_mbox_in { 1004 struct mlx5_inbox_hdr hdr; 1005 __be16 remote_lid; 1006 u8 rsvd0; 1007 u8 port; 1008 u8 rsvd1[4]; 1009 u8 data[256]; 1010 }; 1011 1012 struct mlx5_mad_ifc_mbox_out { 1013 struct mlx5_outbox_hdr hdr; 1014 u8 rsvd[8]; 1015 u8 data[256]; 1016 }; 1017 1018 struct mlx5_access_reg_mbox_in { 1019 struct mlx5_inbox_hdr hdr; 1020 u8 rsvd0[2]; 1021 __be16 register_id; 1022 __be32 arg; 1023 __be32 data[0]; 1024 }; 1025 1026 struct mlx5_access_reg_mbox_out { 1027 struct mlx5_outbox_hdr hdr; 1028 u8 rsvd[8]; 1029 __be32 data[0]; 1030 }; 1031 1032 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1033 1034 enum { 1035 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1036 }; 1037 1038 struct mlx5_allocate_psv_in { 1039 struct mlx5_inbox_hdr hdr; 1040 __be32 npsv_pd; 1041 __be32 rsvd_psv0; 1042 }; 1043 1044 struct mlx5_allocate_psv_out { 1045 struct mlx5_outbox_hdr hdr; 1046 u8 rsvd[8]; 1047 __be32 psv_idx[4]; 1048 }; 1049 1050 struct mlx5_destroy_psv_in { 1051 struct mlx5_inbox_hdr hdr; 1052 __be32 psv_number; 1053 u8 rsvd[4]; 1054 }; 1055 1056 struct mlx5_destroy_psv_out { 1057 struct mlx5_outbox_hdr hdr; 1058 u8 rsvd[8]; 1059 }; 1060 1061 #define MLX5_CMD_OP_MAX 0x920 1062 1063 enum { 1064 VPORT_STATE_DOWN = 0x0, 1065 VPORT_STATE_UP = 0x1, 1066 }; 1067 1068 enum { 1069 MLX5_L3_PROT_TYPE_IPV4 = 0, 1070 MLX5_L3_PROT_TYPE_IPV6 = 1, 1071 }; 1072 1073 enum { 1074 MLX5_L4_PROT_TYPE_TCP = 0, 1075 MLX5_L4_PROT_TYPE_UDP = 1, 1076 }; 1077 1078 enum { 1079 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1080 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1081 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1082 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1083 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1084 }; 1085 1086 enum { 1087 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1088 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1089 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1090 1091 }; 1092 1093 enum { 1094 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1095 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1096 }; 1097 1098 enum { 1099 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1100 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1101 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1102 }; 1103 1104 enum { 1105 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1106 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1107 }; 1108 1109 /* MLX5 DEV CAPs */ 1110 1111 /* TODO: EAT.ME */ 1112 enum mlx5_cap_mode { 1113 HCA_CAP_OPMOD_GET_MAX = 0, 1114 HCA_CAP_OPMOD_GET_CUR = 1, 1115 }; 1116 1117 enum mlx5_cap_type { 1118 MLX5_CAP_GENERAL = 0, 1119 MLX5_CAP_ETHERNET_OFFLOADS, 1120 MLX5_CAP_ODP, 1121 MLX5_CAP_ATOMIC, 1122 MLX5_CAP_ROCE, 1123 MLX5_CAP_IPOIB_OFFLOADS, 1124 MLX5_CAP_EOIB_OFFLOADS, 1125 MLX5_CAP_FLOW_TABLE, 1126 /* NUM OF CAP Types */ 1127 MLX5_CAP_NUM 1128 }; 1129 1130 /* GET Dev Caps macros */ 1131 #define MLX5_CAP_GEN(mdev, cap) \ 1132 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1133 1134 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1135 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1136 1137 #define MLX5_CAP_ETH(mdev, cap) \ 1138 MLX5_GET(per_protocol_networking_offload_caps,\ 1139 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1140 1141 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1142 MLX5_GET(per_protocol_networking_offload_caps,\ 1143 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1144 1145 #define MLX5_CAP_ROCE(mdev, cap) \ 1146 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1147 1148 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1149 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1150 1151 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1152 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1153 1154 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1155 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1156 1157 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1158 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1159 1160 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1161 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1162 1163 #define MLX5_CAP_ODP(mdev, cap)\ 1164 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1165 1166 enum { 1167 MLX5_CMD_STAT_OK = 0x0, 1168 MLX5_CMD_STAT_INT_ERR = 0x1, 1169 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1170 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1171 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1172 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1173 MLX5_CMD_STAT_RES_BUSY = 0x6, 1174 MLX5_CMD_STAT_LIM_ERR = 0x8, 1175 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1176 MLX5_CMD_STAT_IX_ERR = 0xa, 1177 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1178 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1179 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1180 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1181 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1182 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1183 }; 1184 1185 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1186 { 1187 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1188 return 0; 1189 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1190 } 1191 1192 #endif /* MLX5_DEVICE_H */ 1193