1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_DEVICE_H 34 #define MLX5_DEVICE_H 35 36 #include <linux/types.h> 37 #include <rdma/ib_verbs.h> 38 #include <linux/mlx5/mlx5_ifc.h> 39 40 #if defined(__LITTLE_ENDIAN) 41 #define MLX5_SET_HOST_ENDIANNESS 0 42 #elif defined(__BIG_ENDIAN) 43 #define MLX5_SET_HOST_ENDIANNESS 0x80 44 #else 45 #error Host endianness not defined 46 #endif 47 48 /* helper macros */ 49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld))) 52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 58 59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 66 67 /* insert a value to a struct */ 68 #define MLX5_SET(typ, p, fld, v) do { \ 69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73 << __mlx5_dw_bit_off(typ, fld))); \ 74 } while (0) 75 76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 81 << __mlx5_dw_bit_off(typ, fld))); \ 82 } while (0) 83 84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 86 __mlx5_mask(typ, fld)) 87 88 #define MLX5_GET_PR(typ, p, fld) ({ \ 89 u32 ___t = MLX5_GET(typ, p, fld); \ 90 pr_debug(#fld " = 0x%x\n", ___t); \ 91 ___t; \ 92 }) 93 94 #define MLX5_SET64(typ, p, fld, v) do { \ 95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 98 } while (0) 99 100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 101 102 #define MLX5_GET64_PR(typ, p, fld) ({ \ 103 u64 ___t = MLX5_GET64(typ, p, fld); \ 104 pr_debug(#fld " = 0x%llx\n", ___t); \ 105 ___t; \ 106 }) 107 108 enum { 109 MLX5_MAX_COMMANDS = 32, 110 MLX5_CMD_DATA_BLOCK_SIZE = 512, 111 MLX5_PCI_CMD_XPORT = 7, 112 MLX5_MKEY_BSF_OCTO_SIZE = 4, 113 MLX5_MAX_PSVS = 4, 114 }; 115 116 enum { 117 MLX5_EXTENDED_UD_AV = 0x80000000, 118 }; 119 120 enum { 121 MLX5_CQ_STATE_ARMED = 9, 122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, 123 MLX5_CQ_STATE_FIRED = 0xa, 124 }; 125 126 enum { 127 MLX5_STAT_RATE_OFFSET = 5, 128 }; 129 130 enum { 131 MLX5_INLINE_SEG = 0x80000000, 132 }; 133 134 enum { 135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 136 }; 137 138 enum { 139 MLX5_MIN_PKEY_TABLE_SIZE = 128, 140 MLX5_MAX_LOG_PKEY_TABLE = 5, 141 }; 142 143 enum { 144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 145 }; 146 147 enum { 148 MLX5_PFAULT_SUBTYPE_WQE = 0, 149 MLX5_PFAULT_SUBTYPE_RDMA = 1, 150 }; 151 152 enum { 153 MLX5_PERM_LOCAL_READ = 1 << 2, 154 MLX5_PERM_LOCAL_WRITE = 1 << 3, 155 MLX5_PERM_REMOTE_READ = 1 << 4, 156 MLX5_PERM_REMOTE_WRITE = 1 << 5, 157 MLX5_PERM_ATOMIC = 1 << 6, 158 MLX5_PERM_UMR_EN = 1 << 7, 159 }; 160 161 enum { 162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 167 }; 168 169 enum { 170 MLX5_ACCESS_MODE_PA = 0, 171 MLX5_ACCESS_MODE_MTT = 1, 172 MLX5_ACCESS_MODE_KLM = 2 173 }; 174 175 enum { 176 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 178 MLX5_MKEY_BSF_EN = 1 << 30, 179 MLX5_MKEY_LEN64 = 1 << 31, 180 }; 181 182 enum { 183 MLX5_EN_RD = (u64)1, 184 MLX5_EN_WR = (u64)2 185 }; 186 187 enum { 188 MLX5_BF_REGS_PER_PAGE = 4, 189 MLX5_MAX_UAR_PAGES = 1 << 8, 190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 192 }; 193 194 enum { 195 MLX5_MKEY_MASK_LEN = 1ull << 0, 196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 198 MLX5_MKEY_MASK_PD = 1ull << 7, 199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 202 MLX5_MKEY_MASK_KEY = 1ull << 13, 203 MLX5_MKEY_MASK_QPN = 1ull << 14, 204 MLX5_MKEY_MASK_LR = 1ull << 17, 205 MLX5_MKEY_MASK_LW = 1ull << 18, 206 MLX5_MKEY_MASK_RR = 1ull << 19, 207 MLX5_MKEY_MASK_RW = 1ull << 20, 208 MLX5_MKEY_MASK_A = 1ull << 21, 209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 210 MLX5_MKEY_MASK_FREE = 1ull << 29, 211 }; 212 213 enum { 214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 215 216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 217 MLX5_UMR_CHECK_FREE = (2 << 5), 218 219 MLX5_UMR_INLINE = (1 << 7), 220 }; 221 222 #define MLX5_UMR_MTT_ALIGNMENT 0x40 223 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 224 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 225 226 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) 227 228 enum { 229 MLX5_EVENT_QUEUE_TYPE_QP = 0, 230 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 231 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 232 }; 233 234 enum mlx5_event { 235 MLX5_EVENT_TYPE_COMP = 0x0, 236 237 MLX5_EVENT_TYPE_PATH_MIG = 0x01, 238 MLX5_EVENT_TYPE_COMM_EST = 0x02, 239 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, 240 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 241 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 242 243 MLX5_EVENT_TYPE_CQ_ERROR = 0x04, 244 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 245 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 246 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 247 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 248 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 249 250 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, 251 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, 252 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 253 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 254 255 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 256 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 257 258 MLX5_EVENT_TYPE_CMD = 0x0a, 259 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 260 261 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 262 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 263 }; 264 265 enum { 266 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 267 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 268 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 269 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 270 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 271 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 272 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 273 }; 274 275 enum { 276 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 277 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 278 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 279 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 280 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 281 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 282 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24, 283 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 284 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 285 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 286 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 287 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 288 }; 289 290 enum { 291 MLX5_ROCE_VERSION_1 = 0, 292 MLX5_ROCE_VERSION_2 = 2, 293 }; 294 295 enum { 296 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 297 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 298 }; 299 300 enum { 301 MLX5_ROCE_L3_TYPE_IPV4 = 0, 302 MLX5_ROCE_L3_TYPE_IPV6 = 1, 303 }; 304 305 enum { 306 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 307 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 308 }; 309 310 enum { 311 MLX5_OPCODE_NOP = 0x00, 312 MLX5_OPCODE_SEND_INVAL = 0x01, 313 MLX5_OPCODE_RDMA_WRITE = 0x08, 314 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 315 MLX5_OPCODE_SEND = 0x0a, 316 MLX5_OPCODE_SEND_IMM = 0x0b, 317 MLX5_OPCODE_LSO = 0x0e, 318 MLX5_OPCODE_RDMA_READ = 0x10, 319 MLX5_OPCODE_ATOMIC_CS = 0x11, 320 MLX5_OPCODE_ATOMIC_FA = 0x12, 321 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 322 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 323 MLX5_OPCODE_BIND_MW = 0x18, 324 MLX5_OPCODE_CONFIG_CMD = 0x1f, 325 326 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 327 MLX5_RECV_OPCODE_SEND = 0x01, 328 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 329 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 330 331 MLX5_CQE_OPCODE_ERROR = 0x1e, 332 MLX5_CQE_OPCODE_RESIZE = 0x16, 333 334 MLX5_OPCODE_SET_PSV = 0x20, 335 MLX5_OPCODE_GET_PSV = 0x21, 336 MLX5_OPCODE_CHECK_PSV = 0x22, 337 MLX5_OPCODE_RGET_PSV = 0x26, 338 MLX5_OPCODE_RCHECK_PSV = 0x27, 339 340 MLX5_OPCODE_UMR = 0x25, 341 342 }; 343 344 enum { 345 MLX5_SET_PORT_RESET_QKEY = 0, 346 MLX5_SET_PORT_GUID0 = 16, 347 MLX5_SET_PORT_NODE_GUID = 17, 348 MLX5_SET_PORT_SYS_GUID = 18, 349 MLX5_SET_PORT_GID_TABLE = 19, 350 MLX5_SET_PORT_PKEY_TABLE = 20, 351 }; 352 353 enum { 354 MLX5_BW_NO_LIMIT = 0, 355 MLX5_100_MBPS_UNIT = 3, 356 MLX5_GBPS_UNIT = 4, 357 }; 358 359 enum { 360 MLX5_MAX_PAGE_SHIFT = 31 361 }; 362 363 enum { 364 MLX5_ADAPTER_PAGE_SHIFT = 12, 365 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 366 }; 367 368 enum { 369 MLX5_CAP_OFF_CMDIF_CSUM = 46, 370 }; 371 372 struct mlx5_inbox_hdr { 373 __be16 opcode; 374 u8 rsvd[4]; 375 __be16 opmod; 376 }; 377 378 struct mlx5_outbox_hdr { 379 u8 status; 380 u8 rsvd[3]; 381 __be32 syndrome; 382 }; 383 384 struct mlx5_cmd_query_adapter_mbox_in { 385 struct mlx5_inbox_hdr hdr; 386 u8 rsvd[8]; 387 }; 388 389 struct mlx5_cmd_query_adapter_mbox_out { 390 struct mlx5_outbox_hdr hdr; 391 u8 rsvd0[24]; 392 u8 intapin; 393 u8 rsvd1[13]; 394 __be16 vsd_vendor_id; 395 u8 vsd[208]; 396 u8 vsd_psid[16]; 397 }; 398 399 enum mlx5_odp_transport_cap_bits { 400 MLX5_ODP_SUPPORT_SEND = 1 << 31, 401 MLX5_ODP_SUPPORT_RECV = 1 << 30, 402 MLX5_ODP_SUPPORT_WRITE = 1 << 29, 403 MLX5_ODP_SUPPORT_READ = 1 << 28, 404 }; 405 406 struct mlx5_odp_caps { 407 char reserved[0x10]; 408 struct { 409 __be32 rc_odp_caps; 410 __be32 uc_odp_caps; 411 __be32 ud_odp_caps; 412 } per_transport_caps; 413 char reserved2[0xe4]; 414 }; 415 416 struct mlx5_cmd_init_hca_mbox_in { 417 struct mlx5_inbox_hdr hdr; 418 u8 rsvd0[2]; 419 __be16 profile; 420 u8 rsvd1[4]; 421 }; 422 423 struct mlx5_cmd_init_hca_mbox_out { 424 struct mlx5_outbox_hdr hdr; 425 u8 rsvd[8]; 426 }; 427 428 struct mlx5_cmd_teardown_hca_mbox_in { 429 struct mlx5_inbox_hdr hdr; 430 u8 rsvd0[2]; 431 __be16 profile; 432 u8 rsvd1[4]; 433 }; 434 435 struct mlx5_cmd_teardown_hca_mbox_out { 436 struct mlx5_outbox_hdr hdr; 437 u8 rsvd[8]; 438 }; 439 440 struct mlx5_cmd_layout { 441 u8 type; 442 u8 rsvd0[3]; 443 __be32 inlen; 444 __be64 in_ptr; 445 __be32 in[4]; 446 __be32 out[4]; 447 __be64 out_ptr; 448 __be32 outlen; 449 u8 token; 450 u8 sig; 451 u8 rsvd1; 452 u8 status_own; 453 }; 454 455 456 struct health_buffer { 457 __be32 assert_var[5]; 458 __be32 rsvd0[3]; 459 __be32 assert_exit_ptr; 460 __be32 assert_callra; 461 __be32 rsvd1[2]; 462 __be32 fw_ver; 463 __be32 hw_id; 464 __be32 rsvd2; 465 u8 irisc_index; 466 u8 synd; 467 __be16 ext_synd; 468 }; 469 470 struct mlx5_init_seg { 471 __be32 fw_rev; 472 __be32 cmdif_rev_fw_sub; 473 __be32 rsvd0[2]; 474 __be32 cmdq_addr_h; 475 __be32 cmdq_addr_l_sz; 476 __be32 cmd_dbell; 477 __be32 rsvd1[120]; 478 __be32 initializing; 479 struct health_buffer health; 480 __be32 rsvd2[880]; 481 __be32 internal_timer_h; 482 __be32 internal_timer_l; 483 __be32 rsvd3[2]; 484 __be32 health_counter; 485 __be32 rsvd4[1019]; 486 __be64 ieee1588_clk; 487 __be32 ieee1588_clk_type; 488 __be32 clr_intx; 489 }; 490 491 struct mlx5_eqe_comp { 492 __be32 reserved[6]; 493 __be32 cqn; 494 }; 495 496 struct mlx5_eqe_qp_srq { 497 __be32 reserved1[5]; 498 u8 type; 499 u8 reserved2[3]; 500 __be32 qp_srq_n; 501 }; 502 503 struct mlx5_eqe_cq_err { 504 __be32 cqn; 505 u8 reserved1[7]; 506 u8 syndrome; 507 }; 508 509 struct mlx5_eqe_port_state { 510 u8 reserved0[8]; 511 u8 port; 512 }; 513 514 struct mlx5_eqe_gpio { 515 __be32 reserved0[2]; 516 __be64 gpio_event; 517 }; 518 519 struct mlx5_eqe_congestion { 520 u8 type; 521 u8 rsvd0; 522 u8 congestion_level; 523 }; 524 525 struct mlx5_eqe_stall_vl { 526 u8 rsvd0[3]; 527 u8 port_vl; 528 }; 529 530 struct mlx5_eqe_cmd { 531 __be32 vector; 532 __be32 rsvd[6]; 533 }; 534 535 struct mlx5_eqe_page_req { 536 u8 rsvd0[2]; 537 __be16 func_id; 538 __be32 num_pages; 539 __be32 rsvd1[5]; 540 }; 541 542 struct mlx5_eqe_page_fault { 543 __be32 bytes_committed; 544 union { 545 struct { 546 u16 reserved1; 547 __be16 wqe_index; 548 u16 reserved2; 549 __be16 packet_length; 550 u8 reserved3[12]; 551 } __packed wqe; 552 struct { 553 __be32 r_key; 554 u16 reserved1; 555 __be16 packet_length; 556 __be32 rdma_op_len; 557 __be64 rdma_va; 558 } __packed rdma; 559 } __packed; 560 __be32 flags_qpn; 561 } __packed; 562 563 struct mlx5_eqe_vport_change { 564 u8 rsvd0[2]; 565 __be16 vport_num; 566 __be32 rsvd1[6]; 567 } __packed; 568 569 union ev_data { 570 __be32 raw[7]; 571 struct mlx5_eqe_cmd cmd; 572 struct mlx5_eqe_comp comp; 573 struct mlx5_eqe_qp_srq qp_srq; 574 struct mlx5_eqe_cq_err cq_err; 575 struct mlx5_eqe_port_state port; 576 struct mlx5_eqe_gpio gpio; 577 struct mlx5_eqe_congestion cong; 578 struct mlx5_eqe_stall_vl stall_vl; 579 struct mlx5_eqe_page_req req_pages; 580 struct mlx5_eqe_page_fault page_fault; 581 struct mlx5_eqe_vport_change vport_change; 582 } __packed; 583 584 struct mlx5_eqe { 585 u8 rsvd0; 586 u8 type; 587 u8 rsvd1; 588 u8 sub_type; 589 __be32 rsvd2[7]; 590 union ev_data data; 591 __be16 rsvd3; 592 u8 signature; 593 u8 owner; 594 } __packed; 595 596 struct mlx5_cmd_prot_block { 597 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 598 u8 rsvd0[48]; 599 __be64 next; 600 __be32 block_num; 601 u8 rsvd1; 602 u8 token; 603 u8 ctrl_sig; 604 u8 sig; 605 }; 606 607 enum { 608 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 609 }; 610 611 struct mlx5_err_cqe { 612 u8 rsvd0[32]; 613 __be32 srqn; 614 u8 rsvd1[18]; 615 u8 vendor_err_synd; 616 u8 syndrome; 617 __be32 s_wqe_opcode_qpn; 618 __be16 wqe_counter; 619 u8 signature; 620 u8 op_own; 621 }; 622 623 struct mlx5_cqe64 { 624 u8 rsvd0[4]; 625 u8 lro_tcppsh_abort_dupack; 626 u8 lro_min_ttl; 627 __be16 lro_tcp_win; 628 __be32 lro_ack_seq_num; 629 __be32 rss_hash_result; 630 u8 rss_hash_type; 631 u8 ml_path; 632 u8 rsvd20[2]; 633 __be16 check_sum; 634 __be16 slid; 635 __be32 flags_rqpn; 636 u8 hds_ip_ext; 637 u8 l4_hdr_type_etc; 638 __be16 vlan_info; 639 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 640 __be32 imm_inval_pkey; 641 u8 rsvd40[4]; 642 __be32 byte_cnt; 643 __be32 timestamp_h; 644 __be32 timestamp_l; 645 __be32 sop_drop_qpn; 646 __be16 wqe_counter; 647 u8 signature; 648 u8 op_own; 649 }; 650 651 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 652 { 653 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 654 } 655 656 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 657 { 658 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 659 } 660 661 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe) 662 { 663 return !!(cqe->l4_hdr_type_etc & 0x1); 664 } 665 666 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) 667 { 668 u32 hi, lo; 669 670 hi = be32_to_cpu(cqe->timestamp_h); 671 lo = be32_to_cpu(cqe->timestamp_l); 672 673 return (u64)lo | ((u64)hi << 32); 674 } 675 676 enum { 677 CQE_L4_HDR_TYPE_NONE = 0x0, 678 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 679 CQE_L4_HDR_TYPE_UDP = 0x2, 680 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 681 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 682 }; 683 684 enum { 685 CQE_RSS_HTYPE_IP = 0x3 << 6, 686 CQE_RSS_HTYPE_L4 = 0x3 << 2, 687 }; 688 689 enum { 690 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 691 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 692 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 693 }; 694 695 enum { 696 CQE_L2_OK = 1 << 0, 697 CQE_L3_OK = 1 << 1, 698 CQE_L4_OK = 1 << 2, 699 }; 700 701 struct mlx5_sig_err_cqe { 702 u8 rsvd0[16]; 703 __be32 expected_trans_sig; 704 __be32 actual_trans_sig; 705 __be32 expected_reftag; 706 __be32 actual_reftag; 707 __be16 syndrome; 708 u8 rsvd22[2]; 709 __be32 mkey; 710 __be64 err_offset; 711 u8 rsvd30[8]; 712 __be32 qpn; 713 u8 rsvd38[2]; 714 u8 signature; 715 u8 op_own; 716 }; 717 718 struct mlx5_wqe_srq_next_seg { 719 u8 rsvd0[2]; 720 __be16 next_wqe_index; 721 u8 signature; 722 u8 rsvd1[11]; 723 }; 724 725 union mlx5_ext_cqe { 726 struct ib_grh grh; 727 u8 inl[64]; 728 }; 729 730 struct mlx5_cqe128 { 731 union mlx5_ext_cqe inl_grh; 732 struct mlx5_cqe64 cqe64; 733 }; 734 735 struct mlx5_srq_ctx { 736 u8 state_log_sz; 737 u8 rsvd0[3]; 738 __be32 flags_xrcd; 739 __be32 pgoff_cqn; 740 u8 rsvd1[4]; 741 u8 log_pg_sz; 742 u8 rsvd2[7]; 743 __be32 pd; 744 __be16 lwm; 745 __be16 wqe_cnt; 746 u8 rsvd3[8]; 747 __be64 db_record; 748 }; 749 750 struct mlx5_create_srq_mbox_in { 751 struct mlx5_inbox_hdr hdr; 752 __be32 input_srqn; 753 u8 rsvd0[4]; 754 struct mlx5_srq_ctx ctx; 755 u8 rsvd1[208]; 756 __be64 pas[0]; 757 }; 758 759 struct mlx5_create_srq_mbox_out { 760 struct mlx5_outbox_hdr hdr; 761 __be32 srqn; 762 u8 rsvd[4]; 763 }; 764 765 struct mlx5_destroy_srq_mbox_in { 766 struct mlx5_inbox_hdr hdr; 767 __be32 srqn; 768 u8 rsvd[4]; 769 }; 770 771 struct mlx5_destroy_srq_mbox_out { 772 struct mlx5_outbox_hdr hdr; 773 u8 rsvd[8]; 774 }; 775 776 struct mlx5_query_srq_mbox_in { 777 struct mlx5_inbox_hdr hdr; 778 __be32 srqn; 779 u8 rsvd0[4]; 780 }; 781 782 struct mlx5_query_srq_mbox_out { 783 struct mlx5_outbox_hdr hdr; 784 u8 rsvd0[8]; 785 struct mlx5_srq_ctx ctx; 786 u8 rsvd1[32]; 787 __be64 pas[0]; 788 }; 789 790 struct mlx5_arm_srq_mbox_in { 791 struct mlx5_inbox_hdr hdr; 792 __be32 srqn; 793 __be16 rsvd; 794 __be16 lwm; 795 }; 796 797 struct mlx5_arm_srq_mbox_out { 798 struct mlx5_outbox_hdr hdr; 799 u8 rsvd[8]; 800 }; 801 802 struct mlx5_cq_context { 803 u8 status; 804 u8 cqe_sz_flags; 805 u8 st; 806 u8 rsvd3; 807 u8 rsvd4[6]; 808 __be16 page_offset; 809 __be32 log_sz_usr_page; 810 __be16 cq_period; 811 __be16 cq_max_count; 812 __be16 rsvd20; 813 __be16 c_eqn; 814 u8 log_pg_sz; 815 u8 rsvd25[7]; 816 __be32 last_notified_index; 817 __be32 solicit_producer_index; 818 __be32 consumer_counter; 819 __be32 producer_counter; 820 u8 rsvd48[8]; 821 __be64 db_record_addr; 822 }; 823 824 struct mlx5_create_cq_mbox_in { 825 struct mlx5_inbox_hdr hdr; 826 __be32 input_cqn; 827 u8 rsvdx[4]; 828 struct mlx5_cq_context ctx; 829 u8 rsvd6[192]; 830 __be64 pas[0]; 831 }; 832 833 struct mlx5_create_cq_mbox_out { 834 struct mlx5_outbox_hdr hdr; 835 __be32 cqn; 836 u8 rsvd0[4]; 837 }; 838 839 struct mlx5_destroy_cq_mbox_in { 840 struct mlx5_inbox_hdr hdr; 841 __be32 cqn; 842 u8 rsvd0[4]; 843 }; 844 845 struct mlx5_destroy_cq_mbox_out { 846 struct mlx5_outbox_hdr hdr; 847 u8 rsvd0[8]; 848 }; 849 850 struct mlx5_query_cq_mbox_in { 851 struct mlx5_inbox_hdr hdr; 852 __be32 cqn; 853 u8 rsvd0[4]; 854 }; 855 856 struct mlx5_query_cq_mbox_out { 857 struct mlx5_outbox_hdr hdr; 858 u8 rsvd0[8]; 859 struct mlx5_cq_context ctx; 860 u8 rsvd6[16]; 861 __be64 pas[0]; 862 }; 863 864 struct mlx5_modify_cq_mbox_in { 865 struct mlx5_inbox_hdr hdr; 866 __be32 cqn; 867 __be32 field_select; 868 struct mlx5_cq_context ctx; 869 u8 rsvd[192]; 870 __be64 pas[0]; 871 }; 872 873 struct mlx5_modify_cq_mbox_out { 874 struct mlx5_outbox_hdr hdr; 875 u8 rsvd[8]; 876 }; 877 878 struct mlx5_enable_hca_mbox_in { 879 struct mlx5_inbox_hdr hdr; 880 u8 rsvd[8]; 881 }; 882 883 struct mlx5_enable_hca_mbox_out { 884 struct mlx5_outbox_hdr hdr; 885 u8 rsvd[8]; 886 }; 887 888 struct mlx5_disable_hca_mbox_in { 889 struct mlx5_inbox_hdr hdr; 890 u8 rsvd[8]; 891 }; 892 893 struct mlx5_disable_hca_mbox_out { 894 struct mlx5_outbox_hdr hdr; 895 u8 rsvd[8]; 896 }; 897 898 struct mlx5_eq_context { 899 u8 status; 900 u8 ec_oi; 901 u8 st; 902 u8 rsvd2[7]; 903 __be16 page_pffset; 904 __be32 log_sz_usr_page; 905 u8 rsvd3[7]; 906 u8 intr; 907 u8 log_page_size; 908 u8 rsvd4[15]; 909 __be32 consumer_counter; 910 __be32 produser_counter; 911 u8 rsvd5[16]; 912 }; 913 914 struct mlx5_create_eq_mbox_in { 915 struct mlx5_inbox_hdr hdr; 916 u8 rsvd0[3]; 917 u8 input_eqn; 918 u8 rsvd1[4]; 919 struct mlx5_eq_context ctx; 920 u8 rsvd2[8]; 921 __be64 events_mask; 922 u8 rsvd3[176]; 923 __be64 pas[0]; 924 }; 925 926 struct mlx5_create_eq_mbox_out { 927 struct mlx5_outbox_hdr hdr; 928 u8 rsvd0[3]; 929 u8 eq_number; 930 u8 rsvd1[4]; 931 }; 932 933 struct mlx5_destroy_eq_mbox_in { 934 struct mlx5_inbox_hdr hdr; 935 u8 rsvd0[3]; 936 u8 eqn; 937 u8 rsvd1[4]; 938 }; 939 940 struct mlx5_destroy_eq_mbox_out { 941 struct mlx5_outbox_hdr hdr; 942 u8 rsvd[8]; 943 }; 944 945 struct mlx5_map_eq_mbox_in { 946 struct mlx5_inbox_hdr hdr; 947 __be64 mask; 948 u8 mu; 949 u8 rsvd0[2]; 950 u8 eqn; 951 u8 rsvd1[24]; 952 }; 953 954 struct mlx5_map_eq_mbox_out { 955 struct mlx5_outbox_hdr hdr; 956 u8 rsvd[8]; 957 }; 958 959 struct mlx5_query_eq_mbox_in { 960 struct mlx5_inbox_hdr hdr; 961 u8 rsvd0[3]; 962 u8 eqn; 963 u8 rsvd1[4]; 964 }; 965 966 struct mlx5_query_eq_mbox_out { 967 struct mlx5_outbox_hdr hdr; 968 u8 rsvd[8]; 969 struct mlx5_eq_context ctx; 970 }; 971 972 enum { 973 MLX5_MKEY_STATUS_FREE = 1 << 6, 974 }; 975 976 struct mlx5_mkey_seg { 977 /* This is a two bit field occupying bits 31-30. 978 * bit 31 is always 0, 979 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 980 */ 981 u8 status; 982 u8 pcie_control; 983 u8 flags; 984 u8 version; 985 __be32 qpn_mkey7_0; 986 u8 rsvd1[4]; 987 __be32 flags_pd; 988 __be64 start_addr; 989 __be64 len; 990 __be32 bsfs_octo_size; 991 u8 rsvd2[16]; 992 __be32 xlt_oct_size; 993 u8 rsvd3[3]; 994 u8 log2_page_size; 995 u8 rsvd4[4]; 996 }; 997 998 struct mlx5_query_special_ctxs_mbox_in { 999 struct mlx5_inbox_hdr hdr; 1000 u8 rsvd[8]; 1001 }; 1002 1003 struct mlx5_query_special_ctxs_mbox_out { 1004 struct mlx5_outbox_hdr hdr; 1005 __be32 dump_fill_mkey; 1006 __be32 reserved_lkey; 1007 }; 1008 1009 struct mlx5_create_mkey_mbox_in { 1010 struct mlx5_inbox_hdr hdr; 1011 __be32 input_mkey_index; 1012 __be32 flags; 1013 struct mlx5_mkey_seg seg; 1014 u8 rsvd1[16]; 1015 __be32 xlat_oct_act_size; 1016 __be32 rsvd2; 1017 u8 rsvd3[168]; 1018 __be64 pas[0]; 1019 }; 1020 1021 struct mlx5_create_mkey_mbox_out { 1022 struct mlx5_outbox_hdr hdr; 1023 __be32 mkey; 1024 u8 rsvd[4]; 1025 }; 1026 1027 struct mlx5_destroy_mkey_mbox_in { 1028 struct mlx5_inbox_hdr hdr; 1029 __be32 mkey; 1030 u8 rsvd[4]; 1031 }; 1032 1033 struct mlx5_destroy_mkey_mbox_out { 1034 struct mlx5_outbox_hdr hdr; 1035 u8 rsvd[8]; 1036 }; 1037 1038 struct mlx5_query_mkey_mbox_in { 1039 struct mlx5_inbox_hdr hdr; 1040 __be32 mkey; 1041 }; 1042 1043 struct mlx5_query_mkey_mbox_out { 1044 struct mlx5_outbox_hdr hdr; 1045 __be64 pas[0]; 1046 }; 1047 1048 struct mlx5_modify_mkey_mbox_in { 1049 struct mlx5_inbox_hdr hdr; 1050 __be32 mkey; 1051 __be64 pas[0]; 1052 }; 1053 1054 struct mlx5_modify_mkey_mbox_out { 1055 struct mlx5_outbox_hdr hdr; 1056 u8 rsvd[8]; 1057 }; 1058 1059 struct mlx5_dump_mkey_mbox_in { 1060 struct mlx5_inbox_hdr hdr; 1061 }; 1062 1063 struct mlx5_dump_mkey_mbox_out { 1064 struct mlx5_outbox_hdr hdr; 1065 __be32 mkey; 1066 }; 1067 1068 struct mlx5_mad_ifc_mbox_in { 1069 struct mlx5_inbox_hdr hdr; 1070 __be16 remote_lid; 1071 u8 rsvd0; 1072 u8 port; 1073 u8 rsvd1[4]; 1074 u8 data[256]; 1075 }; 1076 1077 struct mlx5_mad_ifc_mbox_out { 1078 struct mlx5_outbox_hdr hdr; 1079 u8 rsvd[8]; 1080 u8 data[256]; 1081 }; 1082 1083 struct mlx5_access_reg_mbox_in { 1084 struct mlx5_inbox_hdr hdr; 1085 u8 rsvd0[2]; 1086 __be16 register_id; 1087 __be32 arg; 1088 __be32 data[0]; 1089 }; 1090 1091 struct mlx5_access_reg_mbox_out { 1092 struct mlx5_outbox_hdr hdr; 1093 u8 rsvd[8]; 1094 __be32 data[0]; 1095 }; 1096 1097 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1098 1099 enum { 1100 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1101 }; 1102 1103 struct mlx5_allocate_psv_in { 1104 struct mlx5_inbox_hdr hdr; 1105 __be32 npsv_pd; 1106 __be32 rsvd_psv0; 1107 }; 1108 1109 struct mlx5_allocate_psv_out { 1110 struct mlx5_outbox_hdr hdr; 1111 u8 rsvd[8]; 1112 __be32 psv_idx[4]; 1113 }; 1114 1115 struct mlx5_destroy_psv_in { 1116 struct mlx5_inbox_hdr hdr; 1117 __be32 psv_number; 1118 u8 rsvd[4]; 1119 }; 1120 1121 struct mlx5_destroy_psv_out { 1122 struct mlx5_outbox_hdr hdr; 1123 u8 rsvd[8]; 1124 }; 1125 1126 #define MLX5_CMD_OP_MAX 0x920 1127 1128 enum { 1129 VPORT_STATE_DOWN = 0x0, 1130 VPORT_STATE_UP = 0x1, 1131 }; 1132 1133 enum { 1134 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 1135 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 1136 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 1137 }; 1138 1139 enum { 1140 MLX5_L3_PROT_TYPE_IPV4 = 0, 1141 MLX5_L3_PROT_TYPE_IPV6 = 1, 1142 }; 1143 1144 enum { 1145 MLX5_L4_PROT_TYPE_TCP = 0, 1146 MLX5_L4_PROT_TYPE_UDP = 1, 1147 }; 1148 1149 enum { 1150 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1151 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1152 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1153 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1154 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1155 }; 1156 1157 enum { 1158 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1159 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1160 MLX5_MATCH_INNER_HEADERS = 1 << 2, 1161 1162 }; 1163 1164 enum { 1165 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1166 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1167 }; 1168 1169 enum { 1170 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, 1171 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, 1172 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, 1173 }; 1174 1175 enum mlx5_list_type { 1176 MLX5_NVPRT_LIST_TYPE_UC = 0x0, 1177 MLX5_NVPRT_LIST_TYPE_MC = 0x1, 1178 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, 1179 }; 1180 1181 enum { 1182 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1183 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, 1184 }; 1185 1186 enum mlx5_wol_mode { 1187 MLX5_WOL_DISABLE = 0, 1188 MLX5_WOL_SECURED_MAGIC = 1 << 1, 1189 MLX5_WOL_MAGIC = 1 << 2, 1190 MLX5_WOL_ARP = 1 << 3, 1191 MLX5_WOL_BROADCAST = 1 << 4, 1192 MLX5_WOL_MULTICAST = 1 << 5, 1193 MLX5_WOL_UNICAST = 1 << 6, 1194 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 1195 }; 1196 1197 /* MLX5 DEV CAPs */ 1198 1199 /* TODO: EAT.ME */ 1200 enum mlx5_cap_mode { 1201 HCA_CAP_OPMOD_GET_MAX = 0, 1202 HCA_CAP_OPMOD_GET_CUR = 1, 1203 }; 1204 1205 enum mlx5_cap_type { 1206 MLX5_CAP_GENERAL = 0, 1207 MLX5_CAP_ETHERNET_OFFLOADS, 1208 MLX5_CAP_ODP, 1209 MLX5_CAP_ATOMIC, 1210 MLX5_CAP_ROCE, 1211 MLX5_CAP_IPOIB_OFFLOADS, 1212 MLX5_CAP_EOIB_OFFLOADS, 1213 MLX5_CAP_FLOW_TABLE, 1214 MLX5_CAP_ESWITCH_FLOW_TABLE, 1215 MLX5_CAP_ESWITCH, 1216 /* NUM OF CAP Types */ 1217 MLX5_CAP_NUM 1218 }; 1219 1220 /* GET Dev Caps macros */ 1221 #define MLX5_CAP_GEN(mdev, cap) \ 1222 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1223 1224 #define MLX5_CAP_GEN_MAX(mdev, cap) \ 1225 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1226 1227 #define MLX5_CAP_ETH(mdev, cap) \ 1228 MLX5_GET(per_protocol_networking_offload_caps,\ 1229 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1230 1231 #define MLX5_CAP_ETH_MAX(mdev, cap) \ 1232 MLX5_GET(per_protocol_networking_offload_caps,\ 1233 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1234 1235 #define MLX5_CAP_ROCE(mdev, cap) \ 1236 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1237 1238 #define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1239 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1240 1241 #define MLX5_CAP_ATOMIC(mdev, cap) \ 1242 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1243 1244 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1245 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1246 1247 #define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1248 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1249 1250 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1251 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1252 1253 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1254 MLX5_GET(flow_table_eswitch_cap, \ 1255 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1256 1257 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1258 MLX5_GET(flow_table_eswitch_cap, \ 1259 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1260 1261 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1262 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1263 1264 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1265 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1266 1267 #define MLX5_CAP_ESW(mdev, cap) \ 1268 MLX5_GET(e_switch_cap, \ 1269 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1270 1271 #define MLX5_CAP_ESW_MAX(mdev, cap) \ 1272 MLX5_GET(e_switch_cap, \ 1273 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1274 1275 #define MLX5_CAP_ODP(mdev, cap)\ 1276 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1277 1278 enum { 1279 MLX5_CMD_STAT_OK = 0x0, 1280 MLX5_CMD_STAT_INT_ERR = 0x1, 1281 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1282 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1283 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1284 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1285 MLX5_CMD_STAT_RES_BUSY = 0x6, 1286 MLX5_CMD_STAT_LIM_ERR = 0x8, 1287 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1288 MLX5_CMD_STAT_IX_ERR = 0xa, 1289 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1290 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1291 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1292 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1293 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1294 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1295 }; 1296 1297 enum { 1298 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1299 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1300 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1301 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1302 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1303 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1304 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11 1305 }; 1306 1307 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1308 { 1309 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1310 return 0; 1311 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1312 } 1313 1314 #define MLX5_BY_PASS_NUM_PRIOS 9 1315 1316 #endif /* MLX5_DEVICE_H */ 1317