1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 38 #include <linux/mlx4/device.h> 39 40 #define MLX4_INVALID_LKEY 0x100 41 42 enum mlx4_qp_optpar { 43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 44 MLX4_QP_OPTPAR_RRE = 1 << 1, 45 MLX4_QP_OPTPAR_RAE = 1 << 2, 46 MLX4_QP_OPTPAR_RWE = 1 << 3, 47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 58 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 59 }; 60 61 enum mlx4_qp_state { 62 MLX4_QP_STATE_RST = 0, 63 MLX4_QP_STATE_INIT = 1, 64 MLX4_QP_STATE_RTR = 2, 65 MLX4_QP_STATE_RTS = 3, 66 MLX4_QP_STATE_SQER = 4, 67 MLX4_QP_STATE_SQD = 5, 68 MLX4_QP_STATE_ERR = 6, 69 MLX4_QP_STATE_SQ_DRAINING = 7, 70 MLX4_QP_NUM_STATE 71 }; 72 73 enum { 74 MLX4_QP_ST_RC = 0x0, 75 MLX4_QP_ST_UC = 0x1, 76 MLX4_QP_ST_RD = 0x2, 77 MLX4_QP_ST_UD = 0x3, 78 MLX4_QP_ST_XRC = 0x6, 79 MLX4_QP_ST_MLX = 0x7 80 }; 81 82 enum { 83 MLX4_QP_PM_MIGRATED = 0x3, 84 MLX4_QP_PM_ARMED = 0x0, 85 MLX4_QP_PM_REARM = 0x1 86 }; 87 88 enum { 89 /* params1 */ 90 MLX4_QP_BIT_SRE = 1 << 15, 91 MLX4_QP_BIT_SWE = 1 << 14, 92 MLX4_QP_BIT_SAE = 1 << 13, 93 /* params2 */ 94 MLX4_QP_BIT_RRE = 1 << 15, 95 MLX4_QP_BIT_RWE = 1 << 14, 96 MLX4_QP_BIT_RAE = 1 << 13, 97 MLX4_QP_BIT_RIC = 1 << 4, 98 }; 99 100 struct mlx4_qp_path { 101 u8 fl; 102 u8 reserved1[2]; 103 u8 pkey_index; 104 u8 counter_index; 105 u8 grh_mylmc; 106 __be16 rlid; 107 u8 ackto; 108 u8 mgid_index; 109 u8 static_rate; 110 u8 hop_limit; 111 __be32 tclass_flowlabel; 112 u8 rgid[16]; 113 u8 sched_queue; 114 u8 vlan_index; 115 u8 reserved3[2]; 116 u8 reserved4[2]; 117 u8 dmac[6]; 118 }; 119 120 struct mlx4_qp_context { 121 __be32 flags; 122 __be32 pd; 123 u8 mtu_msgmax; 124 u8 rq_size_stride; 125 u8 sq_size_stride; 126 u8 rlkey; 127 __be32 usr_page; 128 __be32 local_qpn; 129 __be32 remote_qpn; 130 struct mlx4_qp_path pri_path; 131 struct mlx4_qp_path alt_path; 132 __be32 params1; 133 u32 reserved1; 134 __be32 next_send_psn; 135 __be32 cqn_send; 136 u32 reserved2[2]; 137 __be32 last_acked_psn; 138 __be32 ssn; 139 __be32 params2; 140 __be32 rnr_nextrecvpsn; 141 __be32 xrcd; 142 __be32 cqn_recv; 143 __be64 db_rec_addr; 144 __be32 qkey; 145 __be32 srqn; 146 __be32 msn; 147 __be16 rq_wqe_counter; 148 __be16 sq_wqe_counter; 149 u32 reserved3[2]; 150 __be32 param3; 151 __be32 nummmcpeers_basemkey; 152 u8 log_page_size; 153 u8 reserved4[2]; 154 u8 mtt_base_addr_h; 155 __be32 mtt_base_addr_l; 156 u32 reserved5[10]; 157 }; 158 159 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 160 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 161 162 enum { 163 MLX4_WQE_CTRL_NEC = 1 << 29, 164 MLX4_WQE_CTRL_FENCE = 1 << 6, 165 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 166 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 167 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 168 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 169 MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 170 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 171 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 172 }; 173 174 struct mlx4_wqe_ctrl_seg { 175 __be32 owner_opcode; 176 __be16 vlan_tag; 177 u8 ins_vlan; 178 u8 fence_size; 179 /* 180 * High 24 bits are SRC remote buffer; low 8 bits are flags: 181 * [7] SO (strong ordering) 182 * [5] TCP/UDP checksum 183 * [4] IP checksum 184 * [3:2] C (generate completion queue entry) 185 * [1] SE (solicited event) 186 */ 187 __be32 srcrb_flags; 188 /* 189 * imm is immediate data for send/RDMA write w/ immediate; 190 * also invalidation key for send with invalidate; input 191 * modifier for WQEs on CCQs. 192 */ 193 __be32 imm; 194 }; 195 196 enum { 197 MLX4_WQE_MLX_VL15 = 1 << 17, 198 MLX4_WQE_MLX_SLR = 1 << 16 199 }; 200 201 struct mlx4_wqe_mlx_seg { 202 u8 owner; 203 u8 reserved1[2]; 204 u8 opcode; 205 u8 reserved2[3]; 206 u8 size; 207 /* 208 * [17] VL15 209 * [16] SLR 210 * [15:12] static rate 211 * [11:8] SL 212 * [4] ICRC 213 * [3:2] C 214 * [0] FL (force loopback) 215 */ 216 __be32 flags; 217 __be16 rlid; 218 u16 reserved3; 219 }; 220 221 struct mlx4_wqe_datagram_seg { 222 __be32 av[8]; 223 __be32 dqpn; 224 __be32 qkey; 225 __be16 vlan; 226 u8 mac[6]; 227 }; 228 229 struct mlx4_wqe_lso_seg { 230 __be32 mss_hdr_size; 231 __be32 header[0]; 232 }; 233 234 struct mlx4_wqe_bind_seg { 235 __be32 flags1; 236 __be32 flags2; 237 __be32 new_rkey; 238 __be32 lkey; 239 __be64 addr; 240 __be64 length; 241 }; 242 243 enum { 244 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 245 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 246 MLX4_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 247 MLX4_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 248 MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31 249 }; 250 251 struct mlx4_wqe_fmr_seg { 252 __be32 flags; 253 __be32 mem_key; 254 __be64 buf_list; 255 __be64 start_addr; 256 __be64 reg_len; 257 __be32 offset; 258 __be32 page_size; 259 u32 reserved[2]; 260 }; 261 262 struct mlx4_wqe_fmr_ext_seg { 263 u8 flags; 264 u8 reserved; 265 __be16 app_mask; 266 __be16 wire_app_tag; 267 __be16 mem_app_tag; 268 __be32 wire_ref_tag_base; 269 __be32 mem_ref_tag_base; 270 }; 271 272 struct mlx4_wqe_local_inval_seg { 273 __be32 flags; 274 u32 reserved1; 275 __be32 mem_key; 276 u32 reserved2[2]; 277 __be32 guest_id; 278 __be64 pa; 279 }; 280 281 struct mlx4_wqe_raddr_seg { 282 __be64 raddr; 283 __be32 rkey; 284 u32 reserved; 285 }; 286 287 struct mlx4_wqe_atomic_seg { 288 __be64 swap_add; 289 __be64 compare; 290 }; 291 292 struct mlx4_wqe_masked_atomic_seg { 293 __be64 swap_add; 294 __be64 compare; 295 __be64 swap_add_mask; 296 __be64 compare_mask; 297 }; 298 299 struct mlx4_wqe_data_seg { 300 __be32 byte_count; 301 __be32 lkey; 302 __be64 addr; 303 }; 304 305 enum { 306 MLX4_INLINE_ALIGN = 64, 307 MLX4_INLINE_SEG = 1 << 31, 308 }; 309 310 struct mlx4_wqe_inline_seg { 311 __be32 byte_count; 312 }; 313 314 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 315 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 316 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 317 int sqd_event, struct mlx4_qp *qp); 318 319 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 320 struct mlx4_qp_context *context); 321 322 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 323 struct mlx4_qp_context *context, 324 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 325 326 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 327 { 328 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 329 } 330 331 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 332 333 #endif /* MLX4_QP_H */ 334