1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 38 #include <linux/mlx4/device.h> 39 40 #define MLX4_INVALID_LKEY 0x100 41 42 enum mlx4_qp_optpar { 43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 44 MLX4_QP_OPTPAR_RRE = 1 << 1, 45 MLX4_QP_OPTPAR_RAE = 1 << 2, 46 MLX4_QP_OPTPAR_RWE = 1 << 3, 47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 58 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 59 }; 60 61 enum mlx4_qp_state { 62 MLX4_QP_STATE_RST = 0, 63 MLX4_QP_STATE_INIT = 1, 64 MLX4_QP_STATE_RTR = 2, 65 MLX4_QP_STATE_RTS = 3, 66 MLX4_QP_STATE_SQER = 4, 67 MLX4_QP_STATE_SQD = 5, 68 MLX4_QP_STATE_ERR = 6, 69 MLX4_QP_STATE_SQ_DRAINING = 7, 70 MLX4_QP_NUM_STATE 71 }; 72 73 enum { 74 MLX4_QP_ST_RC = 0x0, 75 MLX4_QP_ST_UC = 0x1, 76 MLX4_QP_ST_RD = 0x2, 77 MLX4_QP_ST_UD = 0x3, 78 MLX4_QP_ST_XRC = 0x6, 79 MLX4_QP_ST_MLX = 0x7 80 }; 81 82 enum { 83 MLX4_QP_PM_MIGRATED = 0x3, 84 MLX4_QP_PM_ARMED = 0x0, 85 MLX4_QP_PM_REARM = 0x1 86 }; 87 88 enum { 89 /* params1 */ 90 MLX4_QP_BIT_SRE = 1 << 15, 91 MLX4_QP_BIT_SWE = 1 << 14, 92 MLX4_QP_BIT_SAE = 1 << 13, 93 /* params2 */ 94 MLX4_QP_BIT_RRE = 1 << 15, 95 MLX4_QP_BIT_RWE = 1 << 14, 96 MLX4_QP_BIT_RAE = 1 << 13, 97 MLX4_QP_BIT_RIC = 1 << 4, 98 }; 99 100 enum { 101 MLX4_RSS_HASH_XOR = 0, 102 MLX4_RSS_HASH_TOP = 1, 103 104 MLX4_RSS_UDP_IPV6 = 1 << 0, 105 MLX4_RSS_UDP_IPV4 = 1 << 1, 106 MLX4_RSS_TCP_IPV6 = 1 << 2, 107 MLX4_RSS_IPV6 = 1 << 3, 108 MLX4_RSS_TCP_IPV4 = 1 << 4, 109 MLX4_RSS_IPV4 = 1 << 5, 110 111 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 112 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 113 /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 114 MLX4_RSS_QPC_FLAG_OFFSET = 13, 115 }; 116 117 struct mlx4_rss_context { 118 __be32 base_qpn; 119 __be32 default_qpn; 120 u16 reserved; 121 u8 hash_fn; 122 u8 flags; 123 __be32 rss_key[10]; 124 __be32 base_qpn_udp; 125 }; 126 127 struct mlx4_qp_path { 128 u8 fl; 129 u8 reserved1[1]; 130 u8 disable_pkey_check; 131 u8 pkey_index; 132 u8 counter_index; 133 u8 grh_mylmc; 134 __be16 rlid; 135 u8 ackto; 136 u8 mgid_index; 137 u8 static_rate; 138 u8 hop_limit; 139 __be32 tclass_flowlabel; 140 u8 rgid[16]; 141 u8 sched_queue; 142 u8 vlan_index; 143 u8 feup; 144 u8 reserved3; 145 u8 reserved4[2]; 146 u8 dmac[6]; 147 }; 148 149 struct mlx4_qp_context { 150 __be32 flags; 151 __be32 pd; 152 u8 mtu_msgmax; 153 u8 rq_size_stride; 154 u8 sq_size_stride; 155 u8 rlkey; 156 __be32 usr_page; 157 __be32 local_qpn; 158 __be32 remote_qpn; 159 struct mlx4_qp_path pri_path; 160 struct mlx4_qp_path alt_path; 161 __be32 params1; 162 u32 reserved1; 163 __be32 next_send_psn; 164 __be32 cqn_send; 165 u32 reserved2[2]; 166 __be32 last_acked_psn; 167 __be32 ssn; 168 __be32 params2; 169 __be32 rnr_nextrecvpsn; 170 __be32 xrcd; 171 __be32 cqn_recv; 172 __be64 db_rec_addr; 173 __be32 qkey; 174 __be32 srqn; 175 __be32 msn; 176 __be16 rq_wqe_counter; 177 __be16 sq_wqe_counter; 178 u32 reserved3[2]; 179 __be32 param3; 180 __be32 nummmcpeers_basemkey; 181 u8 log_page_size; 182 u8 reserved4[2]; 183 u8 mtt_base_addr_h; 184 __be32 mtt_base_addr_l; 185 u32 reserved5[10]; 186 }; 187 188 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 189 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 190 191 enum { 192 MLX4_WQE_CTRL_NEC = 1 << 29, 193 MLX4_WQE_CTRL_FENCE = 1 << 6, 194 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 195 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 196 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 197 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 198 MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 199 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 200 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 201 }; 202 203 struct mlx4_wqe_ctrl_seg { 204 __be32 owner_opcode; 205 __be16 vlan_tag; 206 u8 ins_vlan; 207 u8 fence_size; 208 /* 209 * High 24 bits are SRC remote buffer; low 8 bits are flags: 210 * [7] SO (strong ordering) 211 * [5] TCP/UDP checksum 212 * [4] IP checksum 213 * [3:2] C (generate completion queue entry) 214 * [1] SE (solicited event) 215 * [0] FL (force loopback) 216 */ 217 union { 218 __be32 srcrb_flags; 219 __be16 srcrb_flags16[2]; 220 }; 221 /* 222 * imm is immediate data for send/RDMA write w/ immediate; 223 * also invalidation key for send with invalidate; input 224 * modifier for WQEs on CCQs. 225 */ 226 __be32 imm; 227 }; 228 229 enum { 230 MLX4_WQE_MLX_VL15 = 1 << 17, 231 MLX4_WQE_MLX_SLR = 1 << 16 232 }; 233 234 struct mlx4_wqe_mlx_seg { 235 u8 owner; 236 u8 reserved1[2]; 237 u8 opcode; 238 __be16 sched_prio; 239 u8 reserved2; 240 u8 size; 241 /* 242 * [17] VL15 243 * [16] SLR 244 * [15:12] static rate 245 * [11:8] SL 246 * [4] ICRC 247 * [3:2] C 248 * [0] FL (force loopback) 249 */ 250 __be32 flags; 251 __be16 rlid; 252 u16 reserved3; 253 }; 254 255 struct mlx4_wqe_datagram_seg { 256 __be32 av[8]; 257 __be32 dqpn; 258 __be32 qkey; 259 __be16 vlan; 260 u8 mac[6]; 261 }; 262 263 struct mlx4_wqe_lso_seg { 264 __be32 mss_hdr_size; 265 __be32 header[0]; 266 }; 267 268 struct mlx4_wqe_bind_seg { 269 __be32 flags1; 270 __be32 flags2; 271 __be32 new_rkey; 272 __be32 lkey; 273 __be64 addr; 274 __be64 length; 275 }; 276 277 enum { 278 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 279 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 280 MLX4_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 281 MLX4_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 282 MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31 283 }; 284 285 struct mlx4_wqe_fmr_seg { 286 __be32 flags; 287 __be32 mem_key; 288 __be64 buf_list; 289 __be64 start_addr; 290 __be64 reg_len; 291 __be32 offset; 292 __be32 page_size; 293 u32 reserved[2]; 294 }; 295 296 struct mlx4_wqe_fmr_ext_seg { 297 u8 flags; 298 u8 reserved; 299 __be16 app_mask; 300 __be16 wire_app_tag; 301 __be16 mem_app_tag; 302 __be32 wire_ref_tag_base; 303 __be32 mem_ref_tag_base; 304 }; 305 306 struct mlx4_wqe_local_inval_seg { 307 __be32 flags; 308 u32 reserved1; 309 __be32 mem_key; 310 u32 reserved2[2]; 311 __be32 guest_id; 312 __be64 pa; 313 }; 314 315 struct mlx4_wqe_raddr_seg { 316 __be64 raddr; 317 __be32 rkey; 318 u32 reserved; 319 }; 320 321 struct mlx4_wqe_atomic_seg { 322 __be64 swap_add; 323 __be64 compare; 324 }; 325 326 struct mlx4_wqe_masked_atomic_seg { 327 __be64 swap_add; 328 __be64 compare; 329 __be64 swap_add_mask; 330 __be64 compare_mask; 331 }; 332 333 struct mlx4_wqe_data_seg { 334 __be32 byte_count; 335 __be32 lkey; 336 __be64 addr; 337 }; 338 339 enum { 340 MLX4_INLINE_ALIGN = 64, 341 MLX4_INLINE_SEG = 1 << 31, 342 }; 343 344 struct mlx4_wqe_inline_seg { 345 __be32 byte_count; 346 }; 347 348 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 349 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 350 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 351 int sqd_event, struct mlx4_qp *qp); 352 353 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 354 struct mlx4_qp_context *context); 355 356 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 357 struct mlx4_qp_context *context, 358 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 359 360 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 361 { 362 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 363 } 364 365 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 366 367 #endif /* MLX4_QP_H */ 368