1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 #include <linux/if_ether.h> 38 39 #include <linux/mlx4/device.h> 40 41 #define MLX4_INVALID_LKEY 0x100 42 43 enum mlx4_qp_optpar { 44 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 45 MLX4_QP_OPTPAR_RRE = 1 << 1, 46 MLX4_QP_OPTPAR_RAE = 1 << 2, 47 MLX4_QP_OPTPAR_RWE = 1 << 3, 48 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 49 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 50 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 51 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 52 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 53 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 54 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 55 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 56 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 57 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 58 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 59 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 60 }; 61 62 enum mlx4_qp_state { 63 MLX4_QP_STATE_RST = 0, 64 MLX4_QP_STATE_INIT = 1, 65 MLX4_QP_STATE_RTR = 2, 66 MLX4_QP_STATE_RTS = 3, 67 MLX4_QP_STATE_SQER = 4, 68 MLX4_QP_STATE_SQD = 5, 69 MLX4_QP_STATE_ERR = 6, 70 MLX4_QP_STATE_SQ_DRAINING = 7, 71 MLX4_QP_NUM_STATE 72 }; 73 74 enum { 75 MLX4_QP_ST_RC = 0x0, 76 MLX4_QP_ST_UC = 0x1, 77 MLX4_QP_ST_RD = 0x2, 78 MLX4_QP_ST_UD = 0x3, 79 MLX4_QP_ST_XRC = 0x6, 80 MLX4_QP_ST_MLX = 0x7 81 }; 82 83 enum { 84 MLX4_QP_PM_MIGRATED = 0x3, 85 MLX4_QP_PM_ARMED = 0x0, 86 MLX4_QP_PM_REARM = 0x1 87 }; 88 89 enum { 90 /* params1 */ 91 MLX4_QP_BIT_SRE = 1 << 15, 92 MLX4_QP_BIT_SWE = 1 << 14, 93 MLX4_QP_BIT_SAE = 1 << 13, 94 /* params2 */ 95 MLX4_QP_BIT_RRE = 1 << 15, 96 MLX4_QP_BIT_RWE = 1 << 14, 97 MLX4_QP_BIT_RAE = 1 << 13, 98 MLX4_QP_BIT_RIC = 1 << 4, 99 }; 100 101 enum { 102 MLX4_RSS_HASH_XOR = 0, 103 MLX4_RSS_HASH_TOP = 1, 104 105 MLX4_RSS_UDP_IPV6 = 1 << 0, 106 MLX4_RSS_UDP_IPV4 = 1 << 1, 107 MLX4_RSS_TCP_IPV6 = 1 << 2, 108 MLX4_RSS_IPV6 = 1 << 3, 109 MLX4_RSS_TCP_IPV4 = 1 << 4, 110 MLX4_RSS_IPV4 = 1 << 5, 111 112 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 113 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 114 /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 115 MLX4_RSS_QPC_FLAG_OFFSET = 13, 116 }; 117 118 struct mlx4_rss_context { 119 __be32 base_qpn; 120 __be32 default_qpn; 121 u16 reserved; 122 u8 hash_fn; 123 u8 flags; 124 __be32 rss_key[10]; 125 __be32 base_qpn_udp; 126 }; 127 128 struct mlx4_qp_path { 129 u8 fl; 130 u8 vlan_control; 131 u8 disable_pkey_check; 132 u8 pkey_index; 133 u8 counter_index; 134 u8 grh_mylmc; 135 __be16 rlid; 136 u8 ackto; 137 u8 mgid_index; 138 u8 static_rate; 139 u8 hop_limit; 140 __be32 tclass_flowlabel; 141 u8 rgid[16]; 142 u8 sched_queue; 143 u8 vlan_index; 144 u8 feup; 145 u8 fvl_rx; 146 u8 reserved4[2]; 147 u8 dmac[ETH_ALEN]; 148 }; 149 150 enum { /* fl */ 151 MLX4_FL_CV = 1 << 6, 152 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2 153 }; 154 enum { /* vlan_control */ 155 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 156 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */ 157 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4, 158 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 159 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ 160 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 161 }; 162 163 enum { /* feup */ 164 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 165 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 166 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 167 }; 168 169 enum { /* fvl_rx */ 170 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 171 }; 172 173 struct mlx4_qp_context { 174 __be32 flags; 175 __be32 pd; 176 u8 mtu_msgmax; 177 u8 rq_size_stride; 178 u8 sq_size_stride; 179 u8 rlkey; 180 __be32 usr_page; 181 __be32 local_qpn; 182 __be32 remote_qpn; 183 struct mlx4_qp_path pri_path; 184 struct mlx4_qp_path alt_path; 185 __be32 params1; 186 u32 reserved1; 187 __be32 next_send_psn; 188 __be32 cqn_send; 189 u32 reserved2[2]; 190 __be32 last_acked_psn; 191 __be32 ssn; 192 __be32 params2; 193 __be32 rnr_nextrecvpsn; 194 __be32 xrcd; 195 __be32 cqn_recv; 196 __be64 db_rec_addr; 197 __be32 qkey; 198 __be32 srqn; 199 __be32 msn; 200 __be16 rq_wqe_counter; 201 __be16 sq_wqe_counter; 202 u32 reserved3[2]; 203 __be32 param3; 204 __be32 nummmcpeers_basemkey; 205 u8 log_page_size; 206 u8 reserved4[2]; 207 u8 mtt_base_addr_h; 208 __be32 mtt_base_addr_l; 209 u32 reserved5[10]; 210 }; 211 212 struct mlx4_update_qp_context { 213 __be64 qp_mask; 214 __be64 primary_addr_path_mask; 215 __be64 secondary_addr_path_mask; 216 u64 reserved1; 217 struct mlx4_qp_context qp_context; 218 u64 reserved2[58]; 219 }; 220 221 enum { 222 MLX4_UPD_QP_MASK_PM_STATE = 32, 223 MLX4_UPD_QP_MASK_VSD = 33, 224 }; 225 226 enum { 227 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 228 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 229 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 230 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 231 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 232 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 233 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 234 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 235 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 236 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 237 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 238 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 239 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 240 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 241 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 242 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 243 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 244 }; 245 246 enum { /* param3 */ 247 MLX4_STRIP_VLAN = 1 << 30 248 }; 249 250 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 251 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 252 253 enum { 254 MLX4_WQE_CTRL_NEC = 1 << 29, 255 MLX4_WQE_CTRL_FENCE = 1 << 6, 256 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 257 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 258 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 259 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 260 MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 261 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 262 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 263 }; 264 265 struct mlx4_wqe_ctrl_seg { 266 __be32 owner_opcode; 267 __be16 vlan_tag; 268 u8 ins_vlan; 269 u8 fence_size; 270 /* 271 * High 24 bits are SRC remote buffer; low 8 bits are flags: 272 * [7] SO (strong ordering) 273 * [5] TCP/UDP checksum 274 * [4] IP checksum 275 * [3:2] C (generate completion queue entry) 276 * [1] SE (solicited event) 277 * [0] FL (force loopback) 278 */ 279 union { 280 __be32 srcrb_flags; 281 __be16 srcrb_flags16[2]; 282 }; 283 /* 284 * imm is immediate data for send/RDMA write w/ immediate; 285 * also invalidation key for send with invalidate; input 286 * modifier for WQEs on CCQs. 287 */ 288 __be32 imm; 289 }; 290 291 enum { 292 MLX4_WQE_MLX_VL15 = 1 << 17, 293 MLX4_WQE_MLX_SLR = 1 << 16 294 }; 295 296 struct mlx4_wqe_mlx_seg { 297 u8 owner; 298 u8 reserved1[2]; 299 u8 opcode; 300 __be16 sched_prio; 301 u8 reserved2; 302 u8 size; 303 /* 304 * [17] VL15 305 * [16] SLR 306 * [15:12] static rate 307 * [11:8] SL 308 * [4] ICRC 309 * [3:2] C 310 * [0] FL (force loopback) 311 */ 312 __be32 flags; 313 __be16 rlid; 314 u16 reserved3; 315 }; 316 317 struct mlx4_wqe_datagram_seg { 318 __be32 av[8]; 319 __be32 dqpn; 320 __be32 qkey; 321 __be16 vlan; 322 u8 mac[ETH_ALEN]; 323 }; 324 325 struct mlx4_wqe_lso_seg { 326 __be32 mss_hdr_size; 327 __be32 header[0]; 328 }; 329 330 enum mlx4_wqe_bind_seg_flags2 { 331 MLX4_WQE_BIND_ZERO_BASED = (1 << 30), 332 MLX4_WQE_BIND_TYPE_2 = (1 << 31), 333 }; 334 335 struct mlx4_wqe_bind_seg { 336 __be32 flags1; 337 __be32 flags2; 338 __be32 new_rkey; 339 __be32 lkey; 340 __be64 addr; 341 __be64 length; 342 }; 343 344 enum { 345 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 346 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 347 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 348 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 349 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 350 }; 351 352 struct mlx4_wqe_fmr_seg { 353 __be32 flags; 354 __be32 mem_key; 355 __be64 buf_list; 356 __be64 start_addr; 357 __be64 reg_len; 358 __be32 offset; 359 __be32 page_size; 360 u32 reserved[2]; 361 }; 362 363 struct mlx4_wqe_fmr_ext_seg { 364 u8 flags; 365 u8 reserved; 366 __be16 app_mask; 367 __be16 wire_app_tag; 368 __be16 mem_app_tag; 369 __be32 wire_ref_tag_base; 370 __be32 mem_ref_tag_base; 371 }; 372 373 struct mlx4_wqe_local_inval_seg { 374 u64 reserved1; 375 __be32 mem_key; 376 u32 reserved2; 377 u64 reserved3[2]; 378 }; 379 380 struct mlx4_wqe_raddr_seg { 381 __be64 raddr; 382 __be32 rkey; 383 u32 reserved; 384 }; 385 386 struct mlx4_wqe_atomic_seg { 387 __be64 swap_add; 388 __be64 compare; 389 }; 390 391 struct mlx4_wqe_masked_atomic_seg { 392 __be64 swap_add; 393 __be64 compare; 394 __be64 swap_add_mask; 395 __be64 compare_mask; 396 }; 397 398 struct mlx4_wqe_data_seg { 399 __be32 byte_count; 400 __be32 lkey; 401 __be64 addr; 402 }; 403 404 enum { 405 MLX4_INLINE_ALIGN = 64, 406 MLX4_INLINE_SEG = 1 << 31, 407 }; 408 409 struct mlx4_wqe_inline_seg { 410 __be32 byte_count; 411 }; 412 413 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 414 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 415 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 416 int sqd_event, struct mlx4_qp *qp); 417 418 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 419 struct mlx4_qp_context *context); 420 421 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 422 struct mlx4_qp_context *context, 423 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 424 425 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 426 { 427 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 428 } 429 430 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 431 432 #endif /* MLX4_QP_H */ 433