1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 38 #include <linux/mlx4/device.h> 39 40 #define MLX4_INVALID_LKEY 0x100 41 42 enum mlx4_qp_optpar { 43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 44 MLX4_QP_OPTPAR_RRE = 1 << 1, 45 MLX4_QP_OPTPAR_RAE = 1 << 2, 46 MLX4_QP_OPTPAR_RWE = 1 << 3, 47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16 58 }; 59 60 enum mlx4_qp_state { 61 MLX4_QP_STATE_RST = 0, 62 MLX4_QP_STATE_INIT = 1, 63 MLX4_QP_STATE_RTR = 2, 64 MLX4_QP_STATE_RTS = 3, 65 MLX4_QP_STATE_SQER = 4, 66 MLX4_QP_STATE_SQD = 5, 67 MLX4_QP_STATE_ERR = 6, 68 MLX4_QP_STATE_SQ_DRAINING = 7, 69 MLX4_QP_NUM_STATE 70 }; 71 72 enum { 73 MLX4_QP_ST_RC = 0x0, 74 MLX4_QP_ST_UC = 0x1, 75 MLX4_QP_ST_RD = 0x2, 76 MLX4_QP_ST_UD = 0x3, 77 MLX4_QP_ST_MLX = 0x7 78 }; 79 80 enum { 81 MLX4_QP_PM_MIGRATED = 0x3, 82 MLX4_QP_PM_ARMED = 0x0, 83 MLX4_QP_PM_REARM = 0x1 84 }; 85 86 enum { 87 /* params1 */ 88 MLX4_QP_BIT_SRE = 1 << 15, 89 MLX4_QP_BIT_SWE = 1 << 14, 90 MLX4_QP_BIT_SAE = 1 << 13, 91 /* params2 */ 92 MLX4_QP_BIT_RRE = 1 << 15, 93 MLX4_QP_BIT_RWE = 1 << 14, 94 MLX4_QP_BIT_RAE = 1 << 13, 95 MLX4_QP_BIT_RIC = 1 << 4, 96 }; 97 98 struct mlx4_qp_path { 99 u8 fl; 100 u8 reserved1[2]; 101 u8 pkey_index; 102 u8 reserved2; 103 u8 grh_mylmc; 104 __be16 rlid; 105 u8 ackto; 106 u8 mgid_index; 107 u8 static_rate; 108 u8 hop_limit; 109 __be32 tclass_flowlabel; 110 u8 rgid[16]; 111 u8 sched_queue; 112 u8 snooper_flags; 113 u8 reserved3[2]; 114 u8 counter_index; 115 u8 reserved4[7]; 116 }; 117 118 struct mlx4_qp_context { 119 __be32 flags; 120 __be32 pd; 121 u8 mtu_msgmax; 122 u8 rq_size_stride; 123 u8 sq_size_stride; 124 u8 rlkey; 125 __be32 usr_page; 126 __be32 local_qpn; 127 __be32 remote_qpn; 128 struct mlx4_qp_path pri_path; 129 struct mlx4_qp_path alt_path; 130 __be32 params1; 131 u32 reserved1; 132 __be32 next_send_psn; 133 __be32 cqn_send; 134 u32 reserved2[2]; 135 __be32 last_acked_psn; 136 __be32 ssn; 137 __be32 params2; 138 __be32 rnr_nextrecvpsn; 139 __be32 srcd; 140 __be32 cqn_recv; 141 __be64 db_rec_addr; 142 __be32 qkey; 143 __be32 srqn; 144 __be32 msn; 145 __be16 rq_wqe_counter; 146 __be16 sq_wqe_counter; 147 u32 reserved3[2]; 148 __be32 param3; 149 __be32 nummmcpeers_basemkey; 150 u8 log_page_size; 151 u8 reserved4[2]; 152 u8 mtt_base_addr_h; 153 __be32 mtt_base_addr_l; 154 u32 reserved5[10]; 155 }; 156 157 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 158 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 159 160 enum { 161 MLX4_WQE_CTRL_NEC = 1 << 29, 162 MLX4_WQE_CTRL_FENCE = 1 << 6, 163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 164 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 165 }; 166 167 struct mlx4_wqe_ctrl_seg { 168 __be32 owner_opcode; 169 u8 reserved2[3]; 170 u8 fence_size; 171 /* 172 * High 24 bits are SRC remote buffer; low 8 bits are flags: 173 * [7] SO (strong ordering) 174 * [5] TCP/UDP checksum 175 * [4] IP checksum 176 * [3:2] C (generate completion queue entry) 177 * [1] SE (solicited event) 178 */ 179 __be32 srcrb_flags; 180 /* 181 * imm is immediate data for send/RDMA write w/ immediate; 182 * also invalidation key for send with invalidate; input 183 * modifier for WQEs on CCQs. 184 */ 185 __be32 imm; 186 }; 187 188 enum { 189 MLX4_WQE_MLX_VL15 = 1 << 17, 190 MLX4_WQE_MLX_SLR = 1 << 16 191 }; 192 193 struct mlx4_wqe_mlx_seg { 194 u8 owner; 195 u8 reserved1[2]; 196 u8 opcode; 197 u8 reserved2[3]; 198 u8 size; 199 /* 200 * [17] VL15 201 * [16] SLR 202 * [15:12] static rate 203 * [11:8] SL 204 * [4] ICRC 205 * [3:2] C 206 * [0] FL (force loopback) 207 */ 208 __be32 flags; 209 __be16 rlid; 210 u16 reserved3; 211 }; 212 213 struct mlx4_wqe_datagram_seg { 214 __be32 av[8]; 215 __be32 dqpn; 216 __be32 qkey; 217 __be32 reservd[2]; 218 }; 219 220 struct mlx4_wqe_bind_seg { 221 __be32 flags1; 222 __be32 flags2; 223 __be32 new_rkey; 224 __be32 lkey; 225 __be64 addr; 226 __be64 length; 227 }; 228 229 struct mlx4_wqe_fmr_seg { 230 __be32 flags; 231 __be32 mem_key; 232 __be64 buf_list; 233 __be64 start_addr; 234 __be64 reg_len; 235 __be32 offset; 236 __be32 page_size; 237 u32 reserved[2]; 238 }; 239 240 struct mlx4_wqe_fmr_ext_seg { 241 u8 flags; 242 u8 reserved; 243 __be16 app_mask; 244 __be16 wire_app_tag; 245 __be16 mem_app_tag; 246 __be32 wire_ref_tag_base; 247 __be32 mem_ref_tag_base; 248 }; 249 250 struct mlx4_wqe_local_inval_seg { 251 u8 flags; 252 u8 reserved1[3]; 253 __be32 mem_key; 254 u8 reserved2[3]; 255 u8 guest_id; 256 __be64 pa; 257 }; 258 259 struct mlx4_wqe_raddr_seg { 260 __be64 raddr; 261 __be32 rkey; 262 u32 reserved; 263 }; 264 265 struct mlx4_wqe_atomic_seg { 266 __be64 swap_add; 267 __be64 compare; 268 }; 269 270 struct mlx4_wqe_data_seg { 271 __be32 byte_count; 272 __be32 lkey; 273 __be64 addr; 274 }; 275 276 enum { 277 MLX4_INLINE_ALIGN = 64, 278 }; 279 280 struct mlx4_wqe_inline_seg { 281 __be32 byte_count; 282 }; 283 284 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 285 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 286 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 287 int sqd_event, struct mlx4_qp *qp); 288 289 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 290 struct mlx4_qp_context *context); 291 292 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 293 { 294 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 295 } 296 297 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 298 299 #endif /* MLX4_QP_H */ 300