1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_QP_H 34 #define MLX4_QP_H 35 36 #include <linux/types.h> 37 #include <linux/if_ether.h> 38 39 #include <linux/mlx4/device.h> 40 41 #define MLX4_INVALID_LKEY 0x100 42 43 enum mlx4_qp_optpar { 44 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 45 MLX4_QP_OPTPAR_RRE = 1 << 1, 46 MLX4_QP_OPTPAR_RAE = 1 << 2, 47 MLX4_QP_OPTPAR_RWE = 1 << 3, 48 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 49 MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 50 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 51 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 52 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 53 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 54 MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 55 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 56 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 57 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 58 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 59 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20, 60 MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21, 61 }; 62 63 enum mlx4_qp_state { 64 MLX4_QP_STATE_RST = 0, 65 MLX4_QP_STATE_INIT = 1, 66 MLX4_QP_STATE_RTR = 2, 67 MLX4_QP_STATE_RTS = 3, 68 MLX4_QP_STATE_SQER = 4, 69 MLX4_QP_STATE_SQD = 5, 70 MLX4_QP_STATE_ERR = 6, 71 MLX4_QP_STATE_SQ_DRAINING = 7, 72 MLX4_QP_NUM_STATE 73 }; 74 75 enum { 76 MLX4_QP_ST_RC = 0x0, 77 MLX4_QP_ST_UC = 0x1, 78 MLX4_QP_ST_RD = 0x2, 79 MLX4_QP_ST_UD = 0x3, 80 MLX4_QP_ST_XRC = 0x6, 81 MLX4_QP_ST_MLX = 0x7 82 }; 83 84 enum { 85 MLX4_QP_PM_MIGRATED = 0x3, 86 MLX4_QP_PM_ARMED = 0x0, 87 MLX4_QP_PM_REARM = 0x1 88 }; 89 90 enum { 91 /* params1 */ 92 MLX4_QP_BIT_SRE = 1 << 15, 93 MLX4_QP_BIT_SWE = 1 << 14, 94 MLX4_QP_BIT_SAE = 1 << 13, 95 /* params2 */ 96 MLX4_QP_BIT_RRE = 1 << 15, 97 MLX4_QP_BIT_RWE = 1 << 14, 98 MLX4_QP_BIT_RAE = 1 << 13, 99 MLX4_QP_BIT_FPP = 1 << 3, 100 MLX4_QP_BIT_RIC = 1 << 4, 101 }; 102 103 enum { 104 MLX4_RSS_HASH_XOR = 0, 105 MLX4_RSS_HASH_TOP = 1, 106 107 MLX4_RSS_UDP_IPV6 = 1 << 0, 108 MLX4_RSS_UDP_IPV4 = 1 << 1, 109 MLX4_RSS_TCP_IPV6 = 1 << 2, 110 MLX4_RSS_IPV6 = 1 << 3, 111 MLX4_RSS_TCP_IPV4 = 1 << 4, 112 MLX4_RSS_IPV4 = 1 << 5, 113 114 MLX4_RSS_BY_OUTER_HEADERS = 0 << 6, 115 MLX4_RSS_BY_INNER_HEADERS = 2 << 6, 116 MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6, 117 118 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 119 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 120 /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 121 MLX4_RSS_QPC_FLAG_OFFSET = 13, 122 }; 123 124 #define MLX4_EN_RSS_KEY_SIZE 40 125 126 struct mlx4_rss_context { 127 __be32 base_qpn; 128 __be32 default_qpn; 129 u16 reserved; 130 u8 hash_fn; 131 u8 flags; 132 __be32 rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)]; 133 __be32 base_qpn_udp; 134 }; 135 136 struct mlx4_qp_path { 137 u8 fl; 138 u8 vlan_control; 139 u8 disable_pkey_check; 140 u8 pkey_index; 141 u8 counter_index; 142 u8 grh_mylmc; 143 __be16 rlid; 144 u8 ackto; 145 u8 mgid_index; 146 u8 static_rate; 147 u8 hop_limit; 148 __be32 tclass_flowlabel; 149 u8 rgid[16]; 150 u8 sched_queue; 151 u8 vlan_index; 152 u8 feup; 153 u8 fvl_rx; 154 u8 reserved4[2]; 155 u8 dmac[ETH_ALEN]; 156 }; 157 158 enum { /* fl */ 159 MLX4_FL_CV = 1 << 6, 160 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2 161 }; 162 enum { /* vlan_control */ 163 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 164 MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */ 165 MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4, 166 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 167 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ 168 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 169 }; 170 171 enum { /* feup */ 172 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 173 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 174 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 175 }; 176 177 enum { /* fvl_rx */ 178 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 179 }; 180 181 struct mlx4_qp_context { 182 __be32 flags; 183 __be32 pd; 184 u8 mtu_msgmax; 185 u8 rq_size_stride; 186 u8 sq_size_stride; 187 u8 rlkey; 188 __be32 usr_page; 189 __be32 local_qpn; 190 __be32 remote_qpn; 191 struct mlx4_qp_path pri_path; 192 struct mlx4_qp_path alt_path; 193 __be32 params1; 194 u32 reserved1; 195 __be32 next_send_psn; 196 __be32 cqn_send; 197 u32 reserved2[2]; 198 __be32 last_acked_psn; 199 __be32 ssn; 200 __be32 params2; 201 __be32 rnr_nextrecvpsn; 202 __be32 xrcd; 203 __be32 cqn_recv; 204 __be64 db_rec_addr; 205 __be32 qkey; 206 __be32 srqn; 207 __be32 msn; 208 __be16 rq_wqe_counter; 209 __be16 sq_wqe_counter; 210 u32 reserved3[2]; 211 __be32 param3; 212 __be32 nummmcpeers_basemkey; 213 u8 log_page_size; 214 u8 reserved4[2]; 215 u8 mtt_base_addr_h; 216 __be32 mtt_base_addr_l; 217 u32 reserved5[10]; 218 }; 219 220 struct mlx4_update_qp_context { 221 __be64 qp_mask; 222 __be64 primary_addr_path_mask; 223 __be64 secondary_addr_path_mask; 224 u64 reserved1; 225 struct mlx4_qp_context qp_context; 226 u64 reserved2[58]; 227 }; 228 229 enum { 230 MLX4_UPD_QP_MASK_PM_STATE = 32, 231 MLX4_UPD_QP_MASK_VSD = 33, 232 }; 233 234 enum { 235 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 236 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 237 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 238 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 239 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 240 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 241 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 242 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 243 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 244 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 245 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 246 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 247 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 248 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 249 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 250 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 251 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 252 }; 253 254 enum { /* param3 */ 255 MLX4_STRIP_VLAN = 1 << 30 256 }; 257 258 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 259 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 260 261 enum { 262 MLX4_WQE_CTRL_NEC = 1 << 29, 263 MLX4_WQE_CTRL_IIP = 1 << 28, 264 MLX4_WQE_CTRL_ILP = 1 << 27, 265 MLX4_WQE_CTRL_FENCE = 1 << 6, 266 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 267 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 268 MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 269 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 270 MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 271 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 272 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 273 }; 274 275 struct mlx4_wqe_ctrl_seg { 276 __be32 owner_opcode; 277 union { 278 struct { 279 __be16 vlan_tag; 280 u8 ins_vlan; 281 u8 fence_size; 282 }; 283 __be32 bf_qpn; 284 }; 285 /* 286 * High 24 bits are SRC remote buffer; low 8 bits are flags: 287 * [7] SO (strong ordering) 288 * [5] TCP/UDP checksum 289 * [4] IP checksum 290 * [3:2] C (generate completion queue entry) 291 * [1] SE (solicited event) 292 * [0] FL (force loopback) 293 */ 294 union { 295 __be32 srcrb_flags; 296 __be16 srcrb_flags16[2]; 297 }; 298 /* 299 * imm is immediate data for send/RDMA write w/ immediate; 300 * also invalidation key for send with invalidate; input 301 * modifier for WQEs on CCQs. 302 */ 303 __be32 imm; 304 }; 305 306 enum { 307 MLX4_WQE_MLX_VL15 = 1 << 17, 308 MLX4_WQE_MLX_SLR = 1 << 16 309 }; 310 311 struct mlx4_wqe_mlx_seg { 312 u8 owner; 313 u8 reserved1[2]; 314 u8 opcode; 315 __be16 sched_prio; 316 u8 reserved2; 317 u8 size; 318 /* 319 * [17] VL15 320 * [16] SLR 321 * [15:12] static rate 322 * [11:8] SL 323 * [4] ICRC 324 * [3:2] C 325 * [0] FL (force loopback) 326 */ 327 __be32 flags; 328 __be16 rlid; 329 u16 reserved3; 330 }; 331 332 struct mlx4_wqe_datagram_seg { 333 __be32 av[8]; 334 __be32 dqpn; 335 __be32 qkey; 336 __be16 vlan; 337 u8 mac[ETH_ALEN]; 338 }; 339 340 struct mlx4_wqe_lso_seg { 341 __be32 mss_hdr_size; 342 __be32 header[0]; 343 }; 344 345 enum mlx4_wqe_bind_seg_flags2 { 346 MLX4_WQE_BIND_ZERO_BASED = (1 << 30), 347 MLX4_WQE_BIND_TYPE_2 = (1 << 31), 348 }; 349 350 struct mlx4_wqe_bind_seg { 351 __be32 flags1; 352 __be32 flags2; 353 __be32 new_rkey; 354 __be32 lkey; 355 __be64 addr; 356 __be64 length; 357 }; 358 359 enum { 360 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 361 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 362 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 363 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 364 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 365 }; 366 367 struct mlx4_wqe_fmr_seg { 368 __be32 flags; 369 __be32 mem_key; 370 __be64 buf_list; 371 __be64 start_addr; 372 __be64 reg_len; 373 __be32 offset; 374 __be32 page_size; 375 u32 reserved[2]; 376 }; 377 378 struct mlx4_wqe_fmr_ext_seg { 379 u8 flags; 380 u8 reserved; 381 __be16 app_mask; 382 __be16 wire_app_tag; 383 __be16 mem_app_tag; 384 __be32 wire_ref_tag_base; 385 __be32 mem_ref_tag_base; 386 }; 387 388 struct mlx4_wqe_local_inval_seg { 389 u64 reserved1; 390 __be32 mem_key; 391 u32 reserved2; 392 u64 reserved3[2]; 393 }; 394 395 struct mlx4_wqe_raddr_seg { 396 __be64 raddr; 397 __be32 rkey; 398 u32 reserved; 399 }; 400 401 struct mlx4_wqe_atomic_seg { 402 __be64 swap_add; 403 __be64 compare; 404 }; 405 406 struct mlx4_wqe_masked_atomic_seg { 407 __be64 swap_add; 408 __be64 compare; 409 __be64 swap_add_mask; 410 __be64 compare_mask; 411 }; 412 413 struct mlx4_wqe_data_seg { 414 __be32 byte_count; 415 __be32 lkey; 416 __be64 addr; 417 }; 418 419 enum { 420 MLX4_INLINE_ALIGN = 64, 421 MLX4_INLINE_SEG = 1 << 31, 422 }; 423 424 struct mlx4_wqe_inline_seg { 425 __be32 byte_count; 426 }; 427 428 enum mlx4_update_qp_attr { 429 MLX4_UPDATE_QP_SMAC = 1 << 0, 430 MLX4_UPDATE_QP_VSD = 1 << 2, 431 MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 2) - 1 432 }; 433 434 enum mlx4_update_qp_params_flags { 435 MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 0, 436 }; 437 438 struct mlx4_update_qp_params { 439 u8 smac_index; 440 u32 flags; 441 }; 442 443 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, 444 enum mlx4_update_qp_attr attr, 445 struct mlx4_update_qp_params *params); 446 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 447 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 448 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 449 int sqd_event, struct mlx4_qp *qp); 450 451 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 452 struct mlx4_qp_context *context); 453 454 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 455 struct mlx4_qp_context *context, 456 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 457 458 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 459 { 460 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 461 } 462 463 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 464 465 #endif /* MLX4_QP_H */ 466