1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 42 #include <linux/atomic.h> 43 44 #include <linux/clocksource.h> 45 46 #define MAX_MSIX_P_PORT 17 47 #define MAX_MSIX 64 48 #define MSIX_LEGACY_SZ 4 49 #define MIN_MSIX_P_PORT 5 50 51 enum { 52 MLX4_FLAG_MSI_X = 1 << 0, 53 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 54 MLX4_FLAG_MASTER = 1 << 2, 55 MLX4_FLAG_SLAVE = 1 << 3, 56 MLX4_FLAG_SRIOV = 1 << 4, 57 }; 58 59 enum { 60 MLX4_PORT_CAP_IS_SM = 1 << 1, 61 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 62 }; 63 64 enum { 65 MLX4_MAX_PORTS = 2, 66 MLX4_MAX_PORT_PKEYS = 128 67 }; 68 69 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 70 * These qkeys must not be allowed for general use. This is a 64k range, 71 * and to test for violation, we use the mask (protect against future chg). 72 */ 73 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 74 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 75 76 enum { 77 MLX4_BOARD_ID_LEN = 64 78 }; 79 80 enum { 81 MLX4_MAX_NUM_PF = 16, 82 MLX4_MAX_NUM_VF = 64, 83 MLX4_MFUNC_MAX = 80, 84 MLX4_MAX_EQ_NUM = 1024, 85 MLX4_MFUNC_EQ_NUM = 4, 86 MLX4_MFUNC_MAX_EQES = 8, 87 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 88 }; 89 90 /* Driver supports 3 diffrent device methods to manage traffic steering: 91 * -device managed - High level API for ib and eth flow steering. FW is 92 * managing flow steering tables. 93 * - B0 steering mode - Common low level API for ib and (if supported) eth. 94 * - A0 steering mode - Limited low level API for eth. In case of IB, 95 * B0 mode is in use. 96 */ 97 enum { 98 MLX4_STEERING_MODE_A0, 99 MLX4_STEERING_MODE_B0, 100 MLX4_STEERING_MODE_DEVICE_MANAGED 101 }; 102 103 static inline const char *mlx4_steering_mode_str(int steering_mode) 104 { 105 switch (steering_mode) { 106 case MLX4_STEERING_MODE_A0: 107 return "A0 steering"; 108 109 case MLX4_STEERING_MODE_B0: 110 return "B0 steering"; 111 112 case MLX4_STEERING_MODE_DEVICE_MANAGED: 113 return "Device managed flow steering"; 114 115 default: 116 return "Unrecognize steering mode"; 117 } 118 } 119 120 enum { 121 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 122 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 123 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 124 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 125 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 126 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 127 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 128 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 129 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 130 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 131 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 132 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 133 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 134 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 135 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 136 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 137 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 138 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 139 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 140 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 141 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 142 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 143 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 144 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 145 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 146 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 147 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 148 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 149 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 150 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 151 }; 152 153 enum { 154 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 155 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 156 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 157 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 158 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4, 159 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 160 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 161 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 162 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8 163 }; 164 165 enum { 166 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 167 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 168 }; 169 170 enum { 171 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 172 }; 173 174 enum { 175 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 176 }; 177 178 179 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 180 181 enum { 182 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 183 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 184 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 185 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 186 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 187 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 188 }; 189 190 enum mlx4_event { 191 MLX4_EVENT_TYPE_COMP = 0x00, 192 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 193 MLX4_EVENT_TYPE_COMM_EST = 0x02, 194 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 195 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 196 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 197 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 198 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 199 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 200 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 201 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 202 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 203 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 204 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 205 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 206 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 207 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 208 MLX4_EVENT_TYPE_CMD = 0x0a, 209 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 210 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 211 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 212 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 213 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 214 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 215 MLX4_EVENT_TYPE_NONE = 0xff, 216 }; 217 218 enum { 219 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 220 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 221 }; 222 223 enum { 224 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 225 }; 226 227 enum slave_port_state { 228 SLAVE_PORT_DOWN = 0, 229 SLAVE_PENDING_UP, 230 SLAVE_PORT_UP, 231 }; 232 233 enum slave_port_gen_event { 234 SLAVE_PORT_GEN_EVENT_DOWN = 0, 235 SLAVE_PORT_GEN_EVENT_UP, 236 SLAVE_PORT_GEN_EVENT_NONE, 237 }; 238 239 enum slave_port_state_event { 240 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 241 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 242 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 243 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 244 }; 245 246 enum { 247 MLX4_PERM_LOCAL_READ = 1 << 10, 248 MLX4_PERM_LOCAL_WRITE = 1 << 11, 249 MLX4_PERM_REMOTE_READ = 1 << 12, 250 MLX4_PERM_REMOTE_WRITE = 1 << 13, 251 MLX4_PERM_ATOMIC = 1 << 14, 252 MLX4_PERM_BIND_MW = 1 << 15, 253 }; 254 255 enum { 256 MLX4_OPCODE_NOP = 0x00, 257 MLX4_OPCODE_SEND_INVAL = 0x01, 258 MLX4_OPCODE_RDMA_WRITE = 0x08, 259 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 260 MLX4_OPCODE_SEND = 0x0a, 261 MLX4_OPCODE_SEND_IMM = 0x0b, 262 MLX4_OPCODE_LSO = 0x0e, 263 MLX4_OPCODE_RDMA_READ = 0x10, 264 MLX4_OPCODE_ATOMIC_CS = 0x11, 265 MLX4_OPCODE_ATOMIC_FA = 0x12, 266 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 267 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 268 MLX4_OPCODE_BIND_MW = 0x18, 269 MLX4_OPCODE_FMR = 0x19, 270 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 271 MLX4_OPCODE_CONFIG_CMD = 0x1f, 272 273 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 274 MLX4_RECV_OPCODE_SEND = 0x01, 275 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 276 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 277 278 MLX4_CQE_OPCODE_ERROR = 0x1e, 279 MLX4_CQE_OPCODE_RESIZE = 0x16, 280 }; 281 282 enum { 283 MLX4_STAT_RATE_OFFSET = 5 284 }; 285 286 enum mlx4_protocol { 287 MLX4_PROT_IB_IPV6 = 0, 288 MLX4_PROT_ETH, 289 MLX4_PROT_IB_IPV4, 290 MLX4_PROT_FCOE 291 }; 292 293 enum { 294 MLX4_MTT_FLAG_PRESENT = 1 295 }; 296 297 enum mlx4_qp_region { 298 MLX4_QP_REGION_FW = 0, 299 MLX4_QP_REGION_ETH_ADDR, 300 MLX4_QP_REGION_FC_ADDR, 301 MLX4_QP_REGION_FC_EXCH, 302 MLX4_NUM_QP_REGION 303 }; 304 305 enum mlx4_port_type { 306 MLX4_PORT_TYPE_NONE = 0, 307 MLX4_PORT_TYPE_IB = 1, 308 MLX4_PORT_TYPE_ETH = 2, 309 MLX4_PORT_TYPE_AUTO = 3 310 }; 311 312 enum mlx4_special_vlan_idx { 313 MLX4_NO_VLAN_IDX = 0, 314 MLX4_VLAN_MISS_IDX, 315 MLX4_VLAN_REGULAR 316 }; 317 318 enum mlx4_steer_type { 319 MLX4_MC_STEER = 0, 320 MLX4_UC_STEER, 321 MLX4_NUM_STEERS 322 }; 323 324 enum { 325 MLX4_NUM_FEXCH = 64 * 1024, 326 }; 327 328 enum { 329 MLX4_MAX_FAST_REG_PAGES = 511, 330 }; 331 332 enum { 333 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 334 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 335 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 336 }; 337 338 /* Port mgmt change event handling */ 339 enum { 340 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 341 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 342 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 343 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 344 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 345 }; 346 347 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 348 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 349 350 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 351 { 352 return (major << 32) | (minor << 16) | subminor; 353 } 354 355 struct mlx4_phys_caps { 356 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 357 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 358 u32 num_phys_eqs; 359 u32 base_sqpn; 360 u32 base_proxy_sqpn; 361 u32 base_tunnel_sqpn; 362 }; 363 364 struct mlx4_caps { 365 u64 fw_ver; 366 u32 function; 367 int num_ports; 368 int vl_cap[MLX4_MAX_PORTS + 1]; 369 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 370 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 371 u64 def_mac[MLX4_MAX_PORTS + 1]; 372 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 373 int gid_table_len[MLX4_MAX_PORTS + 1]; 374 int pkey_table_len[MLX4_MAX_PORTS + 1]; 375 int trans_type[MLX4_MAX_PORTS + 1]; 376 int vendor_oui[MLX4_MAX_PORTS + 1]; 377 int wavelength[MLX4_MAX_PORTS + 1]; 378 u64 trans_code[MLX4_MAX_PORTS + 1]; 379 int local_ca_ack_delay; 380 int num_uars; 381 u32 uar_page_size; 382 int bf_reg_size; 383 int bf_regs_per_page; 384 int max_sq_sg; 385 int max_rq_sg; 386 int num_qps; 387 int max_wqes; 388 int max_sq_desc_sz; 389 int max_rq_desc_sz; 390 int max_qp_init_rdma; 391 int max_qp_dest_rdma; 392 u32 *qp0_proxy; 393 u32 *qp1_proxy; 394 u32 *qp0_tunnel; 395 u32 *qp1_tunnel; 396 int num_srqs; 397 int max_srq_wqes; 398 int max_srq_sge; 399 int reserved_srqs; 400 int num_cqs; 401 int max_cqes; 402 int reserved_cqs; 403 int num_eqs; 404 int reserved_eqs; 405 int num_comp_vectors; 406 int comp_pool; 407 int num_mpts; 408 int max_fmr_maps; 409 int num_mtts; 410 int fmr_reserved_mtts; 411 int reserved_mtts; 412 int reserved_mrws; 413 int reserved_uars; 414 int num_mgms; 415 int num_amgms; 416 int reserved_mcgs; 417 int num_qp_per_mgm; 418 int steering_mode; 419 int fs_log_max_ucast_qp_range_size; 420 int num_pds; 421 int reserved_pds; 422 int max_xrcds; 423 int reserved_xrcds; 424 int mtt_entry_sz; 425 u32 max_msg_sz; 426 u32 page_size_cap; 427 u64 flags; 428 u64 flags2; 429 u32 bmme_flags; 430 u32 reserved_lkey; 431 u16 stat_rate_support; 432 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 433 int max_gso_sz; 434 int max_rss_tbl_sz; 435 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 436 int reserved_qps; 437 int reserved_qps_base[MLX4_NUM_QP_REGION]; 438 int log_num_macs; 439 int log_num_vlans; 440 int log_num_prios; 441 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 442 u8 supported_type[MLX4_MAX_PORTS + 1]; 443 u8 suggested_type[MLX4_MAX_PORTS + 1]; 444 u8 default_sense[MLX4_MAX_PORTS + 1]; 445 u32 port_mask[MLX4_MAX_PORTS + 1]; 446 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 447 u32 max_counters; 448 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 449 u16 sqp_demux; 450 u32 eqe_size; 451 u32 cqe_size; 452 u8 eqe_factor; 453 u32 userspace_caps; /* userspace must be aware of these */ 454 u32 function_caps; /* VFs must be aware of these */ 455 u16 hca_core_clock; 456 }; 457 458 struct mlx4_buf_list { 459 void *buf; 460 dma_addr_t map; 461 }; 462 463 struct mlx4_buf { 464 struct mlx4_buf_list direct; 465 struct mlx4_buf_list *page_list; 466 int nbufs; 467 int npages; 468 int page_shift; 469 }; 470 471 struct mlx4_mtt { 472 u32 offset; 473 int order; 474 int page_shift; 475 }; 476 477 enum { 478 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 479 }; 480 481 struct mlx4_db_pgdir { 482 struct list_head list; 483 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 484 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 485 unsigned long *bits[2]; 486 __be32 *db_page; 487 dma_addr_t db_dma; 488 }; 489 490 struct mlx4_ib_user_db_page; 491 492 struct mlx4_db { 493 __be32 *db; 494 union { 495 struct mlx4_db_pgdir *pgdir; 496 struct mlx4_ib_user_db_page *user_page; 497 } u; 498 dma_addr_t dma; 499 int index; 500 int order; 501 }; 502 503 struct mlx4_hwq_resources { 504 struct mlx4_db db; 505 struct mlx4_mtt mtt; 506 struct mlx4_buf buf; 507 }; 508 509 struct mlx4_mr { 510 struct mlx4_mtt mtt; 511 u64 iova; 512 u64 size; 513 u32 key; 514 u32 pd; 515 u32 access; 516 int enabled; 517 }; 518 519 enum mlx4_mw_type { 520 MLX4_MW_TYPE_1 = 1, 521 MLX4_MW_TYPE_2 = 2, 522 }; 523 524 struct mlx4_mw { 525 u32 key; 526 u32 pd; 527 enum mlx4_mw_type type; 528 int enabled; 529 }; 530 531 struct mlx4_fmr { 532 struct mlx4_mr mr; 533 struct mlx4_mpt_entry *mpt; 534 __be64 *mtts; 535 dma_addr_t dma_handle; 536 int max_pages; 537 int max_maps; 538 int maps; 539 u8 page_shift; 540 }; 541 542 struct mlx4_uar { 543 unsigned long pfn; 544 int index; 545 struct list_head bf_list; 546 unsigned free_bf_bmap; 547 void __iomem *map; 548 void __iomem *bf_map; 549 }; 550 551 struct mlx4_bf { 552 unsigned long offset; 553 int buf_size; 554 struct mlx4_uar *uar; 555 void __iomem *reg; 556 }; 557 558 struct mlx4_cq { 559 void (*comp) (struct mlx4_cq *); 560 void (*event) (struct mlx4_cq *, enum mlx4_event); 561 562 struct mlx4_uar *uar; 563 564 u32 cons_index; 565 566 __be32 *set_ci_db; 567 __be32 *arm_db; 568 int arm_sn; 569 570 int cqn; 571 unsigned vector; 572 573 atomic_t refcount; 574 struct completion free; 575 }; 576 577 struct mlx4_qp { 578 void (*event) (struct mlx4_qp *, enum mlx4_event); 579 580 int qpn; 581 582 atomic_t refcount; 583 struct completion free; 584 }; 585 586 struct mlx4_srq { 587 void (*event) (struct mlx4_srq *, enum mlx4_event); 588 589 int srqn; 590 int max; 591 int max_gs; 592 int wqe_shift; 593 594 atomic_t refcount; 595 struct completion free; 596 }; 597 598 struct mlx4_av { 599 __be32 port_pd; 600 u8 reserved1; 601 u8 g_slid; 602 __be16 dlid; 603 u8 reserved2; 604 u8 gid_index; 605 u8 stat_rate; 606 u8 hop_limit; 607 __be32 sl_tclass_flowlabel; 608 u8 dgid[16]; 609 }; 610 611 struct mlx4_eth_av { 612 __be32 port_pd; 613 u8 reserved1; 614 u8 smac_idx; 615 u16 reserved2; 616 u8 reserved3; 617 u8 gid_index; 618 u8 stat_rate; 619 u8 hop_limit; 620 __be32 sl_tclass_flowlabel; 621 u8 dgid[16]; 622 u32 reserved4[2]; 623 __be16 vlan; 624 u8 mac[ETH_ALEN]; 625 }; 626 627 union mlx4_ext_av { 628 struct mlx4_av ib; 629 struct mlx4_eth_av eth; 630 }; 631 632 struct mlx4_counter { 633 u8 reserved1[3]; 634 u8 counter_mode; 635 __be32 num_ifc; 636 u32 reserved2[2]; 637 __be64 rx_frames; 638 __be64 rx_bytes; 639 __be64 tx_frames; 640 __be64 tx_bytes; 641 }; 642 643 struct mlx4_dev { 644 struct pci_dev *pdev; 645 unsigned long flags; 646 unsigned long num_slaves; 647 struct mlx4_caps caps; 648 struct mlx4_phys_caps phys_caps; 649 struct radix_tree_root qp_table_tree; 650 u8 rev_id; 651 char board_id[MLX4_BOARD_ID_LEN]; 652 int num_vfs; 653 int oper_log_mgm_entry_size; 654 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 655 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 656 }; 657 658 struct mlx4_eqe { 659 u8 reserved1; 660 u8 type; 661 u8 reserved2; 662 u8 subtype; 663 union { 664 u32 raw[6]; 665 struct { 666 __be32 cqn; 667 } __packed comp; 668 struct { 669 u16 reserved1; 670 __be16 token; 671 u32 reserved2; 672 u8 reserved3[3]; 673 u8 status; 674 __be64 out_param; 675 } __packed cmd; 676 struct { 677 __be32 qpn; 678 } __packed qp; 679 struct { 680 __be32 srqn; 681 } __packed srq; 682 struct { 683 __be32 cqn; 684 u32 reserved1; 685 u8 reserved2[3]; 686 u8 syndrome; 687 } __packed cq_err; 688 struct { 689 u32 reserved1[2]; 690 __be32 port; 691 } __packed port_change; 692 struct { 693 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 694 u32 reserved; 695 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 696 } __packed comm_channel_arm; 697 struct { 698 u8 port; 699 u8 reserved[3]; 700 __be64 mac; 701 } __packed mac_update; 702 struct { 703 __be32 slave_id; 704 } __packed flr_event; 705 struct { 706 __be16 current_temperature; 707 __be16 warning_threshold; 708 } __packed warming; 709 struct { 710 u8 reserved[3]; 711 u8 port; 712 union { 713 struct { 714 __be16 mstr_sm_lid; 715 __be16 port_lid; 716 __be32 changed_attr; 717 u8 reserved[3]; 718 u8 mstr_sm_sl; 719 __be64 gid_prefix; 720 } __packed port_info; 721 struct { 722 __be32 block_ptr; 723 __be32 tbl_entries_mask; 724 } __packed tbl_change_info; 725 } params; 726 } __packed port_mgmt_change; 727 } event; 728 u8 slave_id; 729 u8 reserved3[2]; 730 u8 owner; 731 } __packed; 732 733 struct mlx4_init_port_param { 734 int set_guid0; 735 int set_node_guid; 736 int set_si_guid; 737 u16 mtu; 738 int port_width_cap; 739 u16 vl_cap; 740 u16 max_gid; 741 u16 max_pkey; 742 u64 guid0; 743 u64 node_guid; 744 u64 si_guid; 745 }; 746 747 #define mlx4_foreach_port(port, dev, type) \ 748 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 749 if ((type) == (dev)->caps.port_mask[(port)]) 750 751 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 752 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 753 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 754 755 #define mlx4_foreach_ib_transport_port(port, dev) \ 756 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 757 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 758 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 759 760 #define MLX4_INVALID_SLAVE_ID 0xFF 761 762 void handle_port_mgmt_change_event(struct work_struct *work); 763 764 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 765 { 766 return dev->caps.function; 767 } 768 769 static inline int mlx4_is_master(struct mlx4_dev *dev) 770 { 771 return dev->flags & MLX4_FLAG_MASTER; 772 } 773 774 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 775 { 776 return (qpn < dev->phys_caps.base_sqpn + 8 + 777 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 778 } 779 780 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 781 { 782 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 783 784 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 785 return 1; 786 787 return 0; 788 } 789 790 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 791 { 792 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 793 } 794 795 static inline int mlx4_is_slave(struct mlx4_dev *dev) 796 { 797 return dev->flags & MLX4_FLAG_SLAVE; 798 } 799 800 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 801 struct mlx4_buf *buf); 802 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 803 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 804 { 805 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 806 return buf->direct.buf + offset; 807 else 808 return buf->page_list[offset >> PAGE_SHIFT].buf + 809 (offset & (PAGE_SIZE - 1)); 810 } 811 812 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 813 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 814 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 815 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 816 817 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 818 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 819 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 820 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 821 822 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 823 struct mlx4_mtt *mtt); 824 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 825 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 826 827 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 828 int npages, int page_shift, struct mlx4_mr *mr); 829 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 830 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 831 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 832 struct mlx4_mw *mw); 833 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 834 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 835 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 836 int start_index, int npages, u64 *page_list); 837 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 838 struct mlx4_buf *buf); 839 840 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 841 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 842 843 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 844 int size, int max_direct); 845 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 846 int size); 847 848 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 849 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 850 unsigned vector, int collapsed, int timestamp_en); 851 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 852 853 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 854 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 855 856 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 857 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 858 859 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 860 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 861 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 862 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 863 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 864 865 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 866 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 867 868 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 869 int block_mcast_loopback, enum mlx4_protocol prot); 870 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 871 enum mlx4_protocol prot); 872 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 873 u8 port, int block_mcast_loopback, 874 enum mlx4_protocol protocol, u64 *reg_id); 875 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 876 enum mlx4_protocol protocol, u64 reg_id); 877 878 enum { 879 MLX4_DOMAIN_UVERBS = 0x1000, 880 MLX4_DOMAIN_ETHTOOL = 0x2000, 881 MLX4_DOMAIN_RFS = 0x3000, 882 MLX4_DOMAIN_NIC = 0x5000, 883 }; 884 885 enum mlx4_net_trans_rule_id { 886 MLX4_NET_TRANS_RULE_ID_ETH = 0, 887 MLX4_NET_TRANS_RULE_ID_IB, 888 MLX4_NET_TRANS_RULE_ID_IPV6, 889 MLX4_NET_TRANS_RULE_ID_IPV4, 890 MLX4_NET_TRANS_RULE_ID_TCP, 891 MLX4_NET_TRANS_RULE_ID_UDP, 892 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 893 }; 894 895 extern const u16 __sw_id_hw[]; 896 897 static inline int map_hw_to_sw_id(u16 header_id) 898 { 899 900 int i; 901 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 902 if (header_id == __sw_id_hw[i]) 903 return i; 904 } 905 return -EINVAL; 906 } 907 908 enum mlx4_net_trans_promisc_mode { 909 MLX4_FS_REGULAR = 1, 910 MLX4_FS_ALL_DEFAULT, 911 MLX4_FS_MC_DEFAULT, 912 MLX4_FS_UC_SNIFFER, 913 MLX4_FS_MC_SNIFFER, 914 MLX4_FS_MODE_NUM, /* should be last */ 915 }; 916 917 struct mlx4_spec_eth { 918 u8 dst_mac[ETH_ALEN]; 919 u8 dst_mac_msk[ETH_ALEN]; 920 u8 src_mac[ETH_ALEN]; 921 u8 src_mac_msk[ETH_ALEN]; 922 u8 ether_type_enable; 923 __be16 ether_type; 924 __be16 vlan_id_msk; 925 __be16 vlan_id; 926 }; 927 928 struct mlx4_spec_tcp_udp { 929 __be16 dst_port; 930 __be16 dst_port_msk; 931 __be16 src_port; 932 __be16 src_port_msk; 933 }; 934 935 struct mlx4_spec_ipv4 { 936 __be32 dst_ip; 937 __be32 dst_ip_msk; 938 __be32 src_ip; 939 __be32 src_ip_msk; 940 }; 941 942 struct mlx4_spec_ib { 943 __be32 l3_qpn; 944 __be32 qpn_msk; 945 u8 dst_gid[16]; 946 u8 dst_gid_msk[16]; 947 }; 948 949 struct mlx4_spec_list { 950 struct list_head list; 951 enum mlx4_net_trans_rule_id id; 952 union { 953 struct mlx4_spec_eth eth; 954 struct mlx4_spec_ib ib; 955 struct mlx4_spec_ipv4 ipv4; 956 struct mlx4_spec_tcp_udp tcp_udp; 957 }; 958 }; 959 960 enum mlx4_net_trans_hw_rule_queue { 961 MLX4_NET_TRANS_Q_FIFO, 962 MLX4_NET_TRANS_Q_LIFO, 963 }; 964 965 struct mlx4_net_trans_rule { 966 struct list_head list; 967 enum mlx4_net_trans_hw_rule_queue queue_mode; 968 bool exclusive; 969 bool allow_loopback; 970 enum mlx4_net_trans_promisc_mode promisc_mode; 971 u8 port; 972 u16 priority; 973 u32 qpn; 974 }; 975 976 struct mlx4_net_trans_rule_hw_ctrl { 977 __be16 prio; 978 u8 type; 979 u8 flags; 980 u8 rsvd1; 981 u8 funcid; 982 u8 vep; 983 u8 port; 984 __be32 qpn; 985 __be32 rsvd2; 986 }; 987 988 struct mlx4_net_trans_rule_hw_ib { 989 u8 size; 990 u8 rsvd1; 991 __be16 id; 992 u32 rsvd2; 993 __be32 l3_qpn; 994 __be32 qpn_mask; 995 u8 dst_gid[16]; 996 u8 dst_gid_msk[16]; 997 } __packed; 998 999 struct mlx4_net_trans_rule_hw_eth { 1000 u8 size; 1001 u8 rsvd; 1002 __be16 id; 1003 u8 rsvd1[6]; 1004 u8 dst_mac[6]; 1005 u16 rsvd2; 1006 u8 dst_mac_msk[6]; 1007 u16 rsvd3; 1008 u8 src_mac[6]; 1009 u16 rsvd4; 1010 u8 src_mac_msk[6]; 1011 u8 rsvd5; 1012 u8 ether_type_enable; 1013 __be16 ether_type; 1014 __be16 vlan_tag_msk; 1015 __be16 vlan_tag; 1016 } __packed; 1017 1018 struct mlx4_net_trans_rule_hw_tcp_udp { 1019 u8 size; 1020 u8 rsvd; 1021 __be16 id; 1022 __be16 rsvd1[3]; 1023 __be16 dst_port; 1024 __be16 rsvd2; 1025 __be16 dst_port_msk; 1026 __be16 rsvd3; 1027 __be16 src_port; 1028 __be16 rsvd4; 1029 __be16 src_port_msk; 1030 } __packed; 1031 1032 struct mlx4_net_trans_rule_hw_ipv4 { 1033 u8 size; 1034 u8 rsvd; 1035 __be16 id; 1036 __be32 rsvd1; 1037 __be32 dst_ip; 1038 __be32 dst_ip_msk; 1039 __be32 src_ip; 1040 __be32 src_ip_msk; 1041 } __packed; 1042 1043 struct _rule_hw { 1044 union { 1045 struct { 1046 u8 size; 1047 u8 rsvd; 1048 __be16 id; 1049 }; 1050 struct mlx4_net_trans_rule_hw_eth eth; 1051 struct mlx4_net_trans_rule_hw_ib ib; 1052 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1053 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1054 }; 1055 }; 1056 1057 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1058 enum mlx4_net_trans_promisc_mode mode); 1059 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1060 enum mlx4_net_trans_promisc_mode mode); 1061 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1062 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1063 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1064 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1065 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1066 1067 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1068 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1069 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1070 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1071 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); 1072 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1073 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1074 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1075 u8 promisc); 1076 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1077 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1078 u8 *pg, u16 *ratelimit); 1079 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1080 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1081 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 1082 1083 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1084 int npages, u64 iova, u32 *lkey, u32 *rkey); 1085 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1086 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1087 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1088 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1089 u32 *lkey, u32 *rkey); 1090 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1091 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1092 int mlx4_test_interrupts(struct mlx4_dev *dev); 1093 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1094 int *vector); 1095 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1096 1097 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1098 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1099 1100 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1101 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1102 1103 int mlx4_flow_attach(struct mlx4_dev *dev, 1104 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1105 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1106 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1107 enum mlx4_net_trans_promisc_mode flow_type); 1108 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1109 enum mlx4_net_trans_rule_id id); 1110 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1111 1112 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1113 int i, int val); 1114 1115 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1116 1117 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1118 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1119 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1120 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1121 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1122 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1123 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1124 1125 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1126 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1127 1128 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1129 1130 #endif /* MLX4_DEVICE_H */ 1131