1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/pci.h> 37 #include <linux/completion.h> 38 #include <linux/radix-tree.h> 39 40 #include <asm/atomic.h> 41 42 enum { 43 MLX4_FLAG_MSI_X = 1 << 0, 44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 45 }; 46 47 enum { 48 MLX4_MAX_PORTS = 2 49 }; 50 51 enum { 52 MLX4_BOARD_ID_LEN = 64 53 }; 54 55 enum { 56 MLX4_DEV_CAP_FLAG_RC = 1 << 0, 57 MLX4_DEV_CAP_FLAG_UC = 1 << 1, 58 MLX4_DEV_CAP_FLAG_UD = 1 << 2, 59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, 60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, 61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, 62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, 63 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, 64 MLX4_DEV_CAP_FLAG_APM = 1 << 17, 65 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, 66 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, 67 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, 68 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21 69 }; 70 71 enum { 72 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 73 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 74 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 75 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 76 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 77 }; 78 79 enum mlx4_event { 80 MLX4_EVENT_TYPE_COMP = 0x00, 81 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 82 MLX4_EVENT_TYPE_COMM_EST = 0x02, 83 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 84 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 85 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 86 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 87 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 88 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 89 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 90 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 91 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 92 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 93 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 94 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 95 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 96 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 97 MLX4_EVENT_TYPE_CMD = 0x0a 98 }; 99 100 enum { 101 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 102 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 103 }; 104 105 enum { 106 MLX4_PERM_LOCAL_READ = 1 << 10, 107 MLX4_PERM_LOCAL_WRITE = 1 << 11, 108 MLX4_PERM_REMOTE_READ = 1 << 12, 109 MLX4_PERM_REMOTE_WRITE = 1 << 13, 110 MLX4_PERM_ATOMIC = 1 << 14 111 }; 112 113 enum { 114 MLX4_OPCODE_NOP = 0x00, 115 MLX4_OPCODE_SEND_INVAL = 0x01, 116 MLX4_OPCODE_RDMA_WRITE = 0x08, 117 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 118 MLX4_OPCODE_SEND = 0x0a, 119 MLX4_OPCODE_SEND_IMM = 0x0b, 120 MLX4_OPCODE_LSO = 0x0e, 121 MLX4_OPCODE_RDMA_READ = 0x10, 122 MLX4_OPCODE_ATOMIC_CS = 0x11, 123 MLX4_OPCODE_ATOMIC_FA = 0x12, 124 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14, 125 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15, 126 MLX4_OPCODE_BIND_MW = 0x18, 127 MLX4_OPCODE_FMR = 0x19, 128 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 129 MLX4_OPCODE_CONFIG_CMD = 0x1f, 130 131 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 132 MLX4_RECV_OPCODE_SEND = 0x01, 133 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 134 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 135 136 MLX4_CQE_OPCODE_ERROR = 0x1e, 137 MLX4_CQE_OPCODE_RESIZE = 0x16, 138 }; 139 140 enum { 141 MLX4_STAT_RATE_OFFSET = 5 142 }; 143 144 enum { 145 MLX4_MTT_FLAG_PRESENT = 1 146 }; 147 148 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 149 { 150 return (major << 32) | (minor << 16) | subminor; 151 } 152 153 struct mlx4_caps { 154 u64 fw_ver; 155 int num_ports; 156 int vl_cap[MLX4_MAX_PORTS + 1]; 157 int mtu_cap[MLX4_MAX_PORTS + 1]; 158 int gid_table_len[MLX4_MAX_PORTS + 1]; 159 int pkey_table_len[MLX4_MAX_PORTS + 1]; 160 int local_ca_ack_delay; 161 int num_uars; 162 int bf_reg_size; 163 int bf_regs_per_page; 164 int max_sq_sg; 165 int max_rq_sg; 166 int num_qps; 167 int max_wqes; 168 int max_sq_desc_sz; 169 int max_rq_desc_sz; 170 int max_qp_init_rdma; 171 int max_qp_dest_rdma; 172 int reserved_qps; 173 int sqp_start; 174 int num_srqs; 175 int max_srq_wqes; 176 int max_srq_sge; 177 int reserved_srqs; 178 int num_cqs; 179 int max_cqes; 180 int reserved_cqs; 181 int num_eqs; 182 int reserved_eqs; 183 int num_mpts; 184 int num_mtt_segs; 185 int fmr_reserved_mtts; 186 int reserved_mtts; 187 int reserved_mrws; 188 int reserved_uars; 189 int num_mgms; 190 int num_amgms; 191 int reserved_mcgs; 192 int num_qp_per_mgm; 193 int num_pds; 194 int reserved_pds; 195 int mtt_entry_sz; 196 u32 max_msg_sz; 197 u32 page_size_cap; 198 u32 flags; 199 u32 bmme_flags; 200 u32 reserved_lkey; 201 u16 stat_rate_support; 202 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 203 int max_gso_sz; 204 }; 205 206 struct mlx4_buf_list { 207 void *buf; 208 dma_addr_t map; 209 }; 210 211 struct mlx4_buf { 212 struct mlx4_buf_list direct; 213 struct mlx4_buf_list *page_list; 214 int nbufs; 215 int npages; 216 int page_shift; 217 }; 218 219 struct mlx4_mtt { 220 u32 first_seg; 221 int order; 222 int page_shift; 223 }; 224 225 enum { 226 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 227 }; 228 229 struct mlx4_db_pgdir { 230 struct list_head list; 231 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 232 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 233 unsigned long *bits[2]; 234 __be32 *db_page; 235 dma_addr_t db_dma; 236 }; 237 238 struct mlx4_ib_user_db_page; 239 240 struct mlx4_db { 241 __be32 *db; 242 union { 243 struct mlx4_db_pgdir *pgdir; 244 struct mlx4_ib_user_db_page *user_page; 245 } u; 246 dma_addr_t dma; 247 int index; 248 int order; 249 }; 250 251 struct mlx4_hwq_resources { 252 struct mlx4_db db; 253 struct mlx4_mtt mtt; 254 struct mlx4_buf buf; 255 }; 256 257 struct mlx4_mr { 258 struct mlx4_mtt mtt; 259 u64 iova; 260 u64 size; 261 u32 key; 262 u32 pd; 263 u32 access; 264 int enabled; 265 }; 266 267 struct mlx4_fmr { 268 struct mlx4_mr mr; 269 struct mlx4_mpt_entry *mpt; 270 __be64 *mtts; 271 dma_addr_t dma_handle; 272 int max_pages; 273 int max_maps; 274 int maps; 275 u8 page_shift; 276 }; 277 278 struct mlx4_uar { 279 unsigned long pfn; 280 int index; 281 }; 282 283 struct mlx4_cq { 284 void (*comp) (struct mlx4_cq *); 285 void (*event) (struct mlx4_cq *, enum mlx4_event); 286 287 struct mlx4_uar *uar; 288 289 u32 cons_index; 290 291 __be32 *set_ci_db; 292 __be32 *arm_db; 293 int arm_sn; 294 295 int cqn; 296 297 atomic_t refcount; 298 struct completion free; 299 }; 300 301 struct mlx4_qp { 302 void (*event) (struct mlx4_qp *, enum mlx4_event); 303 304 int qpn; 305 306 atomic_t refcount; 307 struct completion free; 308 }; 309 310 struct mlx4_srq { 311 void (*event) (struct mlx4_srq *, enum mlx4_event); 312 313 int srqn; 314 int max; 315 int max_gs; 316 int wqe_shift; 317 318 atomic_t refcount; 319 struct completion free; 320 }; 321 322 struct mlx4_av { 323 __be32 port_pd; 324 u8 reserved1; 325 u8 g_slid; 326 __be16 dlid; 327 u8 reserved2; 328 u8 gid_index; 329 u8 stat_rate; 330 u8 hop_limit; 331 __be32 sl_tclass_flowlabel; 332 u8 dgid[16]; 333 }; 334 335 struct mlx4_dev { 336 struct pci_dev *pdev; 337 unsigned long flags; 338 struct mlx4_caps caps; 339 struct radix_tree_root qp_table_tree; 340 u32 rev_id; 341 char board_id[MLX4_BOARD_ID_LEN]; 342 }; 343 344 struct mlx4_init_port_param { 345 int set_guid0; 346 int set_node_guid; 347 int set_si_guid; 348 u16 mtu; 349 int port_width_cap; 350 u16 vl_cap; 351 u16 max_gid; 352 u16 max_pkey; 353 u64 guid0; 354 u64 node_guid; 355 u64 si_guid; 356 }; 357 358 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 359 struct mlx4_buf *buf); 360 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 361 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 362 { 363 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 364 return buf->direct.buf + offset; 365 else 366 return buf->page_list[offset >> PAGE_SHIFT].buf + 367 (offset & (PAGE_SIZE - 1)); 368 } 369 370 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 371 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 372 373 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 374 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 375 376 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 377 struct mlx4_mtt *mtt); 378 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 379 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 380 381 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 382 int npages, int page_shift, struct mlx4_mr *mr); 383 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 384 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 385 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 386 int start_index, int npages, u64 *page_list); 387 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 388 struct mlx4_buf *buf); 389 390 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 391 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 392 393 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 394 int size, int max_direct); 395 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 396 int size); 397 398 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 399 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 400 int collapsed); 401 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 402 403 int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp); 404 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 405 406 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, 407 u64 db_rec, struct mlx4_srq *srq); 408 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 409 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 410 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 411 412 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 413 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 414 415 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 416 int block_mcast_loopback); 417 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); 418 419 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 420 int npages, u64 iova, u32 *lkey, u32 *rkey); 421 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 422 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 423 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 424 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 425 u32 *lkey, u32 *rkey); 426 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 427 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 428 429 #endif /* MLX4_DEVICE_H */ 430