1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/pci.h> 37 #include <linux/completion.h> 38 #include <linux/radix-tree.h> 39 40 #include <asm/atomic.h> 41 42 enum { 43 MLX4_FLAG_MSI_X = 1 << 0, 44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 45 }; 46 47 enum { 48 MLX4_MAX_PORTS = 2 49 }; 50 51 enum { 52 MLX4_BOARD_ID_LEN = 64 53 }; 54 55 enum { 56 MLX4_DEV_CAP_FLAG_RC = 1 << 0, 57 MLX4_DEV_CAP_FLAG_UC = 1 << 1, 58 MLX4_DEV_CAP_FLAG_UD = 1 << 2, 59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, 60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, 61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, 62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, 63 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, 64 MLX4_DEV_CAP_FLAG_APM = 1 << 17, 65 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, 66 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, 67 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, 68 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21 69 }; 70 71 enum { 72 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 73 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 74 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 75 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 76 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 77 }; 78 79 enum mlx4_event { 80 MLX4_EVENT_TYPE_COMP = 0x00, 81 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 82 MLX4_EVENT_TYPE_COMM_EST = 0x02, 83 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 84 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 85 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 86 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 87 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 88 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 89 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 90 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 91 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 92 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 93 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 94 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 95 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 96 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 97 MLX4_EVENT_TYPE_CMD = 0x0a 98 }; 99 100 enum { 101 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 102 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 103 }; 104 105 enum { 106 MLX4_PERM_LOCAL_READ = 1 << 10, 107 MLX4_PERM_LOCAL_WRITE = 1 << 11, 108 MLX4_PERM_REMOTE_READ = 1 << 12, 109 MLX4_PERM_REMOTE_WRITE = 1 << 13, 110 MLX4_PERM_ATOMIC = 1 << 14 111 }; 112 113 enum { 114 MLX4_OPCODE_NOP = 0x00, 115 MLX4_OPCODE_SEND_INVAL = 0x01, 116 MLX4_OPCODE_RDMA_WRITE = 0x08, 117 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 118 MLX4_OPCODE_SEND = 0x0a, 119 MLX4_OPCODE_SEND_IMM = 0x0b, 120 MLX4_OPCODE_LSO = 0x0e, 121 MLX4_OPCODE_RDMA_READ = 0x10, 122 MLX4_OPCODE_ATOMIC_CS = 0x11, 123 MLX4_OPCODE_ATOMIC_FA = 0x12, 124 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14, 125 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15, 126 MLX4_OPCODE_BIND_MW = 0x18, 127 MLX4_OPCODE_FMR = 0x19, 128 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 129 MLX4_OPCODE_CONFIG_CMD = 0x1f, 130 131 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 132 MLX4_RECV_OPCODE_SEND = 0x01, 133 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 134 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 135 136 MLX4_CQE_OPCODE_ERROR = 0x1e, 137 MLX4_CQE_OPCODE_RESIZE = 0x16, 138 }; 139 140 enum { 141 MLX4_STAT_RATE_OFFSET = 5 142 }; 143 144 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 145 { 146 return (major << 32) | (minor << 16) | subminor; 147 } 148 149 struct mlx4_caps { 150 u64 fw_ver; 151 int num_ports; 152 int vl_cap[MLX4_MAX_PORTS + 1]; 153 int mtu_cap[MLX4_MAX_PORTS + 1]; 154 int gid_table_len[MLX4_MAX_PORTS + 1]; 155 int pkey_table_len[MLX4_MAX_PORTS + 1]; 156 int local_ca_ack_delay; 157 int num_uars; 158 int bf_reg_size; 159 int bf_regs_per_page; 160 int max_sq_sg; 161 int max_rq_sg; 162 int num_qps; 163 int max_wqes; 164 int max_sq_desc_sz; 165 int max_rq_desc_sz; 166 int max_qp_init_rdma; 167 int max_qp_dest_rdma; 168 int reserved_qps; 169 int sqp_start; 170 int num_srqs; 171 int max_srq_wqes; 172 int max_srq_sge; 173 int reserved_srqs; 174 int num_cqs; 175 int max_cqes; 176 int reserved_cqs; 177 int num_eqs; 178 int reserved_eqs; 179 int num_mpts; 180 int num_mtt_segs; 181 int fmr_reserved_mtts; 182 int reserved_mtts; 183 int reserved_mrws; 184 int reserved_uars; 185 int num_mgms; 186 int num_amgms; 187 int reserved_mcgs; 188 int num_qp_per_mgm; 189 int num_pds; 190 int reserved_pds; 191 int mtt_entry_sz; 192 u32 max_msg_sz; 193 u32 page_size_cap; 194 u32 flags; 195 u32 bmme_flags; 196 u32 reserved_lkey; 197 u16 stat_rate_support; 198 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 199 int max_gso_sz; 200 }; 201 202 struct mlx4_buf_list { 203 void *buf; 204 dma_addr_t map; 205 }; 206 207 struct mlx4_buf { 208 struct mlx4_buf_list direct; 209 struct mlx4_buf_list *page_list; 210 int nbufs; 211 int npages; 212 int page_shift; 213 }; 214 215 struct mlx4_mtt { 216 u32 first_seg; 217 int order; 218 int page_shift; 219 }; 220 221 enum { 222 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 223 }; 224 225 struct mlx4_db_pgdir { 226 struct list_head list; 227 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 228 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 229 unsigned long *bits[2]; 230 __be32 *db_page; 231 dma_addr_t db_dma; 232 }; 233 234 struct mlx4_ib_user_db_page; 235 236 struct mlx4_db { 237 __be32 *db; 238 union { 239 struct mlx4_db_pgdir *pgdir; 240 struct mlx4_ib_user_db_page *user_page; 241 } u; 242 dma_addr_t dma; 243 int index; 244 int order; 245 }; 246 247 struct mlx4_hwq_resources { 248 struct mlx4_db db; 249 struct mlx4_mtt mtt; 250 struct mlx4_buf buf; 251 }; 252 253 struct mlx4_mr { 254 struct mlx4_mtt mtt; 255 u64 iova; 256 u64 size; 257 u32 key; 258 u32 pd; 259 u32 access; 260 int enabled; 261 }; 262 263 struct mlx4_fmr { 264 struct mlx4_mr mr; 265 struct mlx4_mpt_entry *mpt; 266 __be64 *mtts; 267 dma_addr_t dma_handle; 268 int max_pages; 269 int max_maps; 270 int maps; 271 u8 page_shift; 272 }; 273 274 struct mlx4_uar { 275 unsigned long pfn; 276 int index; 277 }; 278 279 struct mlx4_cq { 280 void (*comp) (struct mlx4_cq *); 281 void (*event) (struct mlx4_cq *, enum mlx4_event); 282 283 struct mlx4_uar *uar; 284 285 u32 cons_index; 286 287 __be32 *set_ci_db; 288 __be32 *arm_db; 289 int arm_sn; 290 291 int cqn; 292 293 atomic_t refcount; 294 struct completion free; 295 }; 296 297 struct mlx4_qp { 298 void (*event) (struct mlx4_qp *, enum mlx4_event); 299 300 int qpn; 301 302 atomic_t refcount; 303 struct completion free; 304 }; 305 306 struct mlx4_srq { 307 void (*event) (struct mlx4_srq *, enum mlx4_event); 308 309 int srqn; 310 int max; 311 int max_gs; 312 int wqe_shift; 313 314 atomic_t refcount; 315 struct completion free; 316 }; 317 318 struct mlx4_av { 319 __be32 port_pd; 320 u8 reserved1; 321 u8 g_slid; 322 __be16 dlid; 323 u8 reserved2; 324 u8 gid_index; 325 u8 stat_rate; 326 u8 hop_limit; 327 __be32 sl_tclass_flowlabel; 328 u8 dgid[16]; 329 }; 330 331 struct mlx4_dev { 332 struct pci_dev *pdev; 333 unsigned long flags; 334 struct mlx4_caps caps; 335 struct radix_tree_root qp_table_tree; 336 u32 rev_id; 337 char board_id[MLX4_BOARD_ID_LEN]; 338 }; 339 340 struct mlx4_init_port_param { 341 int set_guid0; 342 int set_node_guid; 343 int set_si_guid; 344 u16 mtu; 345 int port_width_cap; 346 u16 vl_cap; 347 u16 max_gid; 348 u16 max_pkey; 349 u64 guid0; 350 u64 node_guid; 351 u64 si_guid; 352 }; 353 354 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 355 struct mlx4_buf *buf); 356 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 357 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 358 { 359 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 360 return buf->direct.buf + offset; 361 else 362 return buf->page_list[offset >> PAGE_SHIFT].buf + 363 (offset & (PAGE_SIZE - 1)); 364 } 365 366 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 367 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 368 369 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 370 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 371 372 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 373 struct mlx4_mtt *mtt); 374 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 375 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 376 377 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 378 int npages, int page_shift, struct mlx4_mr *mr); 379 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 380 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 381 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 382 int start_index, int npages, u64 *page_list); 383 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 384 struct mlx4_buf *buf); 385 386 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 387 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 388 389 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 390 int size, int max_direct); 391 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 392 int size); 393 394 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 395 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 396 int collapsed); 397 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 398 399 int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp); 400 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 401 402 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, 403 u64 db_rec, struct mlx4_srq *srq); 404 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 405 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 406 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 407 408 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 409 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 410 411 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 412 int block_mcast_loopback); 413 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); 414 415 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 416 int npages, u64 iova, u32 *lkey, u32 *rkey); 417 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 418 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 419 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 420 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 421 u32 *lkey, u32 *rkey); 422 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 423 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 424 425 #endif /* MLX4_DEVICE_H */ 426