1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/pci.h> 37 #include <linux/completion.h> 38 #include <linux/radix-tree.h> 39 #include <linux/cpu_rmap.h> 40 41 #include <linux/atomic.h> 42 43 #define MAX_MSIX_P_PORT 17 44 #define MAX_MSIX 64 45 #define MSIX_LEGACY_SZ 4 46 #define MIN_MSIX_P_PORT 5 47 48 enum { 49 MLX4_FLAG_MSI_X = 1 << 0, 50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 51 MLX4_FLAG_MASTER = 1 << 2, 52 MLX4_FLAG_SLAVE = 1 << 3, 53 MLX4_FLAG_SRIOV = 1 << 4, 54 }; 55 56 enum { 57 MLX4_MAX_PORTS = 2 58 }; 59 60 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 61 * These qkeys must not be allowed for general use. This is a 64k range, 62 * and to test for violation, we use the mask (protect against future chg). 63 */ 64 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 65 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 66 67 enum { 68 MLX4_BOARD_ID_LEN = 64 69 }; 70 71 enum { 72 MLX4_MAX_NUM_PF = 16, 73 MLX4_MAX_NUM_VF = 64, 74 MLX4_MFUNC_MAX = 80, 75 MLX4_MAX_EQ_NUM = 1024, 76 MLX4_MFUNC_EQ_NUM = 4, 77 MLX4_MFUNC_MAX_EQES = 8, 78 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 79 }; 80 81 /* Driver supports 3 diffrent device methods to manage traffic steering: 82 * -device managed - High level API for ib and eth flow steering. FW is 83 * managing flow steering tables. 84 * - B0 steering mode - Common low level API for ib and (if supported) eth. 85 * - A0 steering mode - Limited low level API for eth. In case of IB, 86 * B0 mode is in use. 87 */ 88 enum { 89 MLX4_STEERING_MODE_A0, 90 MLX4_STEERING_MODE_B0, 91 MLX4_STEERING_MODE_DEVICE_MANAGED 92 }; 93 94 static inline const char *mlx4_steering_mode_str(int steering_mode) 95 { 96 switch (steering_mode) { 97 case MLX4_STEERING_MODE_A0: 98 return "A0 steering"; 99 100 case MLX4_STEERING_MODE_B0: 101 return "B0 steering"; 102 103 case MLX4_STEERING_MODE_DEVICE_MANAGED: 104 return "Device managed flow steering"; 105 106 default: 107 return "Unrecognize steering mode"; 108 } 109 } 110 111 enum { 112 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 113 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 114 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 115 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 116 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 117 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 118 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 119 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 120 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 121 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 122 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 123 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 124 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 125 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 126 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 127 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 128 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 129 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 130 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 131 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 132 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 133 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 134 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 135 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 136 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 137 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 138 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 139 }; 140 141 enum { 142 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 143 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 144 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 145 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3 146 }; 147 148 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 149 150 enum { 151 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 152 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 153 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 154 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 155 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 156 }; 157 158 enum mlx4_event { 159 MLX4_EVENT_TYPE_COMP = 0x00, 160 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 161 MLX4_EVENT_TYPE_COMM_EST = 0x02, 162 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 163 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 164 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 165 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 166 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 167 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 168 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 169 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 170 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 171 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 172 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 173 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 174 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 175 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 176 MLX4_EVENT_TYPE_CMD = 0x0a, 177 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 178 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 179 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 180 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 181 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 182 MLX4_EVENT_TYPE_NONE = 0xff, 183 }; 184 185 enum { 186 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 187 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 188 }; 189 190 enum { 191 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 192 }; 193 194 enum { 195 MLX4_PERM_LOCAL_READ = 1 << 10, 196 MLX4_PERM_LOCAL_WRITE = 1 << 11, 197 MLX4_PERM_REMOTE_READ = 1 << 12, 198 MLX4_PERM_REMOTE_WRITE = 1 << 13, 199 MLX4_PERM_ATOMIC = 1 << 14 200 }; 201 202 enum { 203 MLX4_OPCODE_NOP = 0x00, 204 MLX4_OPCODE_SEND_INVAL = 0x01, 205 MLX4_OPCODE_RDMA_WRITE = 0x08, 206 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 207 MLX4_OPCODE_SEND = 0x0a, 208 MLX4_OPCODE_SEND_IMM = 0x0b, 209 MLX4_OPCODE_LSO = 0x0e, 210 MLX4_OPCODE_RDMA_READ = 0x10, 211 MLX4_OPCODE_ATOMIC_CS = 0x11, 212 MLX4_OPCODE_ATOMIC_FA = 0x12, 213 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 214 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 215 MLX4_OPCODE_BIND_MW = 0x18, 216 MLX4_OPCODE_FMR = 0x19, 217 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 218 MLX4_OPCODE_CONFIG_CMD = 0x1f, 219 220 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 221 MLX4_RECV_OPCODE_SEND = 0x01, 222 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 223 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 224 225 MLX4_CQE_OPCODE_ERROR = 0x1e, 226 MLX4_CQE_OPCODE_RESIZE = 0x16, 227 }; 228 229 enum { 230 MLX4_STAT_RATE_OFFSET = 5 231 }; 232 233 enum mlx4_protocol { 234 MLX4_PROT_IB_IPV6 = 0, 235 MLX4_PROT_ETH, 236 MLX4_PROT_IB_IPV4, 237 MLX4_PROT_FCOE 238 }; 239 240 enum { 241 MLX4_MTT_FLAG_PRESENT = 1 242 }; 243 244 enum mlx4_qp_region { 245 MLX4_QP_REGION_FW = 0, 246 MLX4_QP_REGION_ETH_ADDR, 247 MLX4_QP_REGION_FC_ADDR, 248 MLX4_QP_REGION_FC_EXCH, 249 MLX4_NUM_QP_REGION 250 }; 251 252 enum mlx4_port_type { 253 MLX4_PORT_TYPE_NONE = 0, 254 MLX4_PORT_TYPE_IB = 1, 255 MLX4_PORT_TYPE_ETH = 2, 256 MLX4_PORT_TYPE_AUTO = 3 257 }; 258 259 enum mlx4_special_vlan_idx { 260 MLX4_NO_VLAN_IDX = 0, 261 MLX4_VLAN_MISS_IDX, 262 MLX4_VLAN_REGULAR 263 }; 264 265 enum mlx4_steer_type { 266 MLX4_MC_STEER = 0, 267 MLX4_UC_STEER, 268 MLX4_NUM_STEERS 269 }; 270 271 enum { 272 MLX4_NUM_FEXCH = 64 * 1024, 273 }; 274 275 enum { 276 MLX4_MAX_FAST_REG_PAGES = 511, 277 }; 278 279 enum { 280 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 281 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 282 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 283 }; 284 285 /* Port mgmt change event handling */ 286 enum { 287 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 288 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 289 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 290 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 291 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 292 }; 293 294 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 295 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 296 297 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 298 { 299 return (major << 32) | (minor << 16) | subminor; 300 } 301 302 struct mlx4_phys_caps { 303 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 304 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 305 u32 num_phys_eqs; 306 }; 307 308 struct mlx4_caps { 309 u64 fw_ver; 310 u32 function; 311 int num_ports; 312 int vl_cap[MLX4_MAX_PORTS + 1]; 313 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 314 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 315 u64 def_mac[MLX4_MAX_PORTS + 1]; 316 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 317 int gid_table_len[MLX4_MAX_PORTS + 1]; 318 int pkey_table_len[MLX4_MAX_PORTS + 1]; 319 int trans_type[MLX4_MAX_PORTS + 1]; 320 int vendor_oui[MLX4_MAX_PORTS + 1]; 321 int wavelength[MLX4_MAX_PORTS + 1]; 322 u64 trans_code[MLX4_MAX_PORTS + 1]; 323 int local_ca_ack_delay; 324 int num_uars; 325 u32 uar_page_size; 326 int bf_reg_size; 327 int bf_regs_per_page; 328 int max_sq_sg; 329 int max_rq_sg; 330 int num_qps; 331 int max_wqes; 332 int max_sq_desc_sz; 333 int max_rq_desc_sz; 334 int max_qp_init_rdma; 335 int max_qp_dest_rdma; 336 int sqp_start; 337 u32 base_sqpn; 338 u32 base_tunnel_sqpn; 339 int num_srqs; 340 int max_srq_wqes; 341 int max_srq_sge; 342 int reserved_srqs; 343 int num_cqs; 344 int max_cqes; 345 int reserved_cqs; 346 int num_eqs; 347 int reserved_eqs; 348 int num_comp_vectors; 349 int comp_pool; 350 int num_mpts; 351 int max_fmr_maps; 352 int num_mtts; 353 int fmr_reserved_mtts; 354 int reserved_mtts; 355 int reserved_mrws; 356 int reserved_uars; 357 int num_mgms; 358 int num_amgms; 359 int reserved_mcgs; 360 int num_qp_per_mgm; 361 int steering_mode; 362 int fs_log_max_ucast_qp_range_size; 363 int num_pds; 364 int reserved_pds; 365 int max_xrcds; 366 int reserved_xrcds; 367 int mtt_entry_sz; 368 u32 max_msg_sz; 369 u32 page_size_cap; 370 u64 flags; 371 u64 flags2; 372 u32 bmme_flags; 373 u32 reserved_lkey; 374 u16 stat_rate_support; 375 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 376 int max_gso_sz; 377 int max_rss_tbl_sz; 378 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 379 int reserved_qps; 380 int reserved_qps_base[MLX4_NUM_QP_REGION]; 381 int log_num_macs; 382 int log_num_vlans; 383 int log_num_prios; 384 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 385 u8 supported_type[MLX4_MAX_PORTS + 1]; 386 u8 suggested_type[MLX4_MAX_PORTS + 1]; 387 u8 default_sense[MLX4_MAX_PORTS + 1]; 388 u32 port_mask[MLX4_MAX_PORTS + 1]; 389 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 390 u32 max_counters; 391 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 392 }; 393 394 struct mlx4_buf_list { 395 void *buf; 396 dma_addr_t map; 397 }; 398 399 struct mlx4_buf { 400 struct mlx4_buf_list direct; 401 struct mlx4_buf_list *page_list; 402 int nbufs; 403 int npages; 404 int page_shift; 405 }; 406 407 struct mlx4_mtt { 408 u32 offset; 409 int order; 410 int page_shift; 411 }; 412 413 enum { 414 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 415 }; 416 417 struct mlx4_db_pgdir { 418 struct list_head list; 419 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 420 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 421 unsigned long *bits[2]; 422 __be32 *db_page; 423 dma_addr_t db_dma; 424 }; 425 426 struct mlx4_ib_user_db_page; 427 428 struct mlx4_db { 429 __be32 *db; 430 union { 431 struct mlx4_db_pgdir *pgdir; 432 struct mlx4_ib_user_db_page *user_page; 433 } u; 434 dma_addr_t dma; 435 int index; 436 int order; 437 }; 438 439 struct mlx4_hwq_resources { 440 struct mlx4_db db; 441 struct mlx4_mtt mtt; 442 struct mlx4_buf buf; 443 }; 444 445 struct mlx4_mr { 446 struct mlx4_mtt mtt; 447 u64 iova; 448 u64 size; 449 u32 key; 450 u32 pd; 451 u32 access; 452 int enabled; 453 }; 454 455 struct mlx4_fmr { 456 struct mlx4_mr mr; 457 struct mlx4_mpt_entry *mpt; 458 __be64 *mtts; 459 dma_addr_t dma_handle; 460 int max_pages; 461 int max_maps; 462 int maps; 463 u8 page_shift; 464 }; 465 466 struct mlx4_uar { 467 unsigned long pfn; 468 int index; 469 struct list_head bf_list; 470 unsigned free_bf_bmap; 471 void __iomem *map; 472 void __iomem *bf_map; 473 }; 474 475 struct mlx4_bf { 476 unsigned long offset; 477 int buf_size; 478 struct mlx4_uar *uar; 479 void __iomem *reg; 480 }; 481 482 struct mlx4_cq { 483 void (*comp) (struct mlx4_cq *); 484 void (*event) (struct mlx4_cq *, enum mlx4_event); 485 486 struct mlx4_uar *uar; 487 488 u32 cons_index; 489 490 __be32 *set_ci_db; 491 __be32 *arm_db; 492 int arm_sn; 493 494 int cqn; 495 unsigned vector; 496 497 atomic_t refcount; 498 struct completion free; 499 }; 500 501 struct mlx4_qp { 502 void (*event) (struct mlx4_qp *, enum mlx4_event); 503 504 int qpn; 505 506 atomic_t refcount; 507 struct completion free; 508 }; 509 510 struct mlx4_srq { 511 void (*event) (struct mlx4_srq *, enum mlx4_event); 512 513 int srqn; 514 int max; 515 int max_gs; 516 int wqe_shift; 517 518 atomic_t refcount; 519 struct completion free; 520 }; 521 522 struct mlx4_av { 523 __be32 port_pd; 524 u8 reserved1; 525 u8 g_slid; 526 __be16 dlid; 527 u8 reserved2; 528 u8 gid_index; 529 u8 stat_rate; 530 u8 hop_limit; 531 __be32 sl_tclass_flowlabel; 532 u8 dgid[16]; 533 }; 534 535 struct mlx4_eth_av { 536 __be32 port_pd; 537 u8 reserved1; 538 u8 smac_idx; 539 u16 reserved2; 540 u8 reserved3; 541 u8 gid_index; 542 u8 stat_rate; 543 u8 hop_limit; 544 __be32 sl_tclass_flowlabel; 545 u8 dgid[16]; 546 u32 reserved4[2]; 547 __be16 vlan; 548 u8 mac[6]; 549 }; 550 551 union mlx4_ext_av { 552 struct mlx4_av ib; 553 struct mlx4_eth_av eth; 554 }; 555 556 struct mlx4_counter { 557 u8 reserved1[3]; 558 u8 counter_mode; 559 __be32 num_ifc; 560 u32 reserved2[2]; 561 __be64 rx_frames; 562 __be64 rx_bytes; 563 __be64 tx_frames; 564 __be64 tx_bytes; 565 }; 566 567 struct mlx4_dev { 568 struct pci_dev *pdev; 569 unsigned long flags; 570 unsigned long num_slaves; 571 struct mlx4_caps caps; 572 struct mlx4_phys_caps phys_caps; 573 struct radix_tree_root qp_table_tree; 574 u8 rev_id; 575 char board_id[MLX4_BOARD_ID_LEN]; 576 int num_vfs; 577 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 578 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 579 }; 580 581 struct mlx4_eqe { 582 u8 reserved1; 583 u8 type; 584 u8 reserved2; 585 u8 subtype; 586 union { 587 u32 raw[6]; 588 struct { 589 __be32 cqn; 590 } __packed comp; 591 struct { 592 u16 reserved1; 593 __be16 token; 594 u32 reserved2; 595 u8 reserved3[3]; 596 u8 status; 597 __be64 out_param; 598 } __packed cmd; 599 struct { 600 __be32 qpn; 601 } __packed qp; 602 struct { 603 __be32 srqn; 604 } __packed srq; 605 struct { 606 __be32 cqn; 607 u32 reserved1; 608 u8 reserved2[3]; 609 u8 syndrome; 610 } __packed cq_err; 611 struct { 612 u32 reserved1[2]; 613 __be32 port; 614 } __packed port_change; 615 struct { 616 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 617 u32 reserved; 618 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 619 } __packed comm_channel_arm; 620 struct { 621 u8 port; 622 u8 reserved[3]; 623 __be64 mac; 624 } __packed mac_update; 625 struct { 626 __be32 slave_id; 627 } __packed flr_event; 628 struct { 629 __be16 current_temperature; 630 __be16 warning_threshold; 631 } __packed warming; 632 struct { 633 u8 reserved[3]; 634 u8 port; 635 union { 636 struct { 637 __be16 mstr_sm_lid; 638 __be16 port_lid; 639 __be32 changed_attr; 640 u8 reserved[3]; 641 u8 mstr_sm_sl; 642 __be64 gid_prefix; 643 } __packed port_info; 644 struct { 645 __be32 block_ptr; 646 __be32 tbl_entries_mask; 647 } __packed tbl_change_info; 648 } params; 649 } __packed port_mgmt_change; 650 } event; 651 u8 slave_id; 652 u8 reserved3[2]; 653 u8 owner; 654 } __packed; 655 656 struct mlx4_init_port_param { 657 int set_guid0; 658 int set_node_guid; 659 int set_si_guid; 660 u16 mtu; 661 int port_width_cap; 662 u16 vl_cap; 663 u16 max_gid; 664 u16 max_pkey; 665 u64 guid0; 666 u64 node_guid; 667 u64 si_guid; 668 }; 669 670 #define mlx4_foreach_port(port, dev, type) \ 671 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 672 if ((type) == (dev)->caps.port_mask[(port)]) 673 674 #define mlx4_foreach_ib_transport_port(port, dev) \ 675 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 676 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 677 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 678 679 #define MLX4_INVALID_SLAVE_ID 0xFF 680 681 void handle_port_mgmt_change_event(struct work_struct *work); 682 683 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 684 { 685 return dev->caps.function; 686 } 687 688 static inline int mlx4_is_master(struct mlx4_dev *dev) 689 { 690 return dev->flags & MLX4_FLAG_MASTER; 691 } 692 693 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 694 { 695 return (qpn < dev->caps.sqp_start + 8); 696 } 697 698 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 699 { 700 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 701 } 702 703 static inline int mlx4_is_slave(struct mlx4_dev *dev) 704 { 705 return dev->flags & MLX4_FLAG_SLAVE; 706 } 707 708 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 709 struct mlx4_buf *buf); 710 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 711 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 712 { 713 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 714 return buf->direct.buf + offset; 715 else 716 return buf->page_list[offset >> PAGE_SHIFT].buf + 717 (offset & (PAGE_SIZE - 1)); 718 } 719 720 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 721 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 722 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 723 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 724 725 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 726 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 727 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 728 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 729 730 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 731 struct mlx4_mtt *mtt); 732 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 733 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 734 735 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 736 int npages, int page_shift, struct mlx4_mr *mr); 737 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 738 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 739 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 740 int start_index, int npages, u64 *page_list); 741 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 742 struct mlx4_buf *buf); 743 744 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 745 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 746 747 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 748 int size, int max_direct); 749 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 750 int size); 751 752 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 753 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 754 unsigned vector, int collapsed); 755 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 756 757 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 758 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 759 760 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 761 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 762 763 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 764 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 765 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 766 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 767 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 768 769 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 770 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 771 772 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 773 int block_mcast_loopback, enum mlx4_protocol prot); 774 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 775 enum mlx4_protocol prot); 776 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 777 u8 port, int block_mcast_loopback, 778 enum mlx4_protocol protocol, u64 *reg_id); 779 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 780 enum mlx4_protocol protocol, u64 reg_id); 781 782 enum { 783 MLX4_DOMAIN_UVERBS = 0x1000, 784 MLX4_DOMAIN_ETHTOOL = 0x2000, 785 MLX4_DOMAIN_RFS = 0x3000, 786 MLX4_DOMAIN_NIC = 0x5000, 787 }; 788 789 enum mlx4_net_trans_rule_id { 790 MLX4_NET_TRANS_RULE_ID_ETH = 0, 791 MLX4_NET_TRANS_RULE_ID_IB, 792 MLX4_NET_TRANS_RULE_ID_IPV6, 793 MLX4_NET_TRANS_RULE_ID_IPV4, 794 MLX4_NET_TRANS_RULE_ID_TCP, 795 MLX4_NET_TRANS_RULE_ID_UDP, 796 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 797 }; 798 799 enum mlx4_net_trans_promisc_mode { 800 MLX4_FS_PROMISC_NONE = 0, 801 MLX4_FS_PROMISC_UPLINK, 802 /* For future use. Not implemented yet */ 803 MLX4_FS_PROMISC_FUNCTION_PORT, 804 MLX4_FS_PROMISC_ALL_MULTI, 805 }; 806 807 struct mlx4_spec_eth { 808 u8 dst_mac[6]; 809 u8 dst_mac_msk[6]; 810 u8 src_mac[6]; 811 u8 src_mac_msk[6]; 812 u8 ether_type_enable; 813 __be16 ether_type; 814 __be16 vlan_id_msk; 815 __be16 vlan_id; 816 }; 817 818 struct mlx4_spec_tcp_udp { 819 __be16 dst_port; 820 __be16 dst_port_msk; 821 __be16 src_port; 822 __be16 src_port_msk; 823 }; 824 825 struct mlx4_spec_ipv4 { 826 __be32 dst_ip; 827 __be32 dst_ip_msk; 828 __be32 src_ip; 829 __be32 src_ip_msk; 830 }; 831 832 struct mlx4_spec_ib { 833 __be32 r_qpn; 834 __be32 qpn_msk; 835 u8 dst_gid[16]; 836 u8 dst_gid_msk[16]; 837 }; 838 839 struct mlx4_spec_list { 840 struct list_head list; 841 enum mlx4_net_trans_rule_id id; 842 union { 843 struct mlx4_spec_eth eth; 844 struct mlx4_spec_ib ib; 845 struct mlx4_spec_ipv4 ipv4; 846 struct mlx4_spec_tcp_udp tcp_udp; 847 }; 848 }; 849 850 enum mlx4_net_trans_hw_rule_queue { 851 MLX4_NET_TRANS_Q_FIFO, 852 MLX4_NET_TRANS_Q_LIFO, 853 }; 854 855 struct mlx4_net_trans_rule { 856 struct list_head list; 857 enum mlx4_net_trans_hw_rule_queue queue_mode; 858 bool exclusive; 859 bool allow_loopback; 860 enum mlx4_net_trans_promisc_mode promisc_mode; 861 u8 port; 862 u16 priority; 863 u32 qpn; 864 }; 865 866 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 867 enum mlx4_net_trans_promisc_mode mode); 868 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 869 enum mlx4_net_trans_promisc_mode mode); 870 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 871 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 872 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 873 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 874 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 875 876 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 877 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 878 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 879 int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn); 880 void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn); 881 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); 882 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 883 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 884 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 885 u8 promisc); 886 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 887 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 888 u8 *pg, u16 *ratelimit); 889 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 890 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 891 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 892 893 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 894 int npages, u64 iova, u32 *lkey, u32 *rkey); 895 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 896 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 897 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 898 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 899 u32 *lkey, u32 *rkey); 900 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 901 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 902 int mlx4_test_interrupts(struct mlx4_dev *dev); 903 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 904 int *vector); 905 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 906 907 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 908 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 909 910 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 911 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 912 913 int mlx4_flow_attach(struct mlx4_dev *dev, 914 struct mlx4_net_trans_rule *rule, u64 *reg_id); 915 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 916 917 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 918 919 #endif /* MLX4_DEVICE_H */ 920