1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define MAX_MSIX_P_PORT 17 48 #define MAX_MSIX 64 49 #define MIN_MSIX_P_PORT 5 50 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 51 (dev_cap).num_ports * MIN_MSIX_P_PORT) 52 53 #define MLX4_MAX_100M_UNITS_VAL 255 /* 54 * work around: can't set values 55 * greater then this value when 56 * using 100 Mbps units. 57 */ 58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 60 #define MLX4_RATELIMIT_DEFAULT 0x00ff 61 62 #define MLX4_ROCE_MAX_GIDS 128 63 #define MLX4_ROCE_PF_GIDS 16 64 65 enum { 66 MLX4_FLAG_MSI_X = 1 << 0, 67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 68 MLX4_FLAG_MASTER = 1 << 2, 69 MLX4_FLAG_SLAVE = 1 << 3, 70 MLX4_FLAG_SRIOV = 1 << 4, 71 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 72 MLX4_FLAG_BONDED = 1 << 7 73 }; 74 75 enum { 76 MLX4_PORT_CAP_IS_SM = 1 << 1, 77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 78 }; 79 80 enum { 81 MLX4_MAX_PORTS = 2, 82 MLX4_MAX_PORT_PKEYS = 128, 83 MLX4_MAX_PORT_GIDS = 128 84 }; 85 86 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 87 * These qkeys must not be allowed for general use. This is a 64k range, 88 * and to test for violation, we use the mask (protect against future chg). 89 */ 90 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 91 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 92 93 enum { 94 MLX4_BOARD_ID_LEN = 64 95 }; 96 97 enum { 98 MLX4_MAX_NUM_PF = 16, 99 MLX4_MAX_NUM_VF = 126, 100 MLX4_MAX_NUM_VF_P_PORT = 64, 101 MLX4_MFUNC_MAX = 128, 102 MLX4_MAX_EQ_NUM = 1024, 103 MLX4_MFUNC_EQ_NUM = 4, 104 MLX4_MFUNC_MAX_EQES = 8, 105 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 106 }; 107 108 /* Driver supports 3 diffrent device methods to manage traffic steering: 109 * -device managed - High level API for ib and eth flow steering. FW is 110 * managing flow steering tables. 111 * - B0 steering mode - Common low level API for ib and (if supported) eth. 112 * - A0 steering mode - Limited low level API for eth. In case of IB, 113 * B0 mode is in use. 114 */ 115 enum { 116 MLX4_STEERING_MODE_A0, 117 MLX4_STEERING_MODE_B0, 118 MLX4_STEERING_MODE_DEVICE_MANAGED 119 }; 120 121 enum { 122 MLX4_STEERING_DMFS_A0_DEFAULT, 123 MLX4_STEERING_DMFS_A0_DYNAMIC, 124 MLX4_STEERING_DMFS_A0_STATIC, 125 MLX4_STEERING_DMFS_A0_DISABLE, 126 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 127 }; 128 129 static inline const char *mlx4_steering_mode_str(int steering_mode) 130 { 131 switch (steering_mode) { 132 case MLX4_STEERING_MODE_A0: 133 return "A0 steering"; 134 135 case MLX4_STEERING_MODE_B0: 136 return "B0 steering"; 137 138 case MLX4_STEERING_MODE_DEVICE_MANAGED: 139 return "Device managed flow steering"; 140 141 default: 142 return "Unrecognize steering mode"; 143 } 144 } 145 146 enum { 147 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 148 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 149 }; 150 151 enum { 152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 176 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 177 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 178 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 179 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 180 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 181 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 182 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 183 }; 184 185 enum { 186 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 187 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 188 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 189 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 190 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 191 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 192 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 193 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 194 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 195 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 196 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 197 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 200 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 201 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 202 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 203 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 204 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 205 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 206 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 207 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 208 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 209 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 210 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 211 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 212 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 213 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 214 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 215 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 216 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 217 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 218 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 219 }; 220 221 enum { 222 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 223 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 224 }; 225 226 enum { 227 MLX4_VF_CAP_FLAG_RESET = 1 << 0 228 }; 229 230 /* bit enums for an 8-bit flags field indicating special use 231 * QPs which require special handling in qp_reserve_range. 232 * Currently, this only includes QPs used by the ETH interface, 233 * where we expect to use blueflame. These QPs must not have 234 * bits 6 and 7 set in their qp number. 235 * 236 * This enum may use only bits 0..7. 237 */ 238 enum { 239 MLX4_RESERVE_A0_QP = 1 << 6, 240 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 241 }; 242 243 enum { 244 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 245 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 246 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 247 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 248 }; 249 250 enum { 251 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 252 }; 253 254 enum { 255 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 256 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 257 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 258 }; 259 260 261 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 262 263 enum { 264 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 265 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 266 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 267 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 268 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 269 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 270 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 271 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 272 }; 273 274 enum { 275 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP 276 }; 277 278 enum mlx4_event { 279 MLX4_EVENT_TYPE_COMP = 0x00, 280 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 281 MLX4_EVENT_TYPE_COMM_EST = 0x02, 282 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 283 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 284 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 285 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 286 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 287 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 288 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 289 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 290 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 291 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 292 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 293 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 294 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 295 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 296 MLX4_EVENT_TYPE_CMD = 0x0a, 297 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 298 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 299 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 300 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 301 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 302 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 303 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 304 MLX4_EVENT_TYPE_NONE = 0xff, 305 }; 306 307 enum { 308 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 309 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 310 }; 311 312 enum { 313 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 314 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 315 }; 316 317 enum { 318 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 319 }; 320 321 enum slave_port_state { 322 SLAVE_PORT_DOWN = 0, 323 SLAVE_PENDING_UP, 324 SLAVE_PORT_UP, 325 }; 326 327 enum slave_port_gen_event { 328 SLAVE_PORT_GEN_EVENT_DOWN = 0, 329 SLAVE_PORT_GEN_EVENT_UP, 330 SLAVE_PORT_GEN_EVENT_NONE, 331 }; 332 333 enum slave_port_state_event { 334 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 335 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 336 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 337 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 338 }; 339 340 enum { 341 MLX4_PERM_LOCAL_READ = 1 << 10, 342 MLX4_PERM_LOCAL_WRITE = 1 << 11, 343 MLX4_PERM_REMOTE_READ = 1 << 12, 344 MLX4_PERM_REMOTE_WRITE = 1 << 13, 345 MLX4_PERM_ATOMIC = 1 << 14, 346 MLX4_PERM_BIND_MW = 1 << 15, 347 MLX4_PERM_MASK = 0xFC00 348 }; 349 350 enum { 351 MLX4_OPCODE_NOP = 0x00, 352 MLX4_OPCODE_SEND_INVAL = 0x01, 353 MLX4_OPCODE_RDMA_WRITE = 0x08, 354 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 355 MLX4_OPCODE_SEND = 0x0a, 356 MLX4_OPCODE_SEND_IMM = 0x0b, 357 MLX4_OPCODE_LSO = 0x0e, 358 MLX4_OPCODE_RDMA_READ = 0x10, 359 MLX4_OPCODE_ATOMIC_CS = 0x11, 360 MLX4_OPCODE_ATOMIC_FA = 0x12, 361 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 362 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 363 MLX4_OPCODE_BIND_MW = 0x18, 364 MLX4_OPCODE_FMR = 0x19, 365 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 366 MLX4_OPCODE_CONFIG_CMD = 0x1f, 367 368 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 369 MLX4_RECV_OPCODE_SEND = 0x01, 370 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 371 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 372 373 MLX4_CQE_OPCODE_ERROR = 0x1e, 374 MLX4_CQE_OPCODE_RESIZE = 0x16, 375 }; 376 377 enum { 378 MLX4_STAT_RATE_OFFSET = 5 379 }; 380 381 enum mlx4_protocol { 382 MLX4_PROT_IB_IPV6 = 0, 383 MLX4_PROT_ETH, 384 MLX4_PROT_IB_IPV4, 385 MLX4_PROT_FCOE 386 }; 387 388 enum { 389 MLX4_MTT_FLAG_PRESENT = 1 390 }; 391 392 enum mlx4_qp_region { 393 MLX4_QP_REGION_FW = 0, 394 MLX4_QP_REGION_RSS_RAW_ETH, 395 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 396 MLX4_QP_REGION_ETH_ADDR, 397 MLX4_QP_REGION_FC_ADDR, 398 MLX4_QP_REGION_FC_EXCH, 399 MLX4_NUM_QP_REGION 400 }; 401 402 enum mlx4_port_type { 403 MLX4_PORT_TYPE_NONE = 0, 404 MLX4_PORT_TYPE_IB = 1, 405 MLX4_PORT_TYPE_ETH = 2, 406 MLX4_PORT_TYPE_AUTO = 3 407 }; 408 409 enum mlx4_special_vlan_idx { 410 MLX4_NO_VLAN_IDX = 0, 411 MLX4_VLAN_MISS_IDX, 412 MLX4_VLAN_REGULAR 413 }; 414 415 enum mlx4_steer_type { 416 MLX4_MC_STEER = 0, 417 MLX4_UC_STEER, 418 MLX4_NUM_STEERS 419 }; 420 421 enum { 422 MLX4_NUM_FEXCH = 64 * 1024, 423 }; 424 425 enum { 426 MLX4_MAX_FAST_REG_PAGES = 511, 427 }; 428 429 enum { 430 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 431 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 432 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 433 }; 434 435 /* Port mgmt change event handling */ 436 enum { 437 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 438 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 439 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 440 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 441 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 442 }; 443 444 enum { 445 MLX4_DEVICE_STATE_UP = 1 << 0, 446 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 447 }; 448 449 enum { 450 MLX4_INTERFACE_STATE_UP = 1 << 0, 451 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 452 }; 453 454 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 455 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 456 457 enum mlx4_module_id { 458 MLX4_MODULE_ID_SFP = 0x3, 459 MLX4_MODULE_ID_QSFP = 0xC, 460 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 461 MLX4_MODULE_ID_QSFP28 = 0x11, 462 }; 463 464 enum { /* rl */ 465 MLX4_QP_RATE_LIMIT_NONE = 0, 466 MLX4_QP_RATE_LIMIT_KBS = 1, 467 MLX4_QP_RATE_LIMIT_MBS = 2, 468 MLX4_QP_RATE_LIMIT_GBS = 3 469 }; 470 471 struct mlx4_rate_limit_caps { 472 u16 num_rates; /* Number of different rates */ 473 u8 min_unit; 474 u16 min_val; 475 u8 max_unit; 476 u16 max_val; 477 }; 478 479 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 480 { 481 return (major << 32) | (minor << 16) | subminor; 482 } 483 484 struct mlx4_phys_caps { 485 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 486 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 487 u32 num_phys_eqs; 488 u32 base_sqpn; 489 u32 base_proxy_sqpn; 490 u32 base_tunnel_sqpn; 491 }; 492 493 struct mlx4_caps { 494 u64 fw_ver; 495 u32 function; 496 int num_ports; 497 int vl_cap[MLX4_MAX_PORTS + 1]; 498 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 499 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 500 u64 def_mac[MLX4_MAX_PORTS + 1]; 501 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 502 int gid_table_len[MLX4_MAX_PORTS + 1]; 503 int pkey_table_len[MLX4_MAX_PORTS + 1]; 504 int trans_type[MLX4_MAX_PORTS + 1]; 505 int vendor_oui[MLX4_MAX_PORTS + 1]; 506 int wavelength[MLX4_MAX_PORTS + 1]; 507 u64 trans_code[MLX4_MAX_PORTS + 1]; 508 int local_ca_ack_delay; 509 int num_uars; 510 u32 uar_page_size; 511 int bf_reg_size; 512 int bf_regs_per_page; 513 int max_sq_sg; 514 int max_rq_sg; 515 int num_qps; 516 int max_wqes; 517 int max_sq_desc_sz; 518 int max_rq_desc_sz; 519 int max_qp_init_rdma; 520 int max_qp_dest_rdma; 521 u32 *qp0_qkey; 522 u32 *qp0_proxy; 523 u32 *qp1_proxy; 524 u32 *qp0_tunnel; 525 u32 *qp1_tunnel; 526 int num_srqs; 527 int max_srq_wqes; 528 int max_srq_sge; 529 int reserved_srqs; 530 int num_cqs; 531 int max_cqes; 532 int reserved_cqs; 533 int num_sys_eqs; 534 int num_eqs; 535 int reserved_eqs; 536 int num_comp_vectors; 537 int num_mpts; 538 int max_fmr_maps; 539 int num_mtts; 540 int fmr_reserved_mtts; 541 int reserved_mtts; 542 int reserved_mrws; 543 int reserved_uars; 544 int num_mgms; 545 int num_amgms; 546 int reserved_mcgs; 547 int num_qp_per_mgm; 548 int steering_mode; 549 int dmfs_high_steer_mode; 550 int fs_log_max_ucast_qp_range_size; 551 int num_pds; 552 int reserved_pds; 553 int max_xrcds; 554 int reserved_xrcds; 555 int mtt_entry_sz; 556 u32 max_msg_sz; 557 u32 page_size_cap; 558 u64 flags; 559 u64 flags2; 560 u32 bmme_flags; 561 u32 reserved_lkey; 562 u16 stat_rate_support; 563 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 564 int max_gso_sz; 565 int max_rss_tbl_sz; 566 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 567 int reserved_qps; 568 int reserved_qps_base[MLX4_NUM_QP_REGION]; 569 int log_num_macs; 570 int log_num_vlans; 571 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 572 u8 supported_type[MLX4_MAX_PORTS + 1]; 573 u8 suggested_type[MLX4_MAX_PORTS + 1]; 574 u8 default_sense[MLX4_MAX_PORTS + 1]; 575 u32 port_mask[MLX4_MAX_PORTS + 1]; 576 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 577 u32 max_counters; 578 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 579 u16 sqp_demux; 580 u32 eqe_size; 581 u32 cqe_size; 582 u8 eqe_factor; 583 u32 userspace_caps; /* userspace must be aware of these */ 584 u32 function_caps; /* VFs must be aware of these */ 585 u16 hca_core_clock; 586 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 587 int tunnel_offload_mode; 588 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 589 u8 phv_bit[MLX4_MAX_PORTS + 1]; 590 u8 alloc_res_qp_mask; 591 u32 dmfs_high_rate_qpn_base; 592 u32 dmfs_high_rate_qpn_range; 593 u32 vf_caps; 594 struct mlx4_rate_limit_caps rl_caps; 595 }; 596 597 struct mlx4_buf_list { 598 void *buf; 599 dma_addr_t map; 600 }; 601 602 struct mlx4_buf { 603 struct mlx4_buf_list direct; 604 struct mlx4_buf_list *page_list; 605 int nbufs; 606 int npages; 607 int page_shift; 608 }; 609 610 struct mlx4_mtt { 611 u32 offset; 612 int order; 613 int page_shift; 614 }; 615 616 enum { 617 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 618 }; 619 620 struct mlx4_db_pgdir { 621 struct list_head list; 622 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 623 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 624 unsigned long *bits[2]; 625 __be32 *db_page; 626 dma_addr_t db_dma; 627 }; 628 629 struct mlx4_ib_user_db_page; 630 631 struct mlx4_db { 632 __be32 *db; 633 union { 634 struct mlx4_db_pgdir *pgdir; 635 struct mlx4_ib_user_db_page *user_page; 636 } u; 637 dma_addr_t dma; 638 int index; 639 int order; 640 }; 641 642 struct mlx4_hwq_resources { 643 struct mlx4_db db; 644 struct mlx4_mtt mtt; 645 struct mlx4_buf buf; 646 }; 647 648 struct mlx4_mr { 649 struct mlx4_mtt mtt; 650 u64 iova; 651 u64 size; 652 u32 key; 653 u32 pd; 654 u32 access; 655 int enabled; 656 }; 657 658 enum mlx4_mw_type { 659 MLX4_MW_TYPE_1 = 1, 660 MLX4_MW_TYPE_2 = 2, 661 }; 662 663 struct mlx4_mw { 664 u32 key; 665 u32 pd; 666 enum mlx4_mw_type type; 667 int enabled; 668 }; 669 670 struct mlx4_fmr { 671 struct mlx4_mr mr; 672 struct mlx4_mpt_entry *mpt; 673 __be64 *mtts; 674 dma_addr_t dma_handle; 675 int max_pages; 676 int max_maps; 677 int maps; 678 u8 page_shift; 679 }; 680 681 struct mlx4_uar { 682 unsigned long pfn; 683 int index; 684 struct list_head bf_list; 685 unsigned free_bf_bmap; 686 void __iomem *map; 687 void __iomem *bf_map; 688 }; 689 690 struct mlx4_bf { 691 unsigned int offset; 692 int buf_size; 693 struct mlx4_uar *uar; 694 void __iomem *reg; 695 }; 696 697 struct mlx4_cq { 698 void (*comp) (struct mlx4_cq *); 699 void (*event) (struct mlx4_cq *, enum mlx4_event); 700 701 struct mlx4_uar *uar; 702 703 u32 cons_index; 704 705 u16 irq; 706 __be32 *set_ci_db; 707 __be32 *arm_db; 708 int arm_sn; 709 710 int cqn; 711 unsigned vector; 712 713 atomic_t refcount; 714 struct completion free; 715 struct { 716 struct list_head list; 717 void (*comp)(struct mlx4_cq *); 718 void *priv; 719 } tasklet_ctx; 720 int reset_notify_added; 721 struct list_head reset_notify; 722 }; 723 724 struct mlx4_qp { 725 void (*event) (struct mlx4_qp *, enum mlx4_event); 726 727 int qpn; 728 729 atomic_t refcount; 730 struct completion free; 731 }; 732 733 struct mlx4_srq { 734 void (*event) (struct mlx4_srq *, enum mlx4_event); 735 736 int srqn; 737 int max; 738 int max_gs; 739 int wqe_shift; 740 741 atomic_t refcount; 742 struct completion free; 743 }; 744 745 struct mlx4_av { 746 __be32 port_pd; 747 u8 reserved1; 748 u8 g_slid; 749 __be16 dlid; 750 u8 reserved2; 751 u8 gid_index; 752 u8 stat_rate; 753 u8 hop_limit; 754 __be32 sl_tclass_flowlabel; 755 u8 dgid[16]; 756 }; 757 758 struct mlx4_eth_av { 759 __be32 port_pd; 760 u8 reserved1; 761 u8 smac_idx; 762 u16 reserved2; 763 u8 reserved3; 764 u8 gid_index; 765 u8 stat_rate; 766 u8 hop_limit; 767 __be32 sl_tclass_flowlabel; 768 u8 dgid[16]; 769 u8 s_mac[6]; 770 u8 reserved4[2]; 771 __be16 vlan; 772 u8 mac[ETH_ALEN]; 773 }; 774 775 union mlx4_ext_av { 776 struct mlx4_av ib; 777 struct mlx4_eth_av eth; 778 }; 779 780 /* Counters should be saturate once they reach their maximum value */ 781 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 782 if ((value) > U32_MAX) \ 783 counter = cpu_to_be32(U32_MAX); \ 784 else \ 785 counter = cpu_to_be32(value); \ 786 } while (0) 787 788 struct mlx4_counter { 789 u8 reserved1[3]; 790 u8 counter_mode; 791 __be32 num_ifc; 792 u32 reserved2[2]; 793 __be64 rx_frames; 794 __be64 rx_bytes; 795 __be64 tx_frames; 796 __be64 tx_bytes; 797 }; 798 799 struct mlx4_quotas { 800 int qp; 801 int cq; 802 int srq; 803 int mpt; 804 int mtt; 805 int counter; 806 int xrcd; 807 }; 808 809 struct mlx4_vf_dev { 810 u8 min_port; 811 u8 n_ports; 812 }; 813 814 struct mlx4_dev_persistent { 815 struct pci_dev *pdev; 816 struct mlx4_dev *dev; 817 int nvfs[MLX4_MAX_PORTS + 1]; 818 int num_vfs; 819 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 820 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 821 struct work_struct catas_work; 822 struct workqueue_struct *catas_wq; 823 struct mutex device_state_mutex; /* protect HW state */ 824 u8 state; 825 struct mutex interface_state_mutex; /* protect SW state */ 826 u8 interface_state; 827 }; 828 829 struct mlx4_dev { 830 struct mlx4_dev_persistent *persist; 831 unsigned long flags; 832 unsigned long num_slaves; 833 struct mlx4_caps caps; 834 struct mlx4_phys_caps phys_caps; 835 struct mlx4_quotas quotas; 836 struct radix_tree_root qp_table_tree; 837 u8 rev_id; 838 u8 port_random_macs; 839 char board_id[MLX4_BOARD_ID_LEN]; 840 int numa_node; 841 int oper_log_mgm_entry_size; 842 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 843 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 844 struct mlx4_vf_dev *dev_vfs; 845 }; 846 847 struct mlx4_clock_params { 848 u64 offset; 849 u8 bar; 850 u8 size; 851 }; 852 853 struct mlx4_eqe { 854 u8 reserved1; 855 u8 type; 856 u8 reserved2; 857 u8 subtype; 858 union { 859 u32 raw[6]; 860 struct { 861 __be32 cqn; 862 } __packed comp; 863 struct { 864 u16 reserved1; 865 __be16 token; 866 u32 reserved2; 867 u8 reserved3[3]; 868 u8 status; 869 __be64 out_param; 870 } __packed cmd; 871 struct { 872 __be32 qpn; 873 } __packed qp; 874 struct { 875 __be32 srqn; 876 } __packed srq; 877 struct { 878 __be32 cqn; 879 u32 reserved1; 880 u8 reserved2[3]; 881 u8 syndrome; 882 } __packed cq_err; 883 struct { 884 u32 reserved1[2]; 885 __be32 port; 886 } __packed port_change; 887 struct { 888 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 889 u32 reserved; 890 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 891 } __packed comm_channel_arm; 892 struct { 893 u8 port; 894 u8 reserved[3]; 895 __be64 mac; 896 } __packed mac_update; 897 struct { 898 __be32 slave_id; 899 } __packed flr_event; 900 struct { 901 __be16 current_temperature; 902 __be16 warning_threshold; 903 } __packed warming; 904 struct { 905 u8 reserved[3]; 906 u8 port; 907 union { 908 struct { 909 __be16 mstr_sm_lid; 910 __be16 port_lid; 911 __be32 changed_attr; 912 u8 reserved[3]; 913 u8 mstr_sm_sl; 914 __be64 gid_prefix; 915 } __packed port_info; 916 struct { 917 __be32 block_ptr; 918 __be32 tbl_entries_mask; 919 } __packed tbl_change_info; 920 } params; 921 } __packed port_mgmt_change; 922 struct { 923 u8 reserved[3]; 924 u8 port; 925 u32 reserved1[5]; 926 } __packed bad_cable; 927 } event; 928 u8 slave_id; 929 u8 reserved3[2]; 930 u8 owner; 931 } __packed; 932 933 struct mlx4_init_port_param { 934 int set_guid0; 935 int set_node_guid; 936 int set_si_guid; 937 u16 mtu; 938 int port_width_cap; 939 u16 vl_cap; 940 u16 max_gid; 941 u16 max_pkey; 942 u64 guid0; 943 u64 node_guid; 944 u64 si_guid; 945 }; 946 947 #define MAD_IFC_DATA_SZ 192 948 /* MAD IFC Mailbox */ 949 struct mlx4_mad_ifc { 950 u8 base_version; 951 u8 mgmt_class; 952 u8 class_version; 953 u8 method; 954 __be16 status; 955 __be16 class_specific; 956 __be64 tid; 957 __be16 attr_id; 958 __be16 resv; 959 __be32 attr_mod; 960 __be64 mkey; 961 __be16 dr_slid; 962 __be16 dr_dlid; 963 u8 reserved[28]; 964 u8 data[MAD_IFC_DATA_SZ]; 965 } __packed; 966 967 #define mlx4_foreach_port(port, dev, type) \ 968 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 969 if ((type) == (dev)->caps.port_mask[(port)]) 970 971 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 972 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 973 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 974 975 #define mlx4_foreach_ib_transport_port(port, dev) \ 976 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 977 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 978 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 979 980 #define MLX4_INVALID_SLAVE_ID 0xFF 981 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 982 983 void handle_port_mgmt_change_event(struct work_struct *work); 984 985 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 986 { 987 return dev->caps.function; 988 } 989 990 static inline int mlx4_is_master(struct mlx4_dev *dev) 991 { 992 return dev->flags & MLX4_FLAG_MASTER; 993 } 994 995 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 996 { 997 return dev->phys_caps.base_sqpn + 8 + 998 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 999 } 1000 1001 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1002 { 1003 return (qpn < dev->phys_caps.base_sqpn + 8 + 1004 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1005 qpn >= dev->phys_caps.base_sqpn) || 1006 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1007 } 1008 1009 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1010 { 1011 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1012 1013 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1014 return 1; 1015 1016 return 0; 1017 } 1018 1019 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1020 { 1021 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1022 } 1023 1024 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1025 { 1026 return dev->flags & MLX4_FLAG_SLAVE; 1027 } 1028 1029 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1030 { 1031 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1032 } 1033 1034 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1035 struct mlx4_buf *buf, gfp_t gfp); 1036 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1037 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1038 { 1039 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1040 return buf->direct.buf + offset; 1041 else 1042 return buf->page_list[offset >> PAGE_SHIFT].buf + 1043 (offset & (PAGE_SIZE - 1)); 1044 } 1045 1046 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1047 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1048 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1049 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1050 1051 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1052 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1053 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1054 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1055 1056 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1057 struct mlx4_mtt *mtt); 1058 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1059 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1060 1061 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1062 int npages, int page_shift, struct mlx4_mr *mr); 1063 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1064 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1065 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1066 struct mlx4_mw *mw); 1067 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1068 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1069 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1070 int start_index, int npages, u64 *page_list); 1071 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1072 struct mlx4_buf *buf, gfp_t gfp); 1073 1074 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1075 gfp_t gfp); 1076 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1077 1078 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1079 int size, int max_direct); 1080 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1081 int size); 1082 1083 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1084 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1085 unsigned vector, int collapsed, int timestamp_en); 1086 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1087 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1088 int *base, u8 flags); 1089 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1090 1091 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1092 gfp_t gfp); 1093 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1094 1095 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1096 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1097 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1098 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1099 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1100 1101 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1102 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1103 1104 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1105 int block_mcast_loopback, enum mlx4_protocol prot); 1106 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1107 enum mlx4_protocol prot); 1108 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1109 u8 port, int block_mcast_loopback, 1110 enum mlx4_protocol protocol, u64 *reg_id); 1111 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1112 enum mlx4_protocol protocol, u64 reg_id); 1113 1114 enum { 1115 MLX4_DOMAIN_UVERBS = 0x1000, 1116 MLX4_DOMAIN_ETHTOOL = 0x2000, 1117 MLX4_DOMAIN_RFS = 0x3000, 1118 MLX4_DOMAIN_NIC = 0x5000, 1119 }; 1120 1121 enum mlx4_net_trans_rule_id { 1122 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1123 MLX4_NET_TRANS_RULE_ID_IB, 1124 MLX4_NET_TRANS_RULE_ID_IPV6, 1125 MLX4_NET_TRANS_RULE_ID_IPV4, 1126 MLX4_NET_TRANS_RULE_ID_TCP, 1127 MLX4_NET_TRANS_RULE_ID_UDP, 1128 MLX4_NET_TRANS_RULE_ID_VXLAN, 1129 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1130 }; 1131 1132 extern const u16 __sw_id_hw[]; 1133 1134 static inline int map_hw_to_sw_id(u16 header_id) 1135 { 1136 1137 int i; 1138 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1139 if (header_id == __sw_id_hw[i]) 1140 return i; 1141 } 1142 return -EINVAL; 1143 } 1144 1145 enum mlx4_net_trans_promisc_mode { 1146 MLX4_FS_REGULAR = 1, 1147 MLX4_FS_ALL_DEFAULT, 1148 MLX4_FS_MC_DEFAULT, 1149 MLX4_FS_UC_SNIFFER, 1150 MLX4_FS_MC_SNIFFER, 1151 MLX4_FS_MODE_NUM, /* should be last */ 1152 }; 1153 1154 struct mlx4_spec_eth { 1155 u8 dst_mac[ETH_ALEN]; 1156 u8 dst_mac_msk[ETH_ALEN]; 1157 u8 src_mac[ETH_ALEN]; 1158 u8 src_mac_msk[ETH_ALEN]; 1159 u8 ether_type_enable; 1160 __be16 ether_type; 1161 __be16 vlan_id_msk; 1162 __be16 vlan_id; 1163 }; 1164 1165 struct mlx4_spec_tcp_udp { 1166 __be16 dst_port; 1167 __be16 dst_port_msk; 1168 __be16 src_port; 1169 __be16 src_port_msk; 1170 }; 1171 1172 struct mlx4_spec_ipv4 { 1173 __be32 dst_ip; 1174 __be32 dst_ip_msk; 1175 __be32 src_ip; 1176 __be32 src_ip_msk; 1177 }; 1178 1179 struct mlx4_spec_ib { 1180 __be32 l3_qpn; 1181 __be32 qpn_msk; 1182 u8 dst_gid[16]; 1183 u8 dst_gid_msk[16]; 1184 }; 1185 1186 struct mlx4_spec_vxlan { 1187 __be32 vni; 1188 __be32 vni_mask; 1189 1190 }; 1191 1192 struct mlx4_spec_list { 1193 struct list_head list; 1194 enum mlx4_net_trans_rule_id id; 1195 union { 1196 struct mlx4_spec_eth eth; 1197 struct mlx4_spec_ib ib; 1198 struct mlx4_spec_ipv4 ipv4; 1199 struct mlx4_spec_tcp_udp tcp_udp; 1200 struct mlx4_spec_vxlan vxlan; 1201 }; 1202 }; 1203 1204 enum mlx4_net_trans_hw_rule_queue { 1205 MLX4_NET_TRANS_Q_FIFO, 1206 MLX4_NET_TRANS_Q_LIFO, 1207 }; 1208 1209 struct mlx4_net_trans_rule { 1210 struct list_head list; 1211 enum mlx4_net_trans_hw_rule_queue queue_mode; 1212 bool exclusive; 1213 bool allow_loopback; 1214 enum mlx4_net_trans_promisc_mode promisc_mode; 1215 u8 port; 1216 u16 priority; 1217 u32 qpn; 1218 }; 1219 1220 struct mlx4_net_trans_rule_hw_ctrl { 1221 __be16 prio; 1222 u8 type; 1223 u8 flags; 1224 u8 rsvd1; 1225 u8 funcid; 1226 u8 vep; 1227 u8 port; 1228 __be32 qpn; 1229 __be32 rsvd2; 1230 }; 1231 1232 struct mlx4_net_trans_rule_hw_ib { 1233 u8 size; 1234 u8 rsvd1; 1235 __be16 id; 1236 u32 rsvd2; 1237 __be32 l3_qpn; 1238 __be32 qpn_mask; 1239 u8 dst_gid[16]; 1240 u8 dst_gid_msk[16]; 1241 } __packed; 1242 1243 struct mlx4_net_trans_rule_hw_eth { 1244 u8 size; 1245 u8 rsvd; 1246 __be16 id; 1247 u8 rsvd1[6]; 1248 u8 dst_mac[6]; 1249 u16 rsvd2; 1250 u8 dst_mac_msk[6]; 1251 u16 rsvd3; 1252 u8 src_mac[6]; 1253 u16 rsvd4; 1254 u8 src_mac_msk[6]; 1255 u8 rsvd5; 1256 u8 ether_type_enable; 1257 __be16 ether_type; 1258 __be16 vlan_tag_msk; 1259 __be16 vlan_tag; 1260 } __packed; 1261 1262 struct mlx4_net_trans_rule_hw_tcp_udp { 1263 u8 size; 1264 u8 rsvd; 1265 __be16 id; 1266 __be16 rsvd1[3]; 1267 __be16 dst_port; 1268 __be16 rsvd2; 1269 __be16 dst_port_msk; 1270 __be16 rsvd3; 1271 __be16 src_port; 1272 __be16 rsvd4; 1273 __be16 src_port_msk; 1274 } __packed; 1275 1276 struct mlx4_net_trans_rule_hw_ipv4 { 1277 u8 size; 1278 u8 rsvd; 1279 __be16 id; 1280 __be32 rsvd1; 1281 __be32 dst_ip; 1282 __be32 dst_ip_msk; 1283 __be32 src_ip; 1284 __be32 src_ip_msk; 1285 } __packed; 1286 1287 struct mlx4_net_trans_rule_hw_vxlan { 1288 u8 size; 1289 u8 rsvd; 1290 __be16 id; 1291 __be32 rsvd1; 1292 __be32 vni; 1293 __be32 vni_mask; 1294 } __packed; 1295 1296 struct _rule_hw { 1297 union { 1298 struct { 1299 u8 size; 1300 u8 rsvd; 1301 __be16 id; 1302 }; 1303 struct mlx4_net_trans_rule_hw_eth eth; 1304 struct mlx4_net_trans_rule_hw_ib ib; 1305 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1306 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1307 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1308 }; 1309 }; 1310 1311 enum { 1312 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1313 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1314 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1315 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1316 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1317 }; 1318 1319 1320 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1321 enum mlx4_net_trans_promisc_mode mode); 1322 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1323 enum mlx4_net_trans_promisc_mode mode); 1324 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1325 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1326 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1327 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1328 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1329 1330 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1331 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1332 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1333 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1334 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1335 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1336 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1337 u8 promisc); 1338 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1339 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1340 u8 ignore_fcs_value); 1341 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1342 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1343 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1344 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1345 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1346 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1347 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1348 1349 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1350 int npages, u64 iova, u32 *lkey, u32 *rkey); 1351 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1352 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1353 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1354 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1355 u32 *lkey, u32 *rkey); 1356 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1357 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1358 int mlx4_test_interrupts(struct mlx4_dev *dev); 1359 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1360 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1361 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1362 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1363 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1364 1365 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1366 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1367 1368 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1369 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1370 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1371 1372 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1373 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1374 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1375 1376 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1377 int port); 1378 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1379 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1380 int mlx4_flow_attach(struct mlx4_dev *dev, 1381 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1382 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1383 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1384 enum mlx4_net_trans_promisc_mode flow_type); 1385 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1386 enum mlx4_net_trans_rule_id id); 1387 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1388 1389 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1390 int port, int qpn, u16 prio, u64 *reg_id); 1391 1392 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1393 int i, int val); 1394 1395 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1396 1397 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1398 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1399 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1400 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1401 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1402 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1403 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1404 1405 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1406 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1407 1408 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1409 int *slave_id); 1410 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1411 u8 *gid); 1412 1413 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1414 u32 max_range_qpn); 1415 1416 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1417 1418 struct mlx4_active_ports { 1419 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1420 }; 1421 /* Returns a bitmap of the physical ports which are assigned to slave */ 1422 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1423 1424 /* Returns the physical port that represents the virtual port of the slave, */ 1425 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1426 /* mapping is returned. */ 1427 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1428 1429 struct mlx4_slaves_pport { 1430 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1431 }; 1432 /* Returns a bitmap of all slaves that are assigned to port. */ 1433 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1434 int port); 1435 1436 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1437 /* the ports that are set in crit_ports. */ 1438 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1439 struct mlx4_dev *dev, 1440 const struct mlx4_active_ports *crit_ports); 1441 1442 /* Returns the slave's virtual port that represents the physical port. */ 1443 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1444 1445 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1446 1447 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1448 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1449 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1450 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1451 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1452 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1453 int enable); 1454 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1455 struct mlx4_mpt_entry ***mpt_entry); 1456 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1457 struct mlx4_mpt_entry **mpt_entry); 1458 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1459 u32 pdn); 1460 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1461 struct mlx4_mpt_entry *mpt_entry, 1462 u32 access); 1463 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1464 struct mlx4_mpt_entry **mpt_entry); 1465 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1466 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1467 u64 iova, u64 size, int npages, 1468 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1469 1470 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1471 u16 offset, u16 size, u8 *data); 1472 1473 /* Returns true if running in low memory profile (kdump kernel) */ 1474 static inline bool mlx4_low_memory_profile(void) 1475 { 1476 return is_kdump_kernel(); 1477 } 1478 1479 /* ACCESS REG commands */ 1480 enum mlx4_access_reg_method { 1481 MLX4_ACCESS_REG_QUERY = 0x1, 1482 MLX4_ACCESS_REG_WRITE = 0x2, 1483 }; 1484 1485 /* ACCESS PTYS Reg command */ 1486 enum mlx4_ptys_proto { 1487 MLX4_PTYS_IB = 1<<0, 1488 MLX4_PTYS_EN = 1<<2, 1489 }; 1490 1491 struct mlx4_ptys_reg { 1492 u8 resrvd1; 1493 u8 local_port; 1494 u8 resrvd2; 1495 u8 proto_mask; 1496 __be32 resrvd3[2]; 1497 __be32 eth_proto_cap; 1498 __be16 ib_width_cap; 1499 __be16 ib_speed_cap; 1500 __be32 resrvd4; 1501 __be32 eth_proto_admin; 1502 __be16 ib_width_admin; 1503 __be16 ib_speed_admin; 1504 __be32 resrvd5; 1505 __be32 eth_proto_oper; 1506 __be16 ib_width_oper; 1507 __be16 ib_speed_oper; 1508 __be32 resrvd6; 1509 __be32 eth_proto_lp_adv; 1510 } __packed; 1511 1512 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1513 enum mlx4_access_reg_method method, 1514 struct mlx4_ptys_reg *ptys_reg); 1515 1516 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1517 struct mlx4_clock_params *params); 1518 1519 #endif /* MLX4_DEVICE_H */ 1520