1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define DEFAULT_UAR_PAGE_SHIFT 12 48 49 #define MAX_MSIX_P_PORT 17 50 #define MAX_MSIX 64 51 #define MIN_MSIX_P_PORT 5 52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 53 (dev_cap).num_ports * MIN_MSIX_P_PORT) 54 55 #define MLX4_MAX_100M_UNITS_VAL 255 /* 56 * work around: can't set values 57 * greater then this value when 58 * using 100 Mbps units. 59 */ 60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 62 #define MLX4_RATELIMIT_DEFAULT 0x00ff 63 64 #define MLX4_ROCE_MAX_GIDS 128 65 #define MLX4_ROCE_PF_GIDS 16 66 67 enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 74 MLX4_FLAG_BONDED = 1 << 7, 75 MLX4_FLAG_SECURE_HOST = 1 << 8, 76 }; 77 78 enum { 79 MLX4_PORT_CAP_IS_SM = 1 << 1, 80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 81 }; 82 83 enum { 84 MLX4_MAX_PORTS = 2, 85 MLX4_MAX_PORT_PKEYS = 128, 86 MLX4_MAX_PORT_GIDS = 128 87 }; 88 89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 90 * These qkeys must not be allowed for general use. This is a 64k range, 91 * and to test for violation, we use the mask (protect against future chg). 92 */ 93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 95 96 enum { 97 MLX4_BOARD_ID_LEN = 64 98 }; 99 100 enum { 101 MLX4_MAX_NUM_PF = 16, 102 MLX4_MAX_NUM_VF = 126, 103 MLX4_MAX_NUM_VF_P_PORT = 64, 104 MLX4_MFUNC_MAX = 128, 105 MLX4_MAX_EQ_NUM = 1024, 106 MLX4_MFUNC_EQ_NUM = 4, 107 MLX4_MFUNC_MAX_EQES = 8, 108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 109 }; 110 111 /* Driver supports 3 different device methods to manage traffic steering: 112 * -device managed - High level API for ib and eth flow steering. FW is 113 * managing flow steering tables. 114 * - B0 steering mode - Common low level API for ib and (if supported) eth. 115 * - A0 steering mode - Limited low level API for eth. In case of IB, 116 * B0 mode is in use. 117 */ 118 enum { 119 MLX4_STEERING_MODE_A0, 120 MLX4_STEERING_MODE_B0, 121 MLX4_STEERING_MODE_DEVICE_MANAGED 122 }; 123 124 enum { 125 MLX4_STEERING_DMFS_A0_DEFAULT, 126 MLX4_STEERING_DMFS_A0_DYNAMIC, 127 MLX4_STEERING_DMFS_A0_STATIC, 128 MLX4_STEERING_DMFS_A0_DISABLE, 129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 130 }; 131 132 static inline const char *mlx4_steering_mode_str(int steering_mode) 133 { 134 switch (steering_mode) { 135 case MLX4_STEERING_MODE_A0: 136 return "A0 steering"; 137 138 case MLX4_STEERING_MODE_B0: 139 return "B0 steering"; 140 141 case MLX4_STEERING_MODE_DEVICE_MANAGED: 142 return "Device managed flow steering"; 143 144 default: 145 return "Unrecognize steering mode"; 146 } 147 } 148 149 enum { 150 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 152 }; 153 154 enum { 155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 186 }; 187 188 enum { 189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, 224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35, 225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36, 226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37, 227 }; 228 229 enum { 230 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 231 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 232 }; 233 234 enum { 235 MLX4_VF_CAP_FLAG_RESET = 1 << 0 236 }; 237 238 /* bit enums for an 8-bit flags field indicating special use 239 * QPs which require special handling in qp_reserve_range. 240 * Currently, this only includes QPs used by the ETH interface, 241 * where we expect to use blueflame. These QPs must not have 242 * bits 6 and 7 set in their qp number. 243 * 244 * This enum may use only bits 0..7. 245 */ 246 enum { 247 MLX4_RESERVE_A0_QP = 1 << 6, 248 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 249 }; 250 251 enum { 252 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 253 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 254 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 255 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 256 }; 257 258 enum { 259 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 260 }; 261 262 enum { 263 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 264 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 265 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 266 }; 267 268 269 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 270 271 enum { 272 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 273 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 274 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 275 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 276 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 277 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 278 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 279 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 280 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 281 }; 282 283 enum { 284 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 285 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 286 }; 287 288 enum mlx4_event { 289 MLX4_EVENT_TYPE_COMP = 0x00, 290 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 291 MLX4_EVENT_TYPE_COMM_EST = 0x02, 292 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 293 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 294 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 295 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 296 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 297 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 298 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 299 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 300 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 301 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 302 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 303 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 304 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 305 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 306 MLX4_EVENT_TYPE_CMD = 0x0a, 307 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 308 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 309 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 310 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 311 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 312 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 313 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 314 MLX4_EVENT_TYPE_NONE = 0xff, 315 }; 316 317 enum { 318 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 319 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 320 }; 321 322 enum { 323 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 324 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 325 }; 326 327 enum { 328 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 329 }; 330 331 enum slave_port_state { 332 SLAVE_PORT_DOWN = 0, 333 SLAVE_PENDING_UP, 334 SLAVE_PORT_UP, 335 }; 336 337 enum slave_port_gen_event { 338 SLAVE_PORT_GEN_EVENT_DOWN = 0, 339 SLAVE_PORT_GEN_EVENT_UP, 340 SLAVE_PORT_GEN_EVENT_NONE, 341 }; 342 343 enum slave_port_state_event { 344 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 345 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 346 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 347 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 348 }; 349 350 enum { 351 MLX4_PERM_LOCAL_READ = 1 << 10, 352 MLX4_PERM_LOCAL_WRITE = 1 << 11, 353 MLX4_PERM_REMOTE_READ = 1 << 12, 354 MLX4_PERM_REMOTE_WRITE = 1 << 13, 355 MLX4_PERM_ATOMIC = 1 << 14, 356 MLX4_PERM_BIND_MW = 1 << 15, 357 MLX4_PERM_MASK = 0xFC00 358 }; 359 360 enum { 361 MLX4_OPCODE_NOP = 0x00, 362 MLX4_OPCODE_SEND_INVAL = 0x01, 363 MLX4_OPCODE_RDMA_WRITE = 0x08, 364 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 365 MLX4_OPCODE_SEND = 0x0a, 366 MLX4_OPCODE_SEND_IMM = 0x0b, 367 MLX4_OPCODE_LSO = 0x0e, 368 MLX4_OPCODE_RDMA_READ = 0x10, 369 MLX4_OPCODE_ATOMIC_CS = 0x11, 370 MLX4_OPCODE_ATOMIC_FA = 0x12, 371 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 372 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 373 MLX4_OPCODE_BIND_MW = 0x18, 374 MLX4_OPCODE_FMR = 0x19, 375 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 376 MLX4_OPCODE_CONFIG_CMD = 0x1f, 377 378 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 379 MLX4_RECV_OPCODE_SEND = 0x01, 380 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 381 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 382 383 MLX4_CQE_OPCODE_ERROR = 0x1e, 384 MLX4_CQE_OPCODE_RESIZE = 0x16, 385 }; 386 387 enum { 388 MLX4_STAT_RATE_OFFSET = 5 389 }; 390 391 enum mlx4_protocol { 392 MLX4_PROT_IB_IPV6 = 0, 393 MLX4_PROT_ETH, 394 MLX4_PROT_IB_IPV4, 395 MLX4_PROT_FCOE 396 }; 397 398 enum { 399 MLX4_MTT_FLAG_PRESENT = 1 400 }; 401 402 enum mlx4_qp_region { 403 MLX4_QP_REGION_FW = 0, 404 MLX4_QP_REGION_RSS_RAW_ETH, 405 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 406 MLX4_QP_REGION_ETH_ADDR, 407 MLX4_QP_REGION_FC_ADDR, 408 MLX4_QP_REGION_FC_EXCH, 409 MLX4_NUM_QP_REGION 410 }; 411 412 enum mlx4_port_type { 413 MLX4_PORT_TYPE_NONE = 0, 414 MLX4_PORT_TYPE_IB = 1, 415 MLX4_PORT_TYPE_ETH = 2, 416 MLX4_PORT_TYPE_AUTO = 3 417 }; 418 419 enum mlx4_special_vlan_idx { 420 MLX4_NO_VLAN_IDX = 0, 421 MLX4_VLAN_MISS_IDX, 422 MLX4_VLAN_REGULAR 423 }; 424 425 enum mlx4_steer_type { 426 MLX4_MC_STEER = 0, 427 MLX4_UC_STEER, 428 MLX4_NUM_STEERS 429 }; 430 431 enum { 432 MLX4_NUM_FEXCH = 64 * 1024, 433 }; 434 435 enum { 436 MLX4_MAX_FAST_REG_PAGES = 511, 437 }; 438 439 enum { 440 /* 441 * Max wqe size for rdma read is 512 bytes, so this 442 * limits our max_sge_rd as the wqe needs to fit: 443 * - ctrl segment (16 bytes) 444 * - rdma segment (16 bytes) 445 * - scatter elements (16 bytes each) 446 */ 447 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 448 }; 449 450 enum { 451 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 452 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 453 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 454 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17, 455 }; 456 457 /* Port mgmt change event handling */ 458 enum { 459 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 460 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 461 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 462 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 463 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 464 }; 465 466 union sl2vl_tbl_to_u64 { 467 u8 sl8[8]; 468 u64 sl64; 469 }; 470 471 enum { 472 MLX4_DEVICE_STATE_UP = 1 << 0, 473 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 474 }; 475 476 enum { 477 MLX4_INTERFACE_STATE_UP = 1 << 0, 478 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 479 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2, 480 }; 481 482 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 483 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 484 485 enum mlx4_module_id { 486 MLX4_MODULE_ID_SFP = 0x3, 487 MLX4_MODULE_ID_QSFP = 0xC, 488 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 489 MLX4_MODULE_ID_QSFP28 = 0x11, 490 }; 491 492 enum { /* rl */ 493 MLX4_QP_RATE_LIMIT_NONE = 0, 494 MLX4_QP_RATE_LIMIT_KBS = 1, 495 MLX4_QP_RATE_LIMIT_MBS = 2, 496 MLX4_QP_RATE_LIMIT_GBS = 3 497 }; 498 499 struct mlx4_rate_limit_caps { 500 u16 num_rates; /* Number of different rates */ 501 u8 min_unit; 502 u16 min_val; 503 u8 max_unit; 504 u16 max_val; 505 }; 506 507 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 508 { 509 return (major << 32) | (minor << 16) | subminor; 510 } 511 512 struct mlx4_phys_caps { 513 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 514 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 515 u32 num_phys_eqs; 516 u32 base_sqpn; 517 u32 base_proxy_sqpn; 518 u32 base_tunnel_sqpn; 519 }; 520 521 struct mlx4_spec_qps { 522 u32 qp0_qkey; 523 u32 qp0_proxy; 524 u32 qp0_tunnel; 525 u32 qp1_proxy; 526 u32 qp1_tunnel; 527 }; 528 529 struct mlx4_caps { 530 u64 fw_ver; 531 u32 function; 532 int num_ports; 533 int vl_cap[MLX4_MAX_PORTS + 1]; 534 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 535 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 536 u64 def_mac[MLX4_MAX_PORTS + 1]; 537 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 538 int gid_table_len[MLX4_MAX_PORTS + 1]; 539 int pkey_table_len[MLX4_MAX_PORTS + 1]; 540 int trans_type[MLX4_MAX_PORTS + 1]; 541 int vendor_oui[MLX4_MAX_PORTS + 1]; 542 int wavelength[MLX4_MAX_PORTS + 1]; 543 u64 trans_code[MLX4_MAX_PORTS + 1]; 544 int local_ca_ack_delay; 545 int num_uars; 546 u32 uar_page_size; 547 int bf_reg_size; 548 int bf_regs_per_page; 549 int max_sq_sg; 550 int max_rq_sg; 551 int num_qps; 552 int max_wqes; 553 int max_sq_desc_sz; 554 int max_rq_desc_sz; 555 int max_qp_init_rdma; 556 int max_qp_dest_rdma; 557 int max_tc_eth; 558 struct mlx4_spec_qps *spec_qps; 559 int num_srqs; 560 int max_srq_wqes; 561 int max_srq_sge; 562 int reserved_srqs; 563 int num_cqs; 564 int max_cqes; 565 int reserved_cqs; 566 int num_sys_eqs; 567 int num_eqs; 568 int reserved_eqs; 569 int num_comp_vectors; 570 int num_mpts; 571 int max_fmr_maps; 572 int num_mtts; 573 int fmr_reserved_mtts; 574 int reserved_mtts; 575 int reserved_mrws; 576 int reserved_uars; 577 int num_mgms; 578 int num_amgms; 579 int reserved_mcgs; 580 int num_qp_per_mgm; 581 int steering_mode; 582 int dmfs_high_steer_mode; 583 int fs_log_max_ucast_qp_range_size; 584 int num_pds; 585 int reserved_pds; 586 int max_xrcds; 587 int reserved_xrcds; 588 int mtt_entry_sz; 589 u32 max_msg_sz; 590 u32 page_size_cap; 591 u64 flags; 592 u64 flags2; 593 u32 bmme_flags; 594 u32 reserved_lkey; 595 u16 stat_rate_support; 596 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 597 int max_gso_sz; 598 int max_rss_tbl_sz; 599 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 600 int reserved_qps; 601 int reserved_qps_base[MLX4_NUM_QP_REGION]; 602 int log_num_macs; 603 int log_num_vlans; 604 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 605 u8 supported_type[MLX4_MAX_PORTS + 1]; 606 u8 suggested_type[MLX4_MAX_PORTS + 1]; 607 u8 default_sense[MLX4_MAX_PORTS + 1]; 608 u32 port_mask[MLX4_MAX_PORTS + 1]; 609 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 610 u32 max_counters; 611 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 612 u16 sqp_demux; 613 u32 eqe_size; 614 u32 cqe_size; 615 u8 eqe_factor; 616 u32 userspace_caps; /* userspace must be aware of these */ 617 u32 function_caps; /* VFs must be aware of these */ 618 u16 hca_core_clock; 619 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 620 int tunnel_offload_mode; 621 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 622 u8 phv_bit[MLX4_MAX_PORTS + 1]; 623 u8 alloc_res_qp_mask; 624 u32 dmfs_high_rate_qpn_base; 625 u32 dmfs_high_rate_qpn_range; 626 u32 vf_caps; 627 bool wol_port[MLX4_MAX_PORTS + 1]; 628 struct mlx4_rate_limit_caps rl_caps; 629 }; 630 631 struct mlx4_buf_list { 632 void *buf; 633 dma_addr_t map; 634 }; 635 636 struct mlx4_buf { 637 struct mlx4_buf_list direct; 638 struct mlx4_buf_list *page_list; 639 int nbufs; 640 int npages; 641 int page_shift; 642 }; 643 644 struct mlx4_mtt { 645 u32 offset; 646 int order; 647 int page_shift; 648 }; 649 650 enum { 651 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 652 }; 653 654 struct mlx4_db_pgdir { 655 struct list_head list; 656 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 657 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 658 unsigned long *bits[2]; 659 __be32 *db_page; 660 dma_addr_t db_dma; 661 }; 662 663 struct mlx4_ib_user_db_page; 664 665 struct mlx4_db { 666 __be32 *db; 667 union { 668 struct mlx4_db_pgdir *pgdir; 669 struct mlx4_ib_user_db_page *user_page; 670 } u; 671 dma_addr_t dma; 672 int index; 673 int order; 674 }; 675 676 struct mlx4_hwq_resources { 677 struct mlx4_db db; 678 struct mlx4_mtt mtt; 679 struct mlx4_buf buf; 680 }; 681 682 struct mlx4_mr { 683 struct mlx4_mtt mtt; 684 u64 iova; 685 u64 size; 686 u32 key; 687 u32 pd; 688 u32 access; 689 int enabled; 690 }; 691 692 enum mlx4_mw_type { 693 MLX4_MW_TYPE_1 = 1, 694 MLX4_MW_TYPE_2 = 2, 695 }; 696 697 struct mlx4_mw { 698 u32 key; 699 u32 pd; 700 enum mlx4_mw_type type; 701 int enabled; 702 }; 703 704 struct mlx4_fmr { 705 struct mlx4_mr mr; 706 struct mlx4_mpt_entry *mpt; 707 __be64 *mtts; 708 dma_addr_t dma_handle; 709 int max_pages; 710 int max_maps; 711 int maps; 712 u8 page_shift; 713 }; 714 715 struct mlx4_uar { 716 unsigned long pfn; 717 int index; 718 struct list_head bf_list; 719 unsigned free_bf_bmap; 720 void __iomem *map; 721 void __iomem *bf_map; 722 }; 723 724 struct mlx4_bf { 725 unsigned int offset; 726 int buf_size; 727 struct mlx4_uar *uar; 728 void __iomem *reg; 729 }; 730 731 struct mlx4_cq { 732 void (*comp) (struct mlx4_cq *); 733 void (*event) (struct mlx4_cq *, enum mlx4_event); 734 735 struct mlx4_uar *uar; 736 737 u32 cons_index; 738 739 u16 irq; 740 __be32 *set_ci_db; 741 __be32 *arm_db; 742 int arm_sn; 743 744 int cqn; 745 unsigned vector; 746 747 atomic_t refcount; 748 struct completion free; 749 struct { 750 struct list_head list; 751 void (*comp)(struct mlx4_cq *); 752 void *priv; 753 } tasklet_ctx; 754 int reset_notify_added; 755 struct list_head reset_notify; 756 }; 757 758 struct mlx4_qp { 759 void (*event) (struct mlx4_qp *, enum mlx4_event); 760 761 int qpn; 762 763 atomic_t refcount; 764 struct completion free; 765 }; 766 767 struct mlx4_srq { 768 void (*event) (struct mlx4_srq *, enum mlx4_event); 769 770 int srqn; 771 int max; 772 int max_gs; 773 int wqe_shift; 774 775 atomic_t refcount; 776 struct completion free; 777 }; 778 779 struct mlx4_av { 780 __be32 port_pd; 781 u8 reserved1; 782 u8 g_slid; 783 __be16 dlid; 784 u8 reserved2; 785 u8 gid_index; 786 u8 stat_rate; 787 u8 hop_limit; 788 __be32 sl_tclass_flowlabel; 789 u8 dgid[16]; 790 }; 791 792 struct mlx4_eth_av { 793 __be32 port_pd; 794 u8 reserved1; 795 u8 smac_idx; 796 u16 reserved2; 797 u8 reserved3; 798 u8 gid_index; 799 u8 stat_rate; 800 u8 hop_limit; 801 __be32 sl_tclass_flowlabel; 802 u8 dgid[16]; 803 u8 s_mac[6]; 804 u8 reserved4[2]; 805 __be16 vlan; 806 u8 mac[ETH_ALEN]; 807 }; 808 809 union mlx4_ext_av { 810 struct mlx4_av ib; 811 struct mlx4_eth_av eth; 812 }; 813 814 /* Counters should be saturate once they reach their maximum value */ 815 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 816 if ((value) > U32_MAX) \ 817 counter = cpu_to_be32(U32_MAX); \ 818 else \ 819 counter = cpu_to_be32(value); \ 820 } while (0) 821 822 struct mlx4_counter { 823 u8 reserved1[3]; 824 u8 counter_mode; 825 __be32 num_ifc; 826 u32 reserved2[2]; 827 __be64 rx_frames; 828 __be64 rx_bytes; 829 __be64 tx_frames; 830 __be64 tx_bytes; 831 }; 832 833 struct mlx4_quotas { 834 int qp; 835 int cq; 836 int srq; 837 int mpt; 838 int mtt; 839 int counter; 840 int xrcd; 841 }; 842 843 struct mlx4_vf_dev { 844 u8 min_port; 845 u8 n_ports; 846 }; 847 848 enum mlx4_pci_status { 849 MLX4_PCI_STATUS_DISABLED, 850 MLX4_PCI_STATUS_ENABLED, 851 }; 852 853 struct mlx4_dev_persistent { 854 struct pci_dev *pdev; 855 struct mlx4_dev *dev; 856 int nvfs[MLX4_MAX_PORTS + 1]; 857 int num_vfs; 858 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 859 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 860 struct work_struct catas_work; 861 struct workqueue_struct *catas_wq; 862 struct mutex device_state_mutex; /* protect HW state */ 863 u8 state; 864 struct mutex interface_state_mutex; /* protect SW state */ 865 u8 interface_state; 866 struct mutex pci_status_mutex; /* sync pci state */ 867 enum mlx4_pci_status pci_status; 868 }; 869 870 struct mlx4_dev { 871 struct mlx4_dev_persistent *persist; 872 unsigned long flags; 873 unsigned long num_slaves; 874 struct mlx4_caps caps; 875 struct mlx4_phys_caps phys_caps; 876 struct mlx4_quotas quotas; 877 struct radix_tree_root qp_table_tree; 878 u8 rev_id; 879 u8 port_random_macs; 880 char board_id[MLX4_BOARD_ID_LEN]; 881 int numa_node; 882 int oper_log_mgm_entry_size; 883 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 884 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 885 struct mlx4_vf_dev *dev_vfs; 886 u8 uar_page_shift; 887 }; 888 889 struct mlx4_clock_params { 890 u64 offset; 891 u8 bar; 892 u8 size; 893 }; 894 895 struct mlx4_eqe { 896 u8 reserved1; 897 u8 type; 898 u8 reserved2; 899 u8 subtype; 900 union { 901 u32 raw[6]; 902 struct { 903 __be32 cqn; 904 } __packed comp; 905 struct { 906 u16 reserved1; 907 __be16 token; 908 u32 reserved2; 909 u8 reserved3[3]; 910 u8 status; 911 __be64 out_param; 912 } __packed cmd; 913 struct { 914 __be32 qpn; 915 } __packed qp; 916 struct { 917 __be32 srqn; 918 } __packed srq; 919 struct { 920 __be32 cqn; 921 u32 reserved1; 922 u8 reserved2[3]; 923 u8 syndrome; 924 } __packed cq_err; 925 struct { 926 u32 reserved1[2]; 927 __be32 port; 928 } __packed port_change; 929 struct { 930 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 931 u32 reserved; 932 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 933 } __packed comm_channel_arm; 934 struct { 935 u8 port; 936 u8 reserved[3]; 937 __be64 mac; 938 } __packed mac_update; 939 struct { 940 __be32 slave_id; 941 } __packed flr_event; 942 struct { 943 __be16 current_temperature; 944 __be16 warning_threshold; 945 } __packed warming; 946 struct { 947 u8 reserved[3]; 948 u8 port; 949 union { 950 struct { 951 __be16 mstr_sm_lid; 952 __be16 port_lid; 953 __be32 changed_attr; 954 u8 reserved[3]; 955 u8 mstr_sm_sl; 956 __be64 gid_prefix; 957 } __packed port_info; 958 struct { 959 __be32 block_ptr; 960 __be32 tbl_entries_mask; 961 } __packed tbl_change_info; 962 struct { 963 u8 sl2vl_table[8]; 964 } __packed sl2vl_tbl_change_info; 965 } params; 966 } __packed port_mgmt_change; 967 struct { 968 u8 reserved[3]; 969 u8 port; 970 u32 reserved1[5]; 971 } __packed bad_cable; 972 } event; 973 u8 slave_id; 974 u8 reserved3[2]; 975 u8 owner; 976 } __packed; 977 978 struct mlx4_init_port_param { 979 int set_guid0; 980 int set_node_guid; 981 int set_si_guid; 982 u16 mtu; 983 int port_width_cap; 984 u16 vl_cap; 985 u16 max_gid; 986 u16 max_pkey; 987 u64 guid0; 988 u64 node_guid; 989 u64 si_guid; 990 }; 991 992 #define MAD_IFC_DATA_SZ 192 993 /* MAD IFC Mailbox */ 994 struct mlx4_mad_ifc { 995 u8 base_version; 996 u8 mgmt_class; 997 u8 class_version; 998 u8 method; 999 __be16 status; 1000 __be16 class_specific; 1001 __be64 tid; 1002 __be16 attr_id; 1003 __be16 resv; 1004 __be32 attr_mod; 1005 __be64 mkey; 1006 __be16 dr_slid; 1007 __be16 dr_dlid; 1008 u8 reserved[28]; 1009 u8 data[MAD_IFC_DATA_SZ]; 1010 } __packed; 1011 1012 #define mlx4_foreach_port(port, dev, type) \ 1013 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1014 if ((type) == (dev)->caps.port_mask[(port)]) 1015 1016 #define mlx4_foreach_ib_transport_port(port, dev) \ 1017 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1018 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 1019 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH)) 1020 1021 #define MLX4_INVALID_SLAVE_ID 0xFF 1022 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 1023 1024 void handle_port_mgmt_change_event(struct work_struct *work); 1025 1026 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1027 { 1028 return dev->caps.function; 1029 } 1030 1031 static inline int mlx4_is_master(struct mlx4_dev *dev) 1032 { 1033 return dev->flags & MLX4_FLAG_MASTER; 1034 } 1035 1036 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1037 { 1038 return dev->phys_caps.base_sqpn + 8 + 1039 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1040 } 1041 1042 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1043 { 1044 return (qpn < dev->phys_caps.base_sqpn + 8 + 1045 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1046 qpn >= dev->phys_caps.base_sqpn) || 1047 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1048 } 1049 1050 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1051 { 1052 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1053 1054 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1055 return 1; 1056 1057 return 0; 1058 } 1059 1060 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1061 { 1062 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1063 } 1064 1065 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1066 { 1067 return dev->flags & MLX4_FLAG_SLAVE; 1068 } 1069 1070 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1071 { 1072 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1073 } 1074 1075 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1076 struct mlx4_buf *buf); 1077 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1078 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1079 { 1080 if (buf->nbufs == 1) 1081 return buf->direct.buf + offset; 1082 else 1083 return buf->page_list[offset >> PAGE_SHIFT].buf + 1084 (offset & (PAGE_SIZE - 1)); 1085 } 1086 1087 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1088 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1089 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1090 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1091 1092 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1093 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1094 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1095 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1096 1097 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1098 struct mlx4_mtt *mtt); 1099 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1100 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1101 1102 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1103 int npages, int page_shift, struct mlx4_mr *mr); 1104 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1105 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1106 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1107 struct mlx4_mw *mw); 1108 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1109 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1110 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1111 int start_index, int npages, u64 *page_list); 1112 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1113 struct mlx4_buf *buf); 1114 1115 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 1116 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1117 1118 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1119 int size); 1120 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1121 int size); 1122 1123 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1124 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1125 unsigned vector, int collapsed, int timestamp_en); 1126 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1127 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1128 int *base, u8 flags); 1129 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1130 1131 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1132 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1133 1134 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1135 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1136 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1137 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1138 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1139 1140 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1141 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1142 1143 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1144 int block_mcast_loopback, enum mlx4_protocol prot); 1145 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1146 enum mlx4_protocol prot); 1147 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1148 u8 port, int block_mcast_loopback, 1149 enum mlx4_protocol protocol, u64 *reg_id); 1150 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1151 enum mlx4_protocol protocol, u64 reg_id); 1152 1153 enum { 1154 MLX4_DOMAIN_UVERBS = 0x1000, 1155 MLX4_DOMAIN_ETHTOOL = 0x2000, 1156 MLX4_DOMAIN_RFS = 0x3000, 1157 MLX4_DOMAIN_NIC = 0x5000, 1158 }; 1159 1160 enum mlx4_net_trans_rule_id { 1161 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1162 MLX4_NET_TRANS_RULE_ID_IB, 1163 MLX4_NET_TRANS_RULE_ID_IPV6, 1164 MLX4_NET_TRANS_RULE_ID_IPV4, 1165 MLX4_NET_TRANS_RULE_ID_TCP, 1166 MLX4_NET_TRANS_RULE_ID_UDP, 1167 MLX4_NET_TRANS_RULE_ID_VXLAN, 1168 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1169 }; 1170 1171 extern const u16 __sw_id_hw[]; 1172 1173 static inline int map_hw_to_sw_id(u16 header_id) 1174 { 1175 1176 int i; 1177 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1178 if (header_id == __sw_id_hw[i]) 1179 return i; 1180 } 1181 return -EINVAL; 1182 } 1183 1184 enum mlx4_net_trans_promisc_mode { 1185 MLX4_FS_REGULAR = 1, 1186 MLX4_FS_ALL_DEFAULT, 1187 MLX4_FS_MC_DEFAULT, 1188 MLX4_FS_MIRROR_RX_PORT, 1189 MLX4_FS_MIRROR_SX_PORT, 1190 MLX4_FS_UC_SNIFFER, 1191 MLX4_FS_MC_SNIFFER, 1192 MLX4_FS_MODE_NUM, /* should be last */ 1193 }; 1194 1195 struct mlx4_spec_eth { 1196 u8 dst_mac[ETH_ALEN]; 1197 u8 dst_mac_msk[ETH_ALEN]; 1198 u8 src_mac[ETH_ALEN]; 1199 u8 src_mac_msk[ETH_ALEN]; 1200 u8 ether_type_enable; 1201 __be16 ether_type; 1202 __be16 vlan_id_msk; 1203 __be16 vlan_id; 1204 }; 1205 1206 struct mlx4_spec_tcp_udp { 1207 __be16 dst_port; 1208 __be16 dst_port_msk; 1209 __be16 src_port; 1210 __be16 src_port_msk; 1211 }; 1212 1213 struct mlx4_spec_ipv4 { 1214 __be32 dst_ip; 1215 __be32 dst_ip_msk; 1216 __be32 src_ip; 1217 __be32 src_ip_msk; 1218 }; 1219 1220 struct mlx4_spec_ib { 1221 __be32 l3_qpn; 1222 __be32 qpn_msk; 1223 u8 dst_gid[16]; 1224 u8 dst_gid_msk[16]; 1225 }; 1226 1227 struct mlx4_spec_vxlan { 1228 __be32 vni; 1229 __be32 vni_mask; 1230 1231 }; 1232 1233 struct mlx4_spec_list { 1234 struct list_head list; 1235 enum mlx4_net_trans_rule_id id; 1236 union { 1237 struct mlx4_spec_eth eth; 1238 struct mlx4_spec_ib ib; 1239 struct mlx4_spec_ipv4 ipv4; 1240 struct mlx4_spec_tcp_udp tcp_udp; 1241 struct mlx4_spec_vxlan vxlan; 1242 }; 1243 }; 1244 1245 enum mlx4_net_trans_hw_rule_queue { 1246 MLX4_NET_TRANS_Q_FIFO, 1247 MLX4_NET_TRANS_Q_LIFO, 1248 }; 1249 1250 struct mlx4_net_trans_rule { 1251 struct list_head list; 1252 enum mlx4_net_trans_hw_rule_queue queue_mode; 1253 bool exclusive; 1254 bool allow_loopback; 1255 enum mlx4_net_trans_promisc_mode promisc_mode; 1256 u8 port; 1257 u16 priority; 1258 u32 qpn; 1259 }; 1260 1261 struct mlx4_net_trans_rule_hw_ctrl { 1262 __be16 prio; 1263 u8 type; 1264 u8 flags; 1265 u8 rsvd1; 1266 u8 funcid; 1267 u8 vep; 1268 u8 port; 1269 __be32 qpn; 1270 __be32 rsvd2; 1271 }; 1272 1273 struct mlx4_net_trans_rule_hw_ib { 1274 u8 size; 1275 u8 rsvd1; 1276 __be16 id; 1277 u32 rsvd2; 1278 __be32 l3_qpn; 1279 __be32 qpn_mask; 1280 u8 dst_gid[16]; 1281 u8 dst_gid_msk[16]; 1282 } __packed; 1283 1284 struct mlx4_net_trans_rule_hw_eth { 1285 u8 size; 1286 u8 rsvd; 1287 __be16 id; 1288 u8 rsvd1[6]; 1289 u8 dst_mac[6]; 1290 u16 rsvd2; 1291 u8 dst_mac_msk[6]; 1292 u16 rsvd3; 1293 u8 src_mac[6]; 1294 u16 rsvd4; 1295 u8 src_mac_msk[6]; 1296 u8 rsvd5; 1297 u8 ether_type_enable; 1298 __be16 ether_type; 1299 __be16 vlan_tag_msk; 1300 __be16 vlan_tag; 1301 } __packed; 1302 1303 struct mlx4_net_trans_rule_hw_tcp_udp { 1304 u8 size; 1305 u8 rsvd; 1306 __be16 id; 1307 __be16 rsvd1[3]; 1308 __be16 dst_port; 1309 __be16 rsvd2; 1310 __be16 dst_port_msk; 1311 __be16 rsvd3; 1312 __be16 src_port; 1313 __be16 rsvd4; 1314 __be16 src_port_msk; 1315 } __packed; 1316 1317 struct mlx4_net_trans_rule_hw_ipv4 { 1318 u8 size; 1319 u8 rsvd; 1320 __be16 id; 1321 __be32 rsvd1; 1322 __be32 dst_ip; 1323 __be32 dst_ip_msk; 1324 __be32 src_ip; 1325 __be32 src_ip_msk; 1326 } __packed; 1327 1328 struct mlx4_net_trans_rule_hw_vxlan { 1329 u8 size; 1330 u8 rsvd; 1331 __be16 id; 1332 __be32 rsvd1; 1333 __be32 vni; 1334 __be32 vni_mask; 1335 } __packed; 1336 1337 struct _rule_hw { 1338 union { 1339 struct { 1340 u8 size; 1341 u8 rsvd; 1342 __be16 id; 1343 }; 1344 struct mlx4_net_trans_rule_hw_eth eth; 1345 struct mlx4_net_trans_rule_hw_ib ib; 1346 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1347 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1348 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1349 }; 1350 }; 1351 1352 enum { 1353 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1354 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1355 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1356 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1357 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1358 }; 1359 1360 enum { 1361 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2, 1362 }; 1363 1364 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1365 enum mlx4_net_trans_promisc_mode mode); 1366 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1367 enum mlx4_net_trans_promisc_mode mode); 1368 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1369 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1370 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1371 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1372 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1373 1374 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1375 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1376 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1377 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1378 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1379 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1380 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu); 1381 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1382 u8 promisc); 1383 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1384 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1385 u8 ignore_fcs_value); 1386 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1387 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1388 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1389 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 1390 bool *vlan_offload_disabled); 1391 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 1392 struct _rule_hw *eth_header); 1393 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1394 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1395 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1396 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1397 1398 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1399 int npages, u64 iova, u32 *lkey, u32 *rkey); 1400 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1401 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1402 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1403 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1404 u32 *lkey, u32 *rkey); 1405 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1406 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1407 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector); 1408 int mlx4_test_async(struct mlx4_dev *dev); 1409 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 1410 const u32 offset[], u32 value[], 1411 size_t array_len, u8 port); 1412 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1413 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1414 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1415 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1416 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1417 1418 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1419 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1420 1421 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1422 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1423 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1424 1425 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1426 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1427 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1428 1429 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1430 int port); 1431 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1432 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1433 int mlx4_flow_attach(struct mlx4_dev *dev, 1434 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1435 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1436 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1437 enum mlx4_net_trans_promisc_mode flow_type); 1438 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1439 enum mlx4_net_trans_rule_id id); 1440 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1441 1442 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1443 int port, int qpn, u16 prio, u64 *reg_id); 1444 1445 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1446 int i, int val); 1447 1448 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1449 1450 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1451 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1452 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1453 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1454 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1455 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1456 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1457 1458 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1459 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1460 1461 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1462 int *slave_id); 1463 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1464 u8 *gid); 1465 1466 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1467 u32 max_range_qpn); 1468 1469 u64 mlx4_read_clock(struct mlx4_dev *dev); 1470 1471 struct mlx4_active_ports { 1472 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1473 }; 1474 /* Returns a bitmap of the physical ports which are assigned to slave */ 1475 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1476 1477 /* Returns the physical port that represents the virtual port of the slave, */ 1478 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1479 /* mapping is returned. */ 1480 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1481 1482 struct mlx4_slaves_pport { 1483 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1484 }; 1485 /* Returns a bitmap of all slaves that are assigned to port. */ 1486 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1487 int port); 1488 1489 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1490 /* the ports that are set in crit_ports. */ 1491 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1492 struct mlx4_dev *dev, 1493 const struct mlx4_active_ports *crit_ports); 1494 1495 /* Returns the slave's virtual port that represents the physical port. */ 1496 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1497 1498 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1499 1500 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1501 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1502 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1503 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1504 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1505 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1506 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1507 int enable); 1508 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1509 struct mlx4_mpt_entry ***mpt_entry); 1510 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1511 struct mlx4_mpt_entry **mpt_entry); 1512 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1513 u32 pdn); 1514 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1515 struct mlx4_mpt_entry *mpt_entry, 1516 u32 access); 1517 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1518 struct mlx4_mpt_entry **mpt_entry); 1519 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1520 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1521 u64 iova, u64 size, int npages, 1522 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1523 1524 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1525 u16 offset, u16 size, u8 *data); 1526 int mlx4_max_tc(struct mlx4_dev *dev); 1527 1528 /* Returns true if running in low memory profile (kdump kernel) */ 1529 static inline bool mlx4_low_memory_profile(void) 1530 { 1531 return is_kdump_kernel(); 1532 } 1533 1534 /* ACCESS REG commands */ 1535 enum mlx4_access_reg_method { 1536 MLX4_ACCESS_REG_QUERY = 0x1, 1537 MLX4_ACCESS_REG_WRITE = 0x2, 1538 }; 1539 1540 /* ACCESS PTYS Reg command */ 1541 enum mlx4_ptys_proto { 1542 MLX4_PTYS_IB = 1<<0, 1543 MLX4_PTYS_EN = 1<<2, 1544 }; 1545 1546 enum mlx4_ptys_flags { 1547 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5, 1548 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6, 1549 }; 1550 1551 struct mlx4_ptys_reg { 1552 u8 flags; 1553 u8 local_port; 1554 u8 resrvd2; 1555 u8 proto_mask; 1556 __be32 resrvd3[2]; 1557 __be32 eth_proto_cap; 1558 __be16 ib_width_cap; 1559 __be16 ib_speed_cap; 1560 __be32 resrvd4; 1561 __be32 eth_proto_admin; 1562 __be16 ib_width_admin; 1563 __be16 ib_speed_admin; 1564 __be32 resrvd5; 1565 __be32 eth_proto_oper; 1566 __be16 ib_width_oper; 1567 __be16 ib_speed_oper; 1568 __be32 resrvd6; 1569 __be32 eth_proto_lp_adv; 1570 } __packed; 1571 1572 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1573 enum mlx4_access_reg_method method, 1574 struct mlx4_ptys_reg *ptys_reg); 1575 1576 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1577 struct mlx4_clock_params *params); 1578 1579 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1580 { 1581 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1582 } 1583 1584 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1585 { 1586 /* The first 128 UARs are used for EQ doorbells */ 1587 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1588 } 1589 #endif /* MLX4_DEVICE_H */ 1590