1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define DEFAULT_UAR_PAGE_SHIFT 12 48 49 #define MAX_MSIX_P_PORT 17 50 #define MAX_MSIX 64 51 #define MIN_MSIX_P_PORT 5 52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 53 (dev_cap).num_ports * MIN_MSIX_P_PORT) 54 55 #define MLX4_MAX_100M_UNITS_VAL 255 /* 56 * work around: can't set values 57 * greater then this value when 58 * using 100 Mbps units. 59 */ 60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 62 #define MLX4_RATELIMIT_DEFAULT 0x00ff 63 64 #define MLX4_ROCE_MAX_GIDS 128 65 #define MLX4_ROCE_PF_GIDS 16 66 67 enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 74 MLX4_FLAG_BONDED = 1 << 7, 75 MLX4_FLAG_SECURE_HOST = 1 << 8, 76 }; 77 78 enum { 79 MLX4_PORT_CAP_IS_SM = 1 << 1, 80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 81 }; 82 83 enum { 84 MLX4_MAX_PORTS = 2, 85 MLX4_MAX_PORT_PKEYS = 128, 86 MLX4_MAX_PORT_GIDS = 128 87 }; 88 89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 90 * These qkeys must not be allowed for general use. This is a 64k range, 91 * and to test for violation, we use the mask (protect against future chg). 92 */ 93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 95 96 enum { 97 MLX4_BOARD_ID_LEN = 64 98 }; 99 100 enum { 101 MLX4_MAX_NUM_PF = 16, 102 MLX4_MAX_NUM_VF = 126, 103 MLX4_MAX_NUM_VF_P_PORT = 64, 104 MLX4_MFUNC_MAX = 128, 105 MLX4_MAX_EQ_NUM = 1024, 106 MLX4_MFUNC_EQ_NUM = 4, 107 MLX4_MFUNC_MAX_EQES = 8, 108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 109 }; 110 111 /* Driver supports 3 different device methods to manage traffic steering: 112 * -device managed - High level API for ib and eth flow steering. FW is 113 * managing flow steering tables. 114 * - B0 steering mode - Common low level API for ib and (if supported) eth. 115 * - A0 steering mode - Limited low level API for eth. In case of IB, 116 * B0 mode is in use. 117 */ 118 enum { 119 MLX4_STEERING_MODE_A0, 120 MLX4_STEERING_MODE_B0, 121 MLX4_STEERING_MODE_DEVICE_MANAGED 122 }; 123 124 enum { 125 MLX4_STEERING_DMFS_A0_DEFAULT, 126 MLX4_STEERING_DMFS_A0_DYNAMIC, 127 MLX4_STEERING_DMFS_A0_STATIC, 128 MLX4_STEERING_DMFS_A0_DISABLE, 129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 130 }; 131 132 static inline const char *mlx4_steering_mode_str(int steering_mode) 133 { 134 switch (steering_mode) { 135 case MLX4_STEERING_MODE_A0: 136 return "A0 steering"; 137 138 case MLX4_STEERING_MODE_B0: 139 return "B0 steering"; 140 141 case MLX4_STEERING_MODE_DEVICE_MANAGED: 142 return "Device managed flow steering"; 143 144 default: 145 return "Unrecognize steering mode"; 146 } 147 } 148 149 enum { 150 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 152 }; 153 154 enum { 155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 186 }; 187 188 enum { 189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, 224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35, 225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36, 226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37, 227 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38, 228 }; 229 230 enum { 231 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 232 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 233 }; 234 235 enum { 236 MLX4_VF_CAP_FLAG_RESET = 1 << 0 237 }; 238 239 /* bit enums for an 8-bit flags field indicating special use 240 * QPs which require special handling in qp_reserve_range. 241 * Currently, this only includes QPs used by the ETH interface, 242 * where we expect to use blueflame. These QPs must not have 243 * bits 6 and 7 set in their qp number. 244 * 245 * This enum may use only bits 0..7. 246 */ 247 enum { 248 MLX4_RESERVE_A0_QP = 1 << 6, 249 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 250 }; 251 252 enum { 253 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 254 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 255 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 256 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 257 }; 258 259 enum { 260 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 261 }; 262 263 enum { 264 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 265 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 266 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 267 }; 268 269 270 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 271 272 enum { 273 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 274 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 275 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 276 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 277 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 278 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 279 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 280 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 281 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 282 }; 283 284 enum { 285 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 286 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 287 }; 288 289 enum mlx4_event { 290 MLX4_EVENT_TYPE_COMP = 0x00, 291 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 292 MLX4_EVENT_TYPE_COMM_EST = 0x02, 293 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 294 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 295 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 296 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 297 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 298 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 299 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 300 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 301 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 302 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 303 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 304 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 305 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 306 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 307 MLX4_EVENT_TYPE_CMD = 0x0a, 308 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 309 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 310 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 311 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 312 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 313 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 314 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 315 MLX4_EVENT_TYPE_NONE = 0xff, 316 }; 317 318 enum { 319 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 320 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 321 }; 322 323 enum { 324 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 325 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 326 }; 327 328 enum { 329 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 330 }; 331 332 enum slave_port_state { 333 SLAVE_PORT_DOWN = 0, 334 SLAVE_PENDING_UP, 335 SLAVE_PORT_UP, 336 }; 337 338 enum slave_port_gen_event { 339 SLAVE_PORT_GEN_EVENT_DOWN = 0, 340 SLAVE_PORT_GEN_EVENT_UP, 341 SLAVE_PORT_GEN_EVENT_NONE, 342 }; 343 344 enum slave_port_state_event { 345 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 346 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 347 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 348 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 349 }; 350 351 enum { 352 MLX4_PERM_LOCAL_READ = 1 << 10, 353 MLX4_PERM_LOCAL_WRITE = 1 << 11, 354 MLX4_PERM_REMOTE_READ = 1 << 12, 355 MLX4_PERM_REMOTE_WRITE = 1 << 13, 356 MLX4_PERM_ATOMIC = 1 << 14, 357 MLX4_PERM_BIND_MW = 1 << 15, 358 MLX4_PERM_MASK = 0xFC00 359 }; 360 361 enum { 362 MLX4_OPCODE_NOP = 0x00, 363 MLX4_OPCODE_SEND_INVAL = 0x01, 364 MLX4_OPCODE_RDMA_WRITE = 0x08, 365 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 366 MLX4_OPCODE_SEND = 0x0a, 367 MLX4_OPCODE_SEND_IMM = 0x0b, 368 MLX4_OPCODE_LSO = 0x0e, 369 MLX4_OPCODE_RDMA_READ = 0x10, 370 MLX4_OPCODE_ATOMIC_CS = 0x11, 371 MLX4_OPCODE_ATOMIC_FA = 0x12, 372 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 373 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 374 MLX4_OPCODE_BIND_MW = 0x18, 375 MLX4_OPCODE_FMR = 0x19, 376 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 377 MLX4_OPCODE_CONFIG_CMD = 0x1f, 378 379 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 380 MLX4_RECV_OPCODE_SEND = 0x01, 381 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 382 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 383 384 MLX4_CQE_OPCODE_ERROR = 0x1e, 385 MLX4_CQE_OPCODE_RESIZE = 0x16, 386 }; 387 388 enum { 389 MLX4_STAT_RATE_OFFSET = 5 390 }; 391 392 enum mlx4_protocol { 393 MLX4_PROT_IB_IPV6 = 0, 394 MLX4_PROT_ETH, 395 MLX4_PROT_IB_IPV4, 396 MLX4_PROT_FCOE 397 }; 398 399 enum { 400 MLX4_MTT_FLAG_PRESENT = 1 401 }; 402 403 enum mlx4_qp_region { 404 MLX4_QP_REGION_FW = 0, 405 MLX4_QP_REGION_RSS_RAW_ETH, 406 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 407 MLX4_QP_REGION_ETH_ADDR, 408 MLX4_QP_REGION_FC_ADDR, 409 MLX4_QP_REGION_FC_EXCH, 410 MLX4_NUM_QP_REGION 411 }; 412 413 enum mlx4_port_type { 414 MLX4_PORT_TYPE_NONE = 0, 415 MLX4_PORT_TYPE_IB = 1, 416 MLX4_PORT_TYPE_ETH = 2, 417 MLX4_PORT_TYPE_AUTO = 3 418 }; 419 420 enum mlx4_special_vlan_idx { 421 MLX4_NO_VLAN_IDX = 0, 422 MLX4_VLAN_MISS_IDX, 423 MLX4_VLAN_REGULAR 424 }; 425 426 enum mlx4_steer_type { 427 MLX4_MC_STEER = 0, 428 MLX4_UC_STEER, 429 MLX4_NUM_STEERS 430 }; 431 432 enum { 433 MLX4_NUM_FEXCH = 64 * 1024, 434 }; 435 436 enum { 437 MLX4_MAX_FAST_REG_PAGES = 511, 438 }; 439 440 enum { 441 /* 442 * Max wqe size for rdma read is 512 bytes, so this 443 * limits our max_sge_rd as the wqe needs to fit: 444 * - ctrl segment (16 bytes) 445 * - rdma segment (16 bytes) 446 * - scatter elements (16 bytes each) 447 */ 448 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 449 }; 450 451 enum { 452 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 453 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 454 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 455 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17, 456 }; 457 458 /* Port mgmt change event handling */ 459 enum { 460 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 461 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 462 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 463 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 464 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 465 }; 466 467 union sl2vl_tbl_to_u64 { 468 u8 sl8[8]; 469 u64 sl64; 470 }; 471 472 enum { 473 MLX4_DEVICE_STATE_UP = 1 << 0, 474 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 475 }; 476 477 enum { 478 MLX4_INTERFACE_STATE_UP = 1 << 0, 479 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 480 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2, 481 }; 482 483 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 484 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 485 486 enum mlx4_module_id { 487 MLX4_MODULE_ID_SFP = 0x3, 488 MLX4_MODULE_ID_QSFP = 0xC, 489 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 490 MLX4_MODULE_ID_QSFP28 = 0x11, 491 }; 492 493 enum { /* rl */ 494 MLX4_QP_RATE_LIMIT_NONE = 0, 495 MLX4_QP_RATE_LIMIT_KBS = 1, 496 MLX4_QP_RATE_LIMIT_MBS = 2, 497 MLX4_QP_RATE_LIMIT_GBS = 3 498 }; 499 500 struct mlx4_rate_limit_caps { 501 u16 num_rates; /* Number of different rates */ 502 u8 min_unit; 503 u16 min_val; 504 u8 max_unit; 505 u16 max_val; 506 }; 507 508 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 509 { 510 return (major << 32) | (minor << 16) | subminor; 511 } 512 513 struct mlx4_phys_caps { 514 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 515 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 516 u32 num_phys_eqs; 517 u32 base_sqpn; 518 u32 base_proxy_sqpn; 519 u32 base_tunnel_sqpn; 520 }; 521 522 struct mlx4_spec_qps { 523 u32 qp0_qkey; 524 u32 qp0_proxy; 525 u32 qp0_tunnel; 526 u32 qp1_proxy; 527 u32 qp1_tunnel; 528 }; 529 530 struct mlx4_caps { 531 u64 fw_ver; 532 u32 function; 533 int num_ports; 534 int vl_cap[MLX4_MAX_PORTS + 1]; 535 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 536 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 537 u64 def_mac[MLX4_MAX_PORTS + 1]; 538 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 539 int gid_table_len[MLX4_MAX_PORTS + 1]; 540 int pkey_table_len[MLX4_MAX_PORTS + 1]; 541 int trans_type[MLX4_MAX_PORTS + 1]; 542 int vendor_oui[MLX4_MAX_PORTS + 1]; 543 int wavelength[MLX4_MAX_PORTS + 1]; 544 u64 trans_code[MLX4_MAX_PORTS + 1]; 545 int local_ca_ack_delay; 546 int num_uars; 547 u32 uar_page_size; 548 int bf_reg_size; 549 int bf_regs_per_page; 550 int max_sq_sg; 551 int max_rq_sg; 552 int num_qps; 553 int max_wqes; 554 int max_sq_desc_sz; 555 int max_rq_desc_sz; 556 int max_qp_init_rdma; 557 int max_qp_dest_rdma; 558 int max_tc_eth; 559 struct mlx4_spec_qps *spec_qps; 560 int num_srqs; 561 int max_srq_wqes; 562 int max_srq_sge; 563 int reserved_srqs; 564 int num_cqs; 565 int max_cqes; 566 int reserved_cqs; 567 int num_sys_eqs; 568 int num_eqs; 569 int reserved_eqs; 570 int num_comp_vectors; 571 int num_mpts; 572 int max_fmr_maps; 573 int num_mtts; 574 int fmr_reserved_mtts; 575 int reserved_mtts; 576 int reserved_mrws; 577 int reserved_uars; 578 int num_mgms; 579 int num_amgms; 580 int reserved_mcgs; 581 int num_qp_per_mgm; 582 int steering_mode; 583 int dmfs_high_steer_mode; 584 int fs_log_max_ucast_qp_range_size; 585 int num_pds; 586 int reserved_pds; 587 int max_xrcds; 588 int reserved_xrcds; 589 int mtt_entry_sz; 590 u32 max_msg_sz; 591 u32 page_size_cap; 592 u64 flags; 593 u64 flags2; 594 u32 bmme_flags; 595 u32 reserved_lkey; 596 u16 stat_rate_support; 597 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 598 int max_gso_sz; 599 int max_rss_tbl_sz; 600 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 601 int reserved_qps; 602 int reserved_qps_base[MLX4_NUM_QP_REGION]; 603 int log_num_macs; 604 int log_num_vlans; 605 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 606 u8 supported_type[MLX4_MAX_PORTS + 1]; 607 u8 suggested_type[MLX4_MAX_PORTS + 1]; 608 u8 default_sense[MLX4_MAX_PORTS + 1]; 609 u32 port_mask[MLX4_MAX_PORTS + 1]; 610 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 611 u32 max_counters; 612 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 613 u16 sqp_demux; 614 u32 eqe_size; 615 u32 cqe_size; 616 u8 eqe_factor; 617 u32 userspace_caps; /* userspace must be aware of these */ 618 u32 function_caps; /* VFs must be aware of these */ 619 u16 hca_core_clock; 620 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 621 int tunnel_offload_mode; 622 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 623 u8 phv_bit[MLX4_MAX_PORTS + 1]; 624 u8 alloc_res_qp_mask; 625 u32 dmfs_high_rate_qpn_base; 626 u32 dmfs_high_rate_qpn_range; 627 u32 vf_caps; 628 bool wol_port[MLX4_MAX_PORTS + 1]; 629 struct mlx4_rate_limit_caps rl_caps; 630 }; 631 632 struct mlx4_buf_list { 633 void *buf; 634 dma_addr_t map; 635 }; 636 637 struct mlx4_buf { 638 struct mlx4_buf_list direct; 639 struct mlx4_buf_list *page_list; 640 int nbufs; 641 int npages; 642 int page_shift; 643 }; 644 645 struct mlx4_mtt { 646 u32 offset; 647 int order; 648 int page_shift; 649 }; 650 651 enum { 652 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 653 }; 654 655 struct mlx4_db_pgdir { 656 struct list_head list; 657 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 658 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 659 unsigned long *bits[2]; 660 __be32 *db_page; 661 dma_addr_t db_dma; 662 }; 663 664 struct mlx4_ib_user_db_page; 665 666 struct mlx4_db { 667 __be32 *db; 668 union { 669 struct mlx4_db_pgdir *pgdir; 670 struct mlx4_ib_user_db_page *user_page; 671 } u; 672 dma_addr_t dma; 673 int index; 674 int order; 675 }; 676 677 struct mlx4_hwq_resources { 678 struct mlx4_db db; 679 struct mlx4_mtt mtt; 680 struct mlx4_buf buf; 681 }; 682 683 struct mlx4_mr { 684 struct mlx4_mtt mtt; 685 u64 iova; 686 u64 size; 687 u32 key; 688 u32 pd; 689 u32 access; 690 int enabled; 691 }; 692 693 enum mlx4_mw_type { 694 MLX4_MW_TYPE_1 = 1, 695 MLX4_MW_TYPE_2 = 2, 696 }; 697 698 struct mlx4_mw { 699 u32 key; 700 u32 pd; 701 enum mlx4_mw_type type; 702 int enabled; 703 }; 704 705 struct mlx4_fmr { 706 struct mlx4_mr mr; 707 struct mlx4_mpt_entry *mpt; 708 __be64 *mtts; 709 dma_addr_t dma_handle; 710 int max_pages; 711 int max_maps; 712 int maps; 713 u8 page_shift; 714 }; 715 716 struct mlx4_uar { 717 unsigned long pfn; 718 int index; 719 struct list_head bf_list; 720 unsigned free_bf_bmap; 721 void __iomem *map; 722 void __iomem *bf_map; 723 }; 724 725 struct mlx4_bf { 726 unsigned int offset; 727 int buf_size; 728 struct mlx4_uar *uar; 729 void __iomem *reg; 730 }; 731 732 struct mlx4_cq { 733 void (*comp) (struct mlx4_cq *); 734 void (*event) (struct mlx4_cq *, enum mlx4_event); 735 736 struct mlx4_uar *uar; 737 738 u32 cons_index; 739 740 u16 irq; 741 __be32 *set_ci_db; 742 __be32 *arm_db; 743 int arm_sn; 744 745 int cqn; 746 unsigned vector; 747 748 atomic_t refcount; 749 struct completion free; 750 struct { 751 struct list_head list; 752 void (*comp)(struct mlx4_cq *); 753 void *priv; 754 } tasklet_ctx; 755 int reset_notify_added; 756 struct list_head reset_notify; 757 }; 758 759 struct mlx4_qp { 760 void (*event) (struct mlx4_qp *, enum mlx4_event); 761 762 int qpn; 763 764 atomic_t refcount; 765 struct completion free; 766 }; 767 768 struct mlx4_srq { 769 void (*event) (struct mlx4_srq *, enum mlx4_event); 770 771 int srqn; 772 int max; 773 int max_gs; 774 int wqe_shift; 775 776 atomic_t refcount; 777 struct completion free; 778 }; 779 780 struct mlx4_av { 781 __be32 port_pd; 782 u8 reserved1; 783 u8 g_slid; 784 __be16 dlid; 785 u8 reserved2; 786 u8 gid_index; 787 u8 stat_rate; 788 u8 hop_limit; 789 __be32 sl_tclass_flowlabel; 790 u8 dgid[16]; 791 }; 792 793 struct mlx4_eth_av { 794 __be32 port_pd; 795 u8 reserved1; 796 u8 smac_idx; 797 u16 reserved2; 798 u8 reserved3; 799 u8 gid_index; 800 u8 stat_rate; 801 u8 hop_limit; 802 __be32 sl_tclass_flowlabel; 803 u8 dgid[16]; 804 u8 s_mac[6]; 805 u8 reserved4[2]; 806 __be16 vlan; 807 u8 mac[ETH_ALEN]; 808 }; 809 810 union mlx4_ext_av { 811 struct mlx4_av ib; 812 struct mlx4_eth_av eth; 813 }; 814 815 /* Counters should be saturate once they reach their maximum value */ 816 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 817 if ((value) > U32_MAX) \ 818 counter = cpu_to_be32(U32_MAX); \ 819 else \ 820 counter = cpu_to_be32(value); \ 821 } while (0) 822 823 struct mlx4_counter { 824 u8 reserved1[3]; 825 u8 counter_mode; 826 __be32 num_ifc; 827 u32 reserved2[2]; 828 __be64 rx_frames; 829 __be64 rx_bytes; 830 __be64 tx_frames; 831 __be64 tx_bytes; 832 }; 833 834 struct mlx4_quotas { 835 int qp; 836 int cq; 837 int srq; 838 int mpt; 839 int mtt; 840 int counter; 841 int xrcd; 842 }; 843 844 struct mlx4_vf_dev { 845 u8 min_port; 846 u8 n_ports; 847 }; 848 849 enum mlx4_pci_status { 850 MLX4_PCI_STATUS_DISABLED, 851 MLX4_PCI_STATUS_ENABLED, 852 }; 853 854 struct mlx4_dev_persistent { 855 struct pci_dev *pdev; 856 struct mlx4_dev *dev; 857 int nvfs[MLX4_MAX_PORTS + 1]; 858 int num_vfs; 859 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 860 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 861 struct work_struct catas_work; 862 struct workqueue_struct *catas_wq; 863 struct mutex device_state_mutex; /* protect HW state */ 864 u8 state; 865 struct mutex interface_state_mutex; /* protect SW state */ 866 u8 interface_state; 867 struct mutex pci_status_mutex; /* sync pci state */ 868 enum mlx4_pci_status pci_status; 869 }; 870 871 struct mlx4_dev { 872 struct mlx4_dev_persistent *persist; 873 unsigned long flags; 874 unsigned long num_slaves; 875 struct mlx4_caps caps; 876 struct mlx4_phys_caps phys_caps; 877 struct mlx4_quotas quotas; 878 struct radix_tree_root qp_table_tree; 879 u8 rev_id; 880 u8 port_random_macs; 881 char board_id[MLX4_BOARD_ID_LEN]; 882 int numa_node; 883 int oper_log_mgm_entry_size; 884 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 885 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 886 struct mlx4_vf_dev *dev_vfs; 887 u8 uar_page_shift; 888 }; 889 890 struct mlx4_clock_params { 891 u64 offset; 892 u8 bar; 893 u8 size; 894 }; 895 896 struct mlx4_eqe { 897 u8 reserved1; 898 u8 type; 899 u8 reserved2; 900 u8 subtype; 901 union { 902 u32 raw[6]; 903 struct { 904 __be32 cqn; 905 } __packed comp; 906 struct { 907 u16 reserved1; 908 __be16 token; 909 u32 reserved2; 910 u8 reserved3[3]; 911 u8 status; 912 __be64 out_param; 913 } __packed cmd; 914 struct { 915 __be32 qpn; 916 } __packed qp; 917 struct { 918 __be32 srqn; 919 } __packed srq; 920 struct { 921 __be32 cqn; 922 u32 reserved1; 923 u8 reserved2[3]; 924 u8 syndrome; 925 } __packed cq_err; 926 struct { 927 u32 reserved1[2]; 928 __be32 port; 929 } __packed port_change; 930 struct { 931 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 932 u32 reserved; 933 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 934 } __packed comm_channel_arm; 935 struct { 936 u8 port; 937 u8 reserved[3]; 938 __be64 mac; 939 } __packed mac_update; 940 struct { 941 __be32 slave_id; 942 } __packed flr_event; 943 struct { 944 __be16 current_temperature; 945 __be16 warning_threshold; 946 } __packed warming; 947 struct { 948 u8 reserved[3]; 949 u8 port; 950 union { 951 struct { 952 __be16 mstr_sm_lid; 953 __be16 port_lid; 954 __be32 changed_attr; 955 u8 reserved[3]; 956 u8 mstr_sm_sl; 957 __be64 gid_prefix; 958 } __packed port_info; 959 struct { 960 __be32 block_ptr; 961 __be32 tbl_entries_mask; 962 } __packed tbl_change_info; 963 struct { 964 u8 sl2vl_table[8]; 965 } __packed sl2vl_tbl_change_info; 966 } params; 967 } __packed port_mgmt_change; 968 struct { 969 u8 reserved[3]; 970 u8 port; 971 u32 reserved1[5]; 972 } __packed bad_cable; 973 } event; 974 u8 slave_id; 975 u8 reserved3[2]; 976 u8 owner; 977 } __packed; 978 979 struct mlx4_init_port_param { 980 int set_guid0; 981 int set_node_guid; 982 int set_si_guid; 983 u16 mtu; 984 int port_width_cap; 985 u16 vl_cap; 986 u16 max_gid; 987 u16 max_pkey; 988 u64 guid0; 989 u64 node_guid; 990 u64 si_guid; 991 }; 992 993 #define MAD_IFC_DATA_SZ 192 994 /* MAD IFC Mailbox */ 995 struct mlx4_mad_ifc { 996 u8 base_version; 997 u8 mgmt_class; 998 u8 class_version; 999 u8 method; 1000 __be16 status; 1001 __be16 class_specific; 1002 __be64 tid; 1003 __be16 attr_id; 1004 __be16 resv; 1005 __be32 attr_mod; 1006 __be64 mkey; 1007 __be16 dr_slid; 1008 __be16 dr_dlid; 1009 u8 reserved[28]; 1010 u8 data[MAD_IFC_DATA_SZ]; 1011 } __packed; 1012 1013 #define mlx4_foreach_port(port, dev, type) \ 1014 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1015 if ((type) == (dev)->caps.port_mask[(port)]) 1016 1017 #define mlx4_foreach_ib_transport_port(port, dev) \ 1018 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1019 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 1020 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH)) 1021 1022 #define MLX4_INVALID_SLAVE_ID 0xFF 1023 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 1024 1025 void handle_port_mgmt_change_event(struct work_struct *work); 1026 1027 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1028 { 1029 return dev->caps.function; 1030 } 1031 1032 static inline int mlx4_is_master(struct mlx4_dev *dev) 1033 { 1034 return dev->flags & MLX4_FLAG_MASTER; 1035 } 1036 1037 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1038 { 1039 return dev->phys_caps.base_sqpn + 8 + 1040 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1041 } 1042 1043 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1044 { 1045 return (qpn < dev->phys_caps.base_sqpn + 8 + 1046 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1047 qpn >= dev->phys_caps.base_sqpn) || 1048 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1049 } 1050 1051 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1052 { 1053 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1054 1055 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1056 return 1; 1057 1058 return 0; 1059 } 1060 1061 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1062 { 1063 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1064 } 1065 1066 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1067 { 1068 return dev->flags & MLX4_FLAG_SLAVE; 1069 } 1070 1071 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1072 { 1073 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1074 } 1075 1076 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1077 struct mlx4_buf *buf); 1078 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1079 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1080 { 1081 if (buf->nbufs == 1) 1082 return buf->direct.buf + offset; 1083 else 1084 return buf->page_list[offset >> PAGE_SHIFT].buf + 1085 (offset & (PAGE_SIZE - 1)); 1086 } 1087 1088 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1089 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1090 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1091 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1092 1093 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1094 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1095 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1096 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1097 1098 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1099 struct mlx4_mtt *mtt); 1100 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1101 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1102 1103 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1104 int npages, int page_shift, struct mlx4_mr *mr); 1105 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1106 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1107 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1108 struct mlx4_mw *mw); 1109 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1110 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1111 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1112 int start_index, int npages, u64 *page_list); 1113 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1114 struct mlx4_buf *buf); 1115 1116 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 1117 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1118 1119 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1120 int size); 1121 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1122 int size); 1123 1124 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1125 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1126 unsigned vector, int collapsed, int timestamp_en); 1127 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1128 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1129 int *base, u8 flags); 1130 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1131 1132 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1133 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1134 1135 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1136 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1137 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1138 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1139 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1140 1141 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1142 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1143 1144 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1145 int block_mcast_loopback, enum mlx4_protocol prot); 1146 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1147 enum mlx4_protocol prot); 1148 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1149 u8 port, int block_mcast_loopback, 1150 enum mlx4_protocol protocol, u64 *reg_id); 1151 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1152 enum mlx4_protocol protocol, u64 reg_id); 1153 1154 enum { 1155 MLX4_DOMAIN_UVERBS = 0x1000, 1156 MLX4_DOMAIN_ETHTOOL = 0x2000, 1157 MLX4_DOMAIN_RFS = 0x3000, 1158 MLX4_DOMAIN_NIC = 0x5000, 1159 }; 1160 1161 enum mlx4_net_trans_rule_id { 1162 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1163 MLX4_NET_TRANS_RULE_ID_IB, 1164 MLX4_NET_TRANS_RULE_ID_IPV6, 1165 MLX4_NET_TRANS_RULE_ID_IPV4, 1166 MLX4_NET_TRANS_RULE_ID_TCP, 1167 MLX4_NET_TRANS_RULE_ID_UDP, 1168 MLX4_NET_TRANS_RULE_ID_VXLAN, 1169 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1170 }; 1171 1172 extern const u16 __sw_id_hw[]; 1173 1174 static inline int map_hw_to_sw_id(u16 header_id) 1175 { 1176 1177 int i; 1178 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1179 if (header_id == __sw_id_hw[i]) 1180 return i; 1181 } 1182 return -EINVAL; 1183 } 1184 1185 enum mlx4_net_trans_promisc_mode { 1186 MLX4_FS_REGULAR = 1, 1187 MLX4_FS_ALL_DEFAULT, 1188 MLX4_FS_MC_DEFAULT, 1189 MLX4_FS_MIRROR_RX_PORT, 1190 MLX4_FS_MIRROR_SX_PORT, 1191 MLX4_FS_UC_SNIFFER, 1192 MLX4_FS_MC_SNIFFER, 1193 MLX4_FS_MODE_NUM, /* should be last */ 1194 }; 1195 1196 struct mlx4_spec_eth { 1197 u8 dst_mac[ETH_ALEN]; 1198 u8 dst_mac_msk[ETH_ALEN]; 1199 u8 src_mac[ETH_ALEN]; 1200 u8 src_mac_msk[ETH_ALEN]; 1201 u8 ether_type_enable; 1202 __be16 ether_type; 1203 __be16 vlan_id_msk; 1204 __be16 vlan_id; 1205 }; 1206 1207 struct mlx4_spec_tcp_udp { 1208 __be16 dst_port; 1209 __be16 dst_port_msk; 1210 __be16 src_port; 1211 __be16 src_port_msk; 1212 }; 1213 1214 struct mlx4_spec_ipv4 { 1215 __be32 dst_ip; 1216 __be32 dst_ip_msk; 1217 __be32 src_ip; 1218 __be32 src_ip_msk; 1219 }; 1220 1221 struct mlx4_spec_ib { 1222 __be32 l3_qpn; 1223 __be32 qpn_msk; 1224 u8 dst_gid[16]; 1225 u8 dst_gid_msk[16]; 1226 }; 1227 1228 struct mlx4_spec_vxlan { 1229 __be32 vni; 1230 __be32 vni_mask; 1231 1232 }; 1233 1234 struct mlx4_spec_list { 1235 struct list_head list; 1236 enum mlx4_net_trans_rule_id id; 1237 union { 1238 struct mlx4_spec_eth eth; 1239 struct mlx4_spec_ib ib; 1240 struct mlx4_spec_ipv4 ipv4; 1241 struct mlx4_spec_tcp_udp tcp_udp; 1242 struct mlx4_spec_vxlan vxlan; 1243 }; 1244 }; 1245 1246 enum mlx4_net_trans_hw_rule_queue { 1247 MLX4_NET_TRANS_Q_FIFO, 1248 MLX4_NET_TRANS_Q_LIFO, 1249 }; 1250 1251 struct mlx4_net_trans_rule { 1252 struct list_head list; 1253 enum mlx4_net_trans_hw_rule_queue queue_mode; 1254 bool exclusive; 1255 bool allow_loopback; 1256 enum mlx4_net_trans_promisc_mode promisc_mode; 1257 u8 port; 1258 u16 priority; 1259 u32 qpn; 1260 }; 1261 1262 struct mlx4_net_trans_rule_hw_ctrl { 1263 __be16 prio; 1264 u8 type; 1265 u8 flags; 1266 u8 rsvd1; 1267 u8 funcid; 1268 u8 vep; 1269 u8 port; 1270 __be32 qpn; 1271 __be32 rsvd2; 1272 }; 1273 1274 struct mlx4_net_trans_rule_hw_ib { 1275 u8 size; 1276 u8 rsvd1; 1277 __be16 id; 1278 u32 rsvd2; 1279 __be32 l3_qpn; 1280 __be32 qpn_mask; 1281 u8 dst_gid[16]; 1282 u8 dst_gid_msk[16]; 1283 } __packed; 1284 1285 struct mlx4_net_trans_rule_hw_eth { 1286 u8 size; 1287 u8 rsvd; 1288 __be16 id; 1289 u8 rsvd1[6]; 1290 u8 dst_mac[6]; 1291 u16 rsvd2; 1292 u8 dst_mac_msk[6]; 1293 u16 rsvd3; 1294 u8 src_mac[6]; 1295 u16 rsvd4; 1296 u8 src_mac_msk[6]; 1297 u8 rsvd5; 1298 u8 ether_type_enable; 1299 __be16 ether_type; 1300 __be16 vlan_tag_msk; 1301 __be16 vlan_tag; 1302 } __packed; 1303 1304 struct mlx4_net_trans_rule_hw_tcp_udp { 1305 u8 size; 1306 u8 rsvd; 1307 __be16 id; 1308 __be16 rsvd1[3]; 1309 __be16 dst_port; 1310 __be16 rsvd2; 1311 __be16 dst_port_msk; 1312 __be16 rsvd3; 1313 __be16 src_port; 1314 __be16 rsvd4; 1315 __be16 src_port_msk; 1316 } __packed; 1317 1318 struct mlx4_net_trans_rule_hw_ipv4 { 1319 u8 size; 1320 u8 rsvd; 1321 __be16 id; 1322 __be32 rsvd1; 1323 __be32 dst_ip; 1324 __be32 dst_ip_msk; 1325 __be32 src_ip; 1326 __be32 src_ip_msk; 1327 } __packed; 1328 1329 struct mlx4_net_trans_rule_hw_vxlan { 1330 u8 size; 1331 u8 rsvd; 1332 __be16 id; 1333 __be32 rsvd1; 1334 __be32 vni; 1335 __be32 vni_mask; 1336 } __packed; 1337 1338 struct _rule_hw { 1339 union { 1340 struct { 1341 u8 size; 1342 u8 rsvd; 1343 __be16 id; 1344 }; 1345 struct mlx4_net_trans_rule_hw_eth eth; 1346 struct mlx4_net_trans_rule_hw_ib ib; 1347 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1348 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1349 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1350 }; 1351 }; 1352 1353 enum { 1354 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1355 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1356 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1357 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1358 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1359 }; 1360 1361 enum { 1362 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2, 1363 }; 1364 1365 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1366 enum mlx4_net_trans_promisc_mode mode); 1367 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1368 enum mlx4_net_trans_promisc_mode mode); 1369 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1370 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1371 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1372 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1373 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1374 1375 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1376 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1377 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1378 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1379 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1380 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1381 int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac); 1382 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu); 1383 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1384 u8 promisc); 1385 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1386 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1387 u8 ignore_fcs_value); 1388 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1389 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1390 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1391 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 1392 bool *vlan_offload_disabled); 1393 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 1394 struct _rule_hw *eth_header); 1395 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1396 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1397 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1398 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1399 1400 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1401 int npages, u64 iova, u32 *lkey, u32 *rkey); 1402 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1403 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1404 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1405 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1406 u32 *lkey, u32 *rkey); 1407 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1408 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1409 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector); 1410 int mlx4_test_async(struct mlx4_dev *dev); 1411 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 1412 const u32 offset[], u32 value[], 1413 size_t array_len, u8 port); 1414 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1415 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1416 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1417 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1418 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1419 1420 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1421 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1422 1423 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1424 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1425 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1426 1427 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1428 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1429 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1430 1431 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1432 int port); 1433 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1434 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1435 int mlx4_flow_attach(struct mlx4_dev *dev, 1436 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1437 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1438 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1439 enum mlx4_net_trans_promisc_mode flow_type); 1440 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1441 enum mlx4_net_trans_rule_id id); 1442 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1443 1444 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1445 int port, int qpn, u16 prio, u64 *reg_id); 1446 1447 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1448 int i, int val); 1449 1450 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1451 1452 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1453 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1454 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1455 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1456 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1457 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1458 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1459 1460 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1461 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1462 1463 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1464 int *slave_id); 1465 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1466 u8 *gid); 1467 1468 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1469 u32 max_range_qpn); 1470 1471 u64 mlx4_read_clock(struct mlx4_dev *dev); 1472 1473 struct mlx4_active_ports { 1474 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1475 }; 1476 /* Returns a bitmap of the physical ports which are assigned to slave */ 1477 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1478 1479 /* Returns the physical port that represents the virtual port of the slave, */ 1480 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1481 /* mapping is returned. */ 1482 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1483 1484 struct mlx4_slaves_pport { 1485 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1486 }; 1487 /* Returns a bitmap of all slaves that are assigned to port. */ 1488 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1489 int port); 1490 1491 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1492 /* the ports that are set in crit_ports. */ 1493 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1494 struct mlx4_dev *dev, 1495 const struct mlx4_active_ports *crit_ports); 1496 1497 /* Returns the slave's virtual port that represents the physical port. */ 1498 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1499 1500 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1501 1502 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1503 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1504 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1505 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1506 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1507 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1508 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1509 int enable); 1510 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1511 struct mlx4_mpt_entry ***mpt_entry); 1512 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1513 struct mlx4_mpt_entry **mpt_entry); 1514 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1515 u32 pdn); 1516 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1517 struct mlx4_mpt_entry *mpt_entry, 1518 u32 access); 1519 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1520 struct mlx4_mpt_entry **mpt_entry); 1521 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1522 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1523 u64 iova, u64 size, int npages, 1524 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1525 1526 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1527 u16 offset, u16 size, u8 *data); 1528 int mlx4_max_tc(struct mlx4_dev *dev); 1529 1530 /* Returns true if running in low memory profile (kdump kernel) */ 1531 static inline bool mlx4_low_memory_profile(void) 1532 { 1533 return is_kdump_kernel(); 1534 } 1535 1536 /* ACCESS REG commands */ 1537 enum mlx4_access_reg_method { 1538 MLX4_ACCESS_REG_QUERY = 0x1, 1539 MLX4_ACCESS_REG_WRITE = 0x2, 1540 }; 1541 1542 /* ACCESS PTYS Reg command */ 1543 enum mlx4_ptys_proto { 1544 MLX4_PTYS_IB = 1<<0, 1545 MLX4_PTYS_EN = 1<<2, 1546 }; 1547 1548 enum mlx4_ptys_flags { 1549 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5, 1550 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6, 1551 }; 1552 1553 struct mlx4_ptys_reg { 1554 u8 flags; 1555 u8 local_port; 1556 u8 resrvd2; 1557 u8 proto_mask; 1558 __be32 resrvd3[2]; 1559 __be32 eth_proto_cap; 1560 __be16 ib_width_cap; 1561 __be16 ib_speed_cap; 1562 __be32 resrvd4; 1563 __be32 eth_proto_admin; 1564 __be16 ib_width_admin; 1565 __be16 ib_speed_admin; 1566 __be32 resrvd5; 1567 __be32 eth_proto_oper; 1568 __be16 ib_width_oper; 1569 __be16 ib_speed_oper; 1570 __be32 resrvd6; 1571 __be32 eth_proto_lp_adv; 1572 } __packed; 1573 1574 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1575 enum mlx4_access_reg_method method, 1576 struct mlx4_ptys_reg *ptys_reg); 1577 1578 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1579 struct mlx4_clock_params *params); 1580 1581 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1582 { 1583 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1584 } 1585 1586 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1587 { 1588 /* The first 128 UARs are used for EQ doorbells */ 1589 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1590 } 1591 #endif /* MLX4_DEVICE_H */ 1592