1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 42 #include <linux/atomic.h> 43 44 #include <linux/clocksource.h> 45 46 #define MAX_MSIX_P_PORT 17 47 #define MAX_MSIX 64 48 #define MSIX_LEGACY_SZ 4 49 #define MIN_MSIX_P_PORT 5 50 51 #define MLX4_ROCE_MAX_GIDS 128 52 #define MLX4_ROCE_PF_GIDS 16 53 54 enum { 55 MLX4_FLAG_MSI_X = 1 << 0, 56 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 57 MLX4_FLAG_MASTER = 1 << 2, 58 MLX4_FLAG_SLAVE = 1 << 3, 59 MLX4_FLAG_SRIOV = 1 << 4, 60 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 61 }; 62 63 enum { 64 MLX4_PORT_CAP_IS_SM = 1 << 1, 65 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 66 }; 67 68 enum { 69 MLX4_MAX_PORTS = 2, 70 MLX4_MAX_PORT_PKEYS = 128 71 }; 72 73 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 74 * These qkeys must not be allowed for general use. This is a 64k range, 75 * and to test for violation, we use the mask (protect against future chg). 76 */ 77 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 78 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 79 80 enum { 81 MLX4_BOARD_ID_LEN = 64 82 }; 83 84 enum { 85 MLX4_MAX_NUM_PF = 16, 86 MLX4_MAX_NUM_VF = 64, 87 MLX4_MAX_NUM_VF_P_PORT = 64, 88 MLX4_MFUNC_MAX = 80, 89 MLX4_MAX_EQ_NUM = 1024, 90 MLX4_MFUNC_EQ_NUM = 4, 91 MLX4_MFUNC_MAX_EQES = 8, 92 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 93 }; 94 95 /* Driver supports 3 diffrent device methods to manage traffic steering: 96 * -device managed - High level API for ib and eth flow steering. FW is 97 * managing flow steering tables. 98 * - B0 steering mode - Common low level API for ib and (if supported) eth. 99 * - A0 steering mode - Limited low level API for eth. In case of IB, 100 * B0 mode is in use. 101 */ 102 enum { 103 MLX4_STEERING_MODE_A0, 104 MLX4_STEERING_MODE_B0, 105 MLX4_STEERING_MODE_DEVICE_MANAGED 106 }; 107 108 static inline const char *mlx4_steering_mode_str(int steering_mode) 109 { 110 switch (steering_mode) { 111 case MLX4_STEERING_MODE_A0: 112 return "A0 steering"; 113 114 case MLX4_STEERING_MODE_B0: 115 return "B0 steering"; 116 117 case MLX4_STEERING_MODE_DEVICE_MANAGED: 118 return "Device managed flow steering"; 119 120 default: 121 return "Unrecognize steering mode"; 122 } 123 } 124 125 enum { 126 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 127 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 128 }; 129 130 enum { 131 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 132 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 133 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 134 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 135 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 136 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 137 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 138 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 139 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 140 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 141 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 142 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 143 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 144 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 145 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 146 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 147 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 148 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 149 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 150 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 151 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 152 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 153 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 154 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 155 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 156 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 157 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 158 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 159 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 160 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 161 }; 162 163 enum { 164 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 165 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 166 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 167 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 168 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 169 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 170 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 171 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 172 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 173 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 174 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 175 }; 176 177 enum { 178 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 179 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 180 }; 181 182 enum { 183 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 184 }; 185 186 enum { 187 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 188 }; 189 190 191 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 192 193 enum { 194 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 195 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 196 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 197 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 198 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 199 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 200 }; 201 202 enum mlx4_event { 203 MLX4_EVENT_TYPE_COMP = 0x00, 204 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 205 MLX4_EVENT_TYPE_COMM_EST = 0x02, 206 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 207 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 208 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 209 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 210 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 211 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 212 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 213 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 214 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 215 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 216 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 217 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 218 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 219 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 220 MLX4_EVENT_TYPE_CMD = 0x0a, 221 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 222 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 223 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 224 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 225 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 226 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 227 MLX4_EVENT_TYPE_NONE = 0xff, 228 }; 229 230 enum { 231 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 232 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 233 }; 234 235 enum { 236 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 237 }; 238 239 enum slave_port_state { 240 SLAVE_PORT_DOWN = 0, 241 SLAVE_PENDING_UP, 242 SLAVE_PORT_UP, 243 }; 244 245 enum slave_port_gen_event { 246 SLAVE_PORT_GEN_EVENT_DOWN = 0, 247 SLAVE_PORT_GEN_EVENT_UP, 248 SLAVE_PORT_GEN_EVENT_NONE, 249 }; 250 251 enum slave_port_state_event { 252 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 253 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 254 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 255 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 256 }; 257 258 enum { 259 MLX4_PERM_LOCAL_READ = 1 << 10, 260 MLX4_PERM_LOCAL_WRITE = 1 << 11, 261 MLX4_PERM_REMOTE_READ = 1 << 12, 262 MLX4_PERM_REMOTE_WRITE = 1 << 13, 263 MLX4_PERM_ATOMIC = 1 << 14, 264 MLX4_PERM_BIND_MW = 1 << 15, 265 }; 266 267 enum { 268 MLX4_OPCODE_NOP = 0x00, 269 MLX4_OPCODE_SEND_INVAL = 0x01, 270 MLX4_OPCODE_RDMA_WRITE = 0x08, 271 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 272 MLX4_OPCODE_SEND = 0x0a, 273 MLX4_OPCODE_SEND_IMM = 0x0b, 274 MLX4_OPCODE_LSO = 0x0e, 275 MLX4_OPCODE_RDMA_READ = 0x10, 276 MLX4_OPCODE_ATOMIC_CS = 0x11, 277 MLX4_OPCODE_ATOMIC_FA = 0x12, 278 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 279 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 280 MLX4_OPCODE_BIND_MW = 0x18, 281 MLX4_OPCODE_FMR = 0x19, 282 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 283 MLX4_OPCODE_CONFIG_CMD = 0x1f, 284 285 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 286 MLX4_RECV_OPCODE_SEND = 0x01, 287 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 288 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 289 290 MLX4_CQE_OPCODE_ERROR = 0x1e, 291 MLX4_CQE_OPCODE_RESIZE = 0x16, 292 }; 293 294 enum { 295 MLX4_STAT_RATE_OFFSET = 5 296 }; 297 298 enum mlx4_protocol { 299 MLX4_PROT_IB_IPV6 = 0, 300 MLX4_PROT_ETH, 301 MLX4_PROT_IB_IPV4, 302 MLX4_PROT_FCOE 303 }; 304 305 enum { 306 MLX4_MTT_FLAG_PRESENT = 1 307 }; 308 309 enum mlx4_qp_region { 310 MLX4_QP_REGION_FW = 0, 311 MLX4_QP_REGION_ETH_ADDR, 312 MLX4_QP_REGION_FC_ADDR, 313 MLX4_QP_REGION_FC_EXCH, 314 MLX4_NUM_QP_REGION 315 }; 316 317 enum mlx4_port_type { 318 MLX4_PORT_TYPE_NONE = 0, 319 MLX4_PORT_TYPE_IB = 1, 320 MLX4_PORT_TYPE_ETH = 2, 321 MLX4_PORT_TYPE_AUTO = 3 322 }; 323 324 enum mlx4_special_vlan_idx { 325 MLX4_NO_VLAN_IDX = 0, 326 MLX4_VLAN_MISS_IDX, 327 MLX4_VLAN_REGULAR 328 }; 329 330 enum mlx4_steer_type { 331 MLX4_MC_STEER = 0, 332 MLX4_UC_STEER, 333 MLX4_NUM_STEERS 334 }; 335 336 enum { 337 MLX4_NUM_FEXCH = 64 * 1024, 338 }; 339 340 enum { 341 MLX4_MAX_FAST_REG_PAGES = 511, 342 }; 343 344 enum { 345 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 346 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 347 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 348 }; 349 350 /* Port mgmt change event handling */ 351 enum { 352 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 353 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 354 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 355 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 356 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 357 }; 358 359 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 360 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 361 362 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 363 { 364 return (major << 32) | (minor << 16) | subminor; 365 } 366 367 struct mlx4_phys_caps { 368 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 369 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 370 u32 num_phys_eqs; 371 u32 base_sqpn; 372 u32 base_proxy_sqpn; 373 u32 base_tunnel_sqpn; 374 }; 375 376 struct mlx4_caps { 377 u64 fw_ver; 378 u32 function; 379 int num_ports; 380 int vl_cap[MLX4_MAX_PORTS + 1]; 381 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 382 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 383 u64 def_mac[MLX4_MAX_PORTS + 1]; 384 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 385 int gid_table_len[MLX4_MAX_PORTS + 1]; 386 int pkey_table_len[MLX4_MAX_PORTS + 1]; 387 int trans_type[MLX4_MAX_PORTS + 1]; 388 int vendor_oui[MLX4_MAX_PORTS + 1]; 389 int wavelength[MLX4_MAX_PORTS + 1]; 390 u64 trans_code[MLX4_MAX_PORTS + 1]; 391 int local_ca_ack_delay; 392 int num_uars; 393 u32 uar_page_size; 394 int bf_reg_size; 395 int bf_regs_per_page; 396 int max_sq_sg; 397 int max_rq_sg; 398 int num_qps; 399 int max_wqes; 400 int max_sq_desc_sz; 401 int max_rq_desc_sz; 402 int max_qp_init_rdma; 403 int max_qp_dest_rdma; 404 u32 *qp0_proxy; 405 u32 *qp1_proxy; 406 u32 *qp0_tunnel; 407 u32 *qp1_tunnel; 408 int num_srqs; 409 int max_srq_wqes; 410 int max_srq_sge; 411 int reserved_srqs; 412 int num_cqs; 413 int max_cqes; 414 int reserved_cqs; 415 int num_eqs; 416 int reserved_eqs; 417 int num_comp_vectors; 418 int comp_pool; 419 int num_mpts; 420 int max_fmr_maps; 421 int num_mtts; 422 int fmr_reserved_mtts; 423 int reserved_mtts; 424 int reserved_mrws; 425 int reserved_uars; 426 int num_mgms; 427 int num_amgms; 428 int reserved_mcgs; 429 int num_qp_per_mgm; 430 int steering_mode; 431 int fs_log_max_ucast_qp_range_size; 432 int num_pds; 433 int reserved_pds; 434 int max_xrcds; 435 int reserved_xrcds; 436 int mtt_entry_sz; 437 u32 max_msg_sz; 438 u32 page_size_cap; 439 u64 flags; 440 u64 flags2; 441 u32 bmme_flags; 442 u32 reserved_lkey; 443 u16 stat_rate_support; 444 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 445 int max_gso_sz; 446 int max_rss_tbl_sz; 447 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 448 int reserved_qps; 449 int reserved_qps_base[MLX4_NUM_QP_REGION]; 450 int log_num_macs; 451 int log_num_vlans; 452 int log_num_prios; 453 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 454 u8 supported_type[MLX4_MAX_PORTS + 1]; 455 u8 suggested_type[MLX4_MAX_PORTS + 1]; 456 u8 default_sense[MLX4_MAX_PORTS + 1]; 457 u32 port_mask[MLX4_MAX_PORTS + 1]; 458 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 459 u32 max_counters; 460 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 461 u16 sqp_demux; 462 u32 eqe_size; 463 u32 cqe_size; 464 u8 eqe_factor; 465 u32 userspace_caps; /* userspace must be aware of these */ 466 u32 function_caps; /* VFs must be aware of these */ 467 u16 hca_core_clock; 468 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 469 int tunnel_offload_mode; 470 }; 471 472 struct mlx4_buf_list { 473 void *buf; 474 dma_addr_t map; 475 }; 476 477 struct mlx4_buf { 478 struct mlx4_buf_list direct; 479 struct mlx4_buf_list *page_list; 480 int nbufs; 481 int npages; 482 int page_shift; 483 }; 484 485 struct mlx4_mtt { 486 u32 offset; 487 int order; 488 int page_shift; 489 }; 490 491 enum { 492 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 493 }; 494 495 struct mlx4_db_pgdir { 496 struct list_head list; 497 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 498 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 499 unsigned long *bits[2]; 500 __be32 *db_page; 501 dma_addr_t db_dma; 502 }; 503 504 struct mlx4_ib_user_db_page; 505 506 struct mlx4_db { 507 __be32 *db; 508 union { 509 struct mlx4_db_pgdir *pgdir; 510 struct mlx4_ib_user_db_page *user_page; 511 } u; 512 dma_addr_t dma; 513 int index; 514 int order; 515 }; 516 517 struct mlx4_hwq_resources { 518 struct mlx4_db db; 519 struct mlx4_mtt mtt; 520 struct mlx4_buf buf; 521 }; 522 523 struct mlx4_mr { 524 struct mlx4_mtt mtt; 525 u64 iova; 526 u64 size; 527 u32 key; 528 u32 pd; 529 u32 access; 530 int enabled; 531 }; 532 533 enum mlx4_mw_type { 534 MLX4_MW_TYPE_1 = 1, 535 MLX4_MW_TYPE_2 = 2, 536 }; 537 538 struct mlx4_mw { 539 u32 key; 540 u32 pd; 541 enum mlx4_mw_type type; 542 int enabled; 543 }; 544 545 struct mlx4_fmr { 546 struct mlx4_mr mr; 547 struct mlx4_mpt_entry *mpt; 548 __be64 *mtts; 549 dma_addr_t dma_handle; 550 int max_pages; 551 int max_maps; 552 int maps; 553 u8 page_shift; 554 }; 555 556 struct mlx4_uar { 557 unsigned long pfn; 558 int index; 559 struct list_head bf_list; 560 unsigned free_bf_bmap; 561 void __iomem *map; 562 void __iomem *bf_map; 563 }; 564 565 struct mlx4_bf { 566 unsigned long offset; 567 int buf_size; 568 struct mlx4_uar *uar; 569 void __iomem *reg; 570 }; 571 572 struct mlx4_cq { 573 void (*comp) (struct mlx4_cq *); 574 void (*event) (struct mlx4_cq *, enum mlx4_event); 575 576 struct mlx4_uar *uar; 577 578 u32 cons_index; 579 580 __be32 *set_ci_db; 581 __be32 *arm_db; 582 int arm_sn; 583 584 int cqn; 585 unsigned vector; 586 587 atomic_t refcount; 588 struct completion free; 589 }; 590 591 struct mlx4_qp { 592 void (*event) (struct mlx4_qp *, enum mlx4_event); 593 594 int qpn; 595 596 atomic_t refcount; 597 struct completion free; 598 }; 599 600 struct mlx4_srq { 601 void (*event) (struct mlx4_srq *, enum mlx4_event); 602 603 int srqn; 604 int max; 605 int max_gs; 606 int wqe_shift; 607 608 atomic_t refcount; 609 struct completion free; 610 }; 611 612 struct mlx4_av { 613 __be32 port_pd; 614 u8 reserved1; 615 u8 g_slid; 616 __be16 dlid; 617 u8 reserved2; 618 u8 gid_index; 619 u8 stat_rate; 620 u8 hop_limit; 621 __be32 sl_tclass_flowlabel; 622 u8 dgid[16]; 623 }; 624 625 struct mlx4_eth_av { 626 __be32 port_pd; 627 u8 reserved1; 628 u8 smac_idx; 629 u16 reserved2; 630 u8 reserved3; 631 u8 gid_index; 632 u8 stat_rate; 633 u8 hop_limit; 634 __be32 sl_tclass_flowlabel; 635 u8 dgid[16]; 636 u8 s_mac[6]; 637 u8 reserved4[2]; 638 __be16 vlan; 639 u8 mac[ETH_ALEN]; 640 }; 641 642 union mlx4_ext_av { 643 struct mlx4_av ib; 644 struct mlx4_eth_av eth; 645 }; 646 647 struct mlx4_counter { 648 u8 reserved1[3]; 649 u8 counter_mode; 650 __be32 num_ifc; 651 u32 reserved2[2]; 652 __be64 rx_frames; 653 __be64 rx_bytes; 654 __be64 tx_frames; 655 __be64 tx_bytes; 656 }; 657 658 struct mlx4_quotas { 659 int qp; 660 int cq; 661 int srq; 662 int mpt; 663 int mtt; 664 int counter; 665 int xrcd; 666 }; 667 668 struct mlx4_vf_dev { 669 u8 min_port; 670 u8 n_ports; 671 }; 672 673 struct mlx4_dev { 674 struct pci_dev *pdev; 675 unsigned long flags; 676 unsigned long num_slaves; 677 struct mlx4_caps caps; 678 struct mlx4_phys_caps phys_caps; 679 struct mlx4_quotas quotas; 680 struct radix_tree_root qp_table_tree; 681 u8 rev_id; 682 char board_id[MLX4_BOARD_ID_LEN]; 683 int num_vfs; 684 int numa_node; 685 int oper_log_mgm_entry_size; 686 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 687 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 688 struct mlx4_vf_dev *dev_vfs; 689 }; 690 691 struct mlx4_eqe { 692 u8 reserved1; 693 u8 type; 694 u8 reserved2; 695 u8 subtype; 696 union { 697 u32 raw[6]; 698 struct { 699 __be32 cqn; 700 } __packed comp; 701 struct { 702 u16 reserved1; 703 __be16 token; 704 u32 reserved2; 705 u8 reserved3[3]; 706 u8 status; 707 __be64 out_param; 708 } __packed cmd; 709 struct { 710 __be32 qpn; 711 } __packed qp; 712 struct { 713 __be32 srqn; 714 } __packed srq; 715 struct { 716 __be32 cqn; 717 u32 reserved1; 718 u8 reserved2[3]; 719 u8 syndrome; 720 } __packed cq_err; 721 struct { 722 u32 reserved1[2]; 723 __be32 port; 724 } __packed port_change; 725 struct { 726 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 727 u32 reserved; 728 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 729 } __packed comm_channel_arm; 730 struct { 731 u8 port; 732 u8 reserved[3]; 733 __be64 mac; 734 } __packed mac_update; 735 struct { 736 __be32 slave_id; 737 } __packed flr_event; 738 struct { 739 __be16 current_temperature; 740 __be16 warning_threshold; 741 } __packed warming; 742 struct { 743 u8 reserved[3]; 744 u8 port; 745 union { 746 struct { 747 __be16 mstr_sm_lid; 748 __be16 port_lid; 749 __be32 changed_attr; 750 u8 reserved[3]; 751 u8 mstr_sm_sl; 752 __be64 gid_prefix; 753 } __packed port_info; 754 struct { 755 __be32 block_ptr; 756 __be32 tbl_entries_mask; 757 } __packed tbl_change_info; 758 } params; 759 } __packed port_mgmt_change; 760 } event; 761 u8 slave_id; 762 u8 reserved3[2]; 763 u8 owner; 764 } __packed; 765 766 struct mlx4_init_port_param { 767 int set_guid0; 768 int set_node_guid; 769 int set_si_guid; 770 u16 mtu; 771 int port_width_cap; 772 u16 vl_cap; 773 u16 max_gid; 774 u16 max_pkey; 775 u64 guid0; 776 u64 node_guid; 777 u64 si_guid; 778 }; 779 780 #define mlx4_foreach_port(port, dev, type) \ 781 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 782 if ((type) == (dev)->caps.port_mask[(port)]) 783 784 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 785 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 786 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 787 788 #define mlx4_foreach_ib_transport_port(port, dev) \ 789 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 790 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 791 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 792 793 #define MLX4_INVALID_SLAVE_ID 0xFF 794 795 void handle_port_mgmt_change_event(struct work_struct *work); 796 797 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 798 { 799 return dev->caps.function; 800 } 801 802 static inline int mlx4_is_master(struct mlx4_dev *dev) 803 { 804 return dev->flags & MLX4_FLAG_MASTER; 805 } 806 807 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 808 { 809 return dev->phys_caps.base_sqpn + 8 + 810 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 811 } 812 813 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 814 { 815 return (qpn < dev->phys_caps.base_sqpn + 8 + 816 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 817 } 818 819 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 820 { 821 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 822 823 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 824 return 1; 825 826 return 0; 827 } 828 829 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 830 { 831 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 832 } 833 834 static inline int mlx4_is_slave(struct mlx4_dev *dev) 835 { 836 return dev->flags & MLX4_FLAG_SLAVE; 837 } 838 839 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 840 struct mlx4_buf *buf); 841 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 842 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 843 { 844 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 845 return buf->direct.buf + offset; 846 else 847 return buf->page_list[offset >> PAGE_SHIFT].buf + 848 (offset & (PAGE_SIZE - 1)); 849 } 850 851 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 852 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 853 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 854 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 855 856 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 857 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 858 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 859 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 860 861 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 862 struct mlx4_mtt *mtt); 863 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 864 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 865 866 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 867 int npages, int page_shift, struct mlx4_mr *mr); 868 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 869 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 870 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 871 struct mlx4_mw *mw); 872 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 873 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 874 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 875 int start_index, int npages, u64 *page_list); 876 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 877 struct mlx4_buf *buf); 878 879 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 880 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 881 882 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 883 int size, int max_direct); 884 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 885 int size); 886 887 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 888 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 889 unsigned vector, int collapsed, int timestamp_en); 890 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 891 892 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 893 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 894 895 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 896 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 897 898 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 899 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 900 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 901 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 902 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 903 904 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 905 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 906 907 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 908 int block_mcast_loopback, enum mlx4_protocol prot); 909 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 910 enum mlx4_protocol prot); 911 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 912 u8 port, int block_mcast_loopback, 913 enum mlx4_protocol protocol, u64 *reg_id); 914 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 915 enum mlx4_protocol protocol, u64 reg_id); 916 917 enum { 918 MLX4_DOMAIN_UVERBS = 0x1000, 919 MLX4_DOMAIN_ETHTOOL = 0x2000, 920 MLX4_DOMAIN_RFS = 0x3000, 921 MLX4_DOMAIN_NIC = 0x5000, 922 }; 923 924 enum mlx4_net_trans_rule_id { 925 MLX4_NET_TRANS_RULE_ID_ETH = 0, 926 MLX4_NET_TRANS_RULE_ID_IB, 927 MLX4_NET_TRANS_RULE_ID_IPV6, 928 MLX4_NET_TRANS_RULE_ID_IPV4, 929 MLX4_NET_TRANS_RULE_ID_TCP, 930 MLX4_NET_TRANS_RULE_ID_UDP, 931 MLX4_NET_TRANS_RULE_ID_VXLAN, 932 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 933 }; 934 935 extern const u16 __sw_id_hw[]; 936 937 static inline int map_hw_to_sw_id(u16 header_id) 938 { 939 940 int i; 941 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 942 if (header_id == __sw_id_hw[i]) 943 return i; 944 } 945 return -EINVAL; 946 } 947 948 enum mlx4_net_trans_promisc_mode { 949 MLX4_FS_REGULAR = 1, 950 MLX4_FS_ALL_DEFAULT, 951 MLX4_FS_MC_DEFAULT, 952 MLX4_FS_UC_SNIFFER, 953 MLX4_FS_MC_SNIFFER, 954 MLX4_FS_MODE_NUM, /* should be last */ 955 }; 956 957 struct mlx4_spec_eth { 958 u8 dst_mac[ETH_ALEN]; 959 u8 dst_mac_msk[ETH_ALEN]; 960 u8 src_mac[ETH_ALEN]; 961 u8 src_mac_msk[ETH_ALEN]; 962 u8 ether_type_enable; 963 __be16 ether_type; 964 __be16 vlan_id_msk; 965 __be16 vlan_id; 966 }; 967 968 struct mlx4_spec_tcp_udp { 969 __be16 dst_port; 970 __be16 dst_port_msk; 971 __be16 src_port; 972 __be16 src_port_msk; 973 }; 974 975 struct mlx4_spec_ipv4 { 976 __be32 dst_ip; 977 __be32 dst_ip_msk; 978 __be32 src_ip; 979 __be32 src_ip_msk; 980 }; 981 982 struct mlx4_spec_ib { 983 __be32 l3_qpn; 984 __be32 qpn_msk; 985 u8 dst_gid[16]; 986 u8 dst_gid_msk[16]; 987 }; 988 989 struct mlx4_spec_vxlan { 990 __be32 vni; 991 __be32 vni_mask; 992 993 }; 994 995 struct mlx4_spec_list { 996 struct list_head list; 997 enum mlx4_net_trans_rule_id id; 998 union { 999 struct mlx4_spec_eth eth; 1000 struct mlx4_spec_ib ib; 1001 struct mlx4_spec_ipv4 ipv4; 1002 struct mlx4_spec_tcp_udp tcp_udp; 1003 struct mlx4_spec_vxlan vxlan; 1004 }; 1005 }; 1006 1007 enum mlx4_net_trans_hw_rule_queue { 1008 MLX4_NET_TRANS_Q_FIFO, 1009 MLX4_NET_TRANS_Q_LIFO, 1010 }; 1011 1012 struct mlx4_net_trans_rule { 1013 struct list_head list; 1014 enum mlx4_net_trans_hw_rule_queue queue_mode; 1015 bool exclusive; 1016 bool allow_loopback; 1017 enum mlx4_net_trans_promisc_mode promisc_mode; 1018 u8 port; 1019 u16 priority; 1020 u32 qpn; 1021 }; 1022 1023 struct mlx4_net_trans_rule_hw_ctrl { 1024 __be16 prio; 1025 u8 type; 1026 u8 flags; 1027 u8 rsvd1; 1028 u8 funcid; 1029 u8 vep; 1030 u8 port; 1031 __be32 qpn; 1032 __be32 rsvd2; 1033 }; 1034 1035 struct mlx4_net_trans_rule_hw_ib { 1036 u8 size; 1037 u8 rsvd1; 1038 __be16 id; 1039 u32 rsvd2; 1040 __be32 l3_qpn; 1041 __be32 qpn_mask; 1042 u8 dst_gid[16]; 1043 u8 dst_gid_msk[16]; 1044 } __packed; 1045 1046 struct mlx4_net_trans_rule_hw_eth { 1047 u8 size; 1048 u8 rsvd; 1049 __be16 id; 1050 u8 rsvd1[6]; 1051 u8 dst_mac[6]; 1052 u16 rsvd2; 1053 u8 dst_mac_msk[6]; 1054 u16 rsvd3; 1055 u8 src_mac[6]; 1056 u16 rsvd4; 1057 u8 src_mac_msk[6]; 1058 u8 rsvd5; 1059 u8 ether_type_enable; 1060 __be16 ether_type; 1061 __be16 vlan_tag_msk; 1062 __be16 vlan_tag; 1063 } __packed; 1064 1065 struct mlx4_net_trans_rule_hw_tcp_udp { 1066 u8 size; 1067 u8 rsvd; 1068 __be16 id; 1069 __be16 rsvd1[3]; 1070 __be16 dst_port; 1071 __be16 rsvd2; 1072 __be16 dst_port_msk; 1073 __be16 rsvd3; 1074 __be16 src_port; 1075 __be16 rsvd4; 1076 __be16 src_port_msk; 1077 } __packed; 1078 1079 struct mlx4_net_trans_rule_hw_ipv4 { 1080 u8 size; 1081 u8 rsvd; 1082 __be16 id; 1083 __be32 rsvd1; 1084 __be32 dst_ip; 1085 __be32 dst_ip_msk; 1086 __be32 src_ip; 1087 __be32 src_ip_msk; 1088 } __packed; 1089 1090 struct mlx4_net_trans_rule_hw_vxlan { 1091 u8 size; 1092 u8 rsvd; 1093 __be16 id; 1094 __be32 rsvd1; 1095 __be32 vni; 1096 __be32 vni_mask; 1097 } __packed; 1098 1099 struct _rule_hw { 1100 union { 1101 struct { 1102 u8 size; 1103 u8 rsvd; 1104 __be16 id; 1105 }; 1106 struct mlx4_net_trans_rule_hw_eth eth; 1107 struct mlx4_net_trans_rule_hw_ib ib; 1108 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1109 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1110 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1111 }; 1112 }; 1113 1114 enum { 1115 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1116 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1117 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1118 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1119 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1120 }; 1121 1122 1123 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1124 enum mlx4_net_trans_promisc_mode mode); 1125 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1126 enum mlx4_net_trans_promisc_mode mode); 1127 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1128 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1129 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1130 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1131 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1132 1133 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1134 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1135 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1136 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1137 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); 1138 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1139 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1140 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1141 u8 promisc); 1142 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1143 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1144 u8 *pg, u16 *ratelimit); 1145 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1146 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1147 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1148 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1149 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1150 1151 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1152 int npages, u64 iova, u32 *lkey, u32 *rkey); 1153 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1154 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1155 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1156 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1157 u32 *lkey, u32 *rkey); 1158 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1159 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1160 int mlx4_test_interrupts(struct mlx4_dev *dev); 1161 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1162 int *vector); 1163 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1164 1165 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1166 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1167 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1168 1169 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1170 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1171 1172 int mlx4_flow_attach(struct mlx4_dev *dev, 1173 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1174 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1175 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1176 enum mlx4_net_trans_promisc_mode flow_type); 1177 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1178 enum mlx4_net_trans_rule_id id); 1179 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1180 1181 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1182 int i, int val); 1183 1184 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1185 1186 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1187 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1188 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1189 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1190 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1191 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1192 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1193 1194 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1195 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1196 1197 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1198 int *slave_id); 1199 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1200 u8 *gid); 1201 1202 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1203 u32 max_range_qpn); 1204 1205 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1206 1207 struct mlx4_active_ports { 1208 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1209 }; 1210 /* Returns a bitmap of the physical ports which are assigned to slave */ 1211 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1212 1213 /* Returns the physical port that represents the virtual port of the slave, */ 1214 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1215 /* mapping is returned. */ 1216 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1217 1218 struct mlx4_slaves_pport { 1219 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1220 }; 1221 /* Returns a bitmap of all slaves that are assigned to port. */ 1222 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1223 int port); 1224 1225 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1226 /* the ports that are set in crit_ports. */ 1227 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1228 struct mlx4_dev *dev, 1229 const struct mlx4_active_ports *crit_ports); 1230 1231 /* Returns the slave's virtual port that represents the physical port. */ 1232 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1233 1234 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1235 1236 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1237 #endif /* MLX4_DEVICE_H */ 1238