1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/pci.h> 37 #include <linux/completion.h> 38 #include <linux/radix-tree.h> 39 40 #include <linux/atomic.h> 41 42 #define MAX_MSIX_P_PORT 17 43 #define MAX_MSIX 64 44 #define MSIX_LEGACY_SZ 4 45 #define MIN_MSIX_P_PORT 5 46 47 enum { 48 MLX4_FLAG_MSI_X = 1 << 0, 49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 50 }; 51 52 enum { 53 MLX4_MAX_PORTS = 2 54 }; 55 56 enum { 57 MLX4_BOARD_ID_LEN = 64 58 }; 59 60 enum { 61 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 62 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 63 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 64 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 65 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 66 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 67 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 68 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 69 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 70 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 71 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 72 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 73 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 74 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 75 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 76 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 77 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 78 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 79 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 80 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 81 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 82 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 83 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 84 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 85 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48 86 }; 87 88 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 89 90 enum { 91 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 92 }; 93 94 enum { 95 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 96 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 97 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 98 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 99 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 100 }; 101 102 enum mlx4_event { 103 MLX4_EVENT_TYPE_COMP = 0x00, 104 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 105 MLX4_EVENT_TYPE_COMM_EST = 0x02, 106 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 107 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 108 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 109 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 110 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 111 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 112 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 113 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 114 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 115 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 116 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 117 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 118 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 119 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 120 MLX4_EVENT_TYPE_CMD = 0x0a 121 }; 122 123 enum { 124 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 125 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 126 }; 127 128 enum { 129 MLX4_PERM_LOCAL_READ = 1 << 10, 130 MLX4_PERM_LOCAL_WRITE = 1 << 11, 131 MLX4_PERM_REMOTE_READ = 1 << 12, 132 MLX4_PERM_REMOTE_WRITE = 1 << 13, 133 MLX4_PERM_ATOMIC = 1 << 14 134 }; 135 136 enum { 137 MLX4_OPCODE_NOP = 0x00, 138 MLX4_OPCODE_SEND_INVAL = 0x01, 139 MLX4_OPCODE_RDMA_WRITE = 0x08, 140 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 141 MLX4_OPCODE_SEND = 0x0a, 142 MLX4_OPCODE_SEND_IMM = 0x0b, 143 MLX4_OPCODE_LSO = 0x0e, 144 MLX4_OPCODE_RDMA_READ = 0x10, 145 MLX4_OPCODE_ATOMIC_CS = 0x11, 146 MLX4_OPCODE_ATOMIC_FA = 0x12, 147 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 148 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 149 MLX4_OPCODE_BIND_MW = 0x18, 150 MLX4_OPCODE_FMR = 0x19, 151 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 152 MLX4_OPCODE_CONFIG_CMD = 0x1f, 153 154 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 155 MLX4_RECV_OPCODE_SEND = 0x01, 156 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 157 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 158 159 MLX4_CQE_OPCODE_ERROR = 0x1e, 160 MLX4_CQE_OPCODE_RESIZE = 0x16, 161 }; 162 163 enum { 164 MLX4_STAT_RATE_OFFSET = 5 165 }; 166 167 enum mlx4_protocol { 168 MLX4_PROT_IB_IPV6 = 0, 169 MLX4_PROT_ETH, 170 MLX4_PROT_IB_IPV4, 171 MLX4_PROT_FCOE 172 }; 173 174 enum { 175 MLX4_MTT_FLAG_PRESENT = 1 176 }; 177 178 enum mlx4_qp_region { 179 MLX4_QP_REGION_FW = 0, 180 MLX4_QP_REGION_ETH_ADDR, 181 MLX4_QP_REGION_FC_ADDR, 182 MLX4_QP_REGION_FC_EXCH, 183 MLX4_NUM_QP_REGION 184 }; 185 186 enum mlx4_port_type { 187 MLX4_PORT_TYPE_IB = 1, 188 MLX4_PORT_TYPE_ETH = 2, 189 MLX4_PORT_TYPE_AUTO = 3 190 }; 191 192 enum mlx4_special_vlan_idx { 193 MLX4_NO_VLAN_IDX = 0, 194 MLX4_VLAN_MISS_IDX, 195 MLX4_VLAN_REGULAR 196 }; 197 198 enum mlx4_steer_type { 199 MLX4_MC_STEER = 0, 200 MLX4_UC_STEER, 201 MLX4_NUM_STEERS 202 }; 203 204 enum { 205 MLX4_NUM_FEXCH = 64 * 1024, 206 }; 207 208 enum { 209 MLX4_MAX_FAST_REG_PAGES = 511, 210 }; 211 212 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 213 { 214 return (major << 32) | (minor << 16) | subminor; 215 } 216 217 struct mlx4_caps { 218 u64 fw_ver; 219 int num_ports; 220 int vl_cap[MLX4_MAX_PORTS + 1]; 221 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 222 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 223 u64 def_mac[MLX4_MAX_PORTS + 1]; 224 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 225 int gid_table_len[MLX4_MAX_PORTS + 1]; 226 int pkey_table_len[MLX4_MAX_PORTS + 1]; 227 int trans_type[MLX4_MAX_PORTS + 1]; 228 int vendor_oui[MLX4_MAX_PORTS + 1]; 229 int wavelength[MLX4_MAX_PORTS + 1]; 230 u64 trans_code[MLX4_MAX_PORTS + 1]; 231 int local_ca_ack_delay; 232 int num_uars; 233 int bf_reg_size; 234 int bf_regs_per_page; 235 int max_sq_sg; 236 int max_rq_sg; 237 int num_qps; 238 int max_wqes; 239 int max_sq_desc_sz; 240 int max_rq_desc_sz; 241 int max_qp_init_rdma; 242 int max_qp_dest_rdma; 243 int sqp_start; 244 int num_srqs; 245 int max_srq_wqes; 246 int max_srq_sge; 247 int reserved_srqs; 248 int num_cqs; 249 int max_cqes; 250 int reserved_cqs; 251 int num_eqs; 252 int reserved_eqs; 253 int num_comp_vectors; 254 int comp_pool; 255 int num_mpts; 256 int num_mtt_segs; 257 int mtts_per_seg; 258 int fmr_reserved_mtts; 259 int reserved_mtts; 260 int reserved_mrws; 261 int reserved_uars; 262 int num_mgms; 263 int num_amgms; 264 int reserved_mcgs; 265 int num_qp_per_mgm; 266 int num_pds; 267 int reserved_pds; 268 int max_xrcds; 269 int reserved_xrcds; 270 int mtt_entry_sz; 271 u32 max_msg_sz; 272 u32 page_size_cap; 273 u64 flags; 274 u32 bmme_flags; 275 u32 reserved_lkey; 276 u16 stat_rate_support; 277 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 278 int max_gso_sz; 279 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 280 int reserved_qps; 281 int reserved_qps_base[MLX4_NUM_QP_REGION]; 282 int log_num_macs; 283 int log_num_vlans; 284 int log_num_prios; 285 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 286 u8 supported_type[MLX4_MAX_PORTS + 1]; 287 u32 port_mask; 288 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 289 u32 max_counters; 290 u8 ext_port_cap[MLX4_MAX_PORTS + 1]; 291 }; 292 293 struct mlx4_buf_list { 294 void *buf; 295 dma_addr_t map; 296 }; 297 298 struct mlx4_buf { 299 struct mlx4_buf_list direct; 300 struct mlx4_buf_list *page_list; 301 int nbufs; 302 int npages; 303 int page_shift; 304 }; 305 306 struct mlx4_mtt { 307 u32 first_seg; 308 int order; 309 int page_shift; 310 }; 311 312 enum { 313 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 314 }; 315 316 struct mlx4_db_pgdir { 317 struct list_head list; 318 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 319 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 320 unsigned long *bits[2]; 321 __be32 *db_page; 322 dma_addr_t db_dma; 323 }; 324 325 struct mlx4_ib_user_db_page; 326 327 struct mlx4_db { 328 __be32 *db; 329 union { 330 struct mlx4_db_pgdir *pgdir; 331 struct mlx4_ib_user_db_page *user_page; 332 } u; 333 dma_addr_t dma; 334 int index; 335 int order; 336 }; 337 338 struct mlx4_hwq_resources { 339 struct mlx4_db db; 340 struct mlx4_mtt mtt; 341 struct mlx4_buf buf; 342 }; 343 344 struct mlx4_mr { 345 struct mlx4_mtt mtt; 346 u64 iova; 347 u64 size; 348 u32 key; 349 u32 pd; 350 u32 access; 351 int enabled; 352 }; 353 354 struct mlx4_fmr { 355 struct mlx4_mr mr; 356 struct mlx4_mpt_entry *mpt; 357 __be64 *mtts; 358 dma_addr_t dma_handle; 359 int max_pages; 360 int max_maps; 361 int maps; 362 u8 page_shift; 363 }; 364 365 struct mlx4_uar { 366 unsigned long pfn; 367 int index; 368 struct list_head bf_list; 369 unsigned free_bf_bmap; 370 void __iomem *map; 371 void __iomem *bf_map; 372 }; 373 374 struct mlx4_bf { 375 unsigned long offset; 376 int buf_size; 377 struct mlx4_uar *uar; 378 void __iomem *reg; 379 }; 380 381 struct mlx4_cq { 382 void (*comp) (struct mlx4_cq *); 383 void (*event) (struct mlx4_cq *, enum mlx4_event); 384 385 struct mlx4_uar *uar; 386 387 u32 cons_index; 388 389 __be32 *set_ci_db; 390 __be32 *arm_db; 391 int arm_sn; 392 393 int cqn; 394 unsigned vector; 395 396 atomic_t refcount; 397 struct completion free; 398 }; 399 400 struct mlx4_qp { 401 void (*event) (struct mlx4_qp *, enum mlx4_event); 402 403 int qpn; 404 405 atomic_t refcount; 406 struct completion free; 407 }; 408 409 struct mlx4_srq { 410 void (*event) (struct mlx4_srq *, enum mlx4_event); 411 412 int srqn; 413 int max; 414 int max_gs; 415 int wqe_shift; 416 417 atomic_t refcount; 418 struct completion free; 419 }; 420 421 struct mlx4_av { 422 __be32 port_pd; 423 u8 reserved1; 424 u8 g_slid; 425 __be16 dlid; 426 u8 reserved2; 427 u8 gid_index; 428 u8 stat_rate; 429 u8 hop_limit; 430 __be32 sl_tclass_flowlabel; 431 u8 dgid[16]; 432 }; 433 434 struct mlx4_eth_av { 435 __be32 port_pd; 436 u8 reserved1; 437 u8 smac_idx; 438 u16 reserved2; 439 u8 reserved3; 440 u8 gid_index; 441 u8 stat_rate; 442 u8 hop_limit; 443 __be32 sl_tclass_flowlabel; 444 u8 dgid[16]; 445 u32 reserved4[2]; 446 __be16 vlan; 447 u8 mac[6]; 448 }; 449 450 union mlx4_ext_av { 451 struct mlx4_av ib; 452 struct mlx4_eth_av eth; 453 }; 454 455 struct mlx4_counter { 456 u8 reserved1[3]; 457 u8 counter_mode; 458 __be32 num_ifc; 459 u32 reserved2[2]; 460 __be64 rx_frames; 461 __be64 rx_bytes; 462 __be64 tx_frames; 463 __be64 tx_bytes; 464 }; 465 466 struct mlx4_dev { 467 struct pci_dev *pdev; 468 unsigned long flags; 469 struct mlx4_caps caps; 470 struct radix_tree_root qp_table_tree; 471 u8 rev_id; 472 char board_id[MLX4_BOARD_ID_LEN]; 473 }; 474 475 struct mlx4_init_port_param { 476 int set_guid0; 477 int set_node_guid; 478 int set_si_guid; 479 u16 mtu; 480 int port_width_cap; 481 u16 vl_cap; 482 u16 max_gid; 483 u16 max_pkey; 484 u64 guid0; 485 u64 node_guid; 486 u64 si_guid; 487 }; 488 489 #define mlx4_foreach_port(port, dev, type) \ 490 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 491 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ 492 ~(dev)->caps.port_mask) & 1 << ((port) - 1)) 493 494 #define mlx4_foreach_ib_transport_port(port, dev) \ 495 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 496 if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \ 497 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 498 499 500 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 501 struct mlx4_buf *buf); 502 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 503 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 504 { 505 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 506 return buf->direct.buf + offset; 507 else 508 return buf->page_list[offset >> PAGE_SHIFT].buf + 509 (offset & (PAGE_SIZE - 1)); 510 } 511 512 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 513 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 514 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 515 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 516 517 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 518 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 519 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 520 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 521 522 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 523 struct mlx4_mtt *mtt); 524 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 525 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 526 527 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 528 int npages, int page_shift, struct mlx4_mr *mr); 529 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 530 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 531 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 532 int start_index, int npages, u64 *page_list); 533 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 534 struct mlx4_buf *buf); 535 536 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 537 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 538 539 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 540 int size, int max_direct); 541 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 542 int size); 543 544 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 545 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 546 unsigned vector, int collapsed); 547 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 548 549 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 550 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 551 552 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 553 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 554 555 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 556 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 557 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 558 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 559 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 560 561 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 562 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 563 564 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 565 int block_mcast_loopback, enum mlx4_protocol protocol); 566 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 567 enum mlx4_protocol protocol); 568 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 569 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 570 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 571 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 572 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 573 574 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap); 575 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn); 576 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap); 577 578 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 579 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 580 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 581 582 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 583 int npages, u64 iova, u32 *lkey, u32 *rkey); 584 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 585 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 586 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 587 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 588 u32 *lkey, u32 *rkey); 589 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 590 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 591 int mlx4_test_interrupts(struct mlx4_dev *dev); 592 int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector); 593 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 594 595 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 596 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 597 598 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 599 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 600 601 #endif /* MLX4_DEVICE_H */ 602