1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define MAX_MSIX_P_PORT 17 48 #define MAX_MSIX 64 49 #define MIN_MSIX_P_PORT 5 50 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 51 (dev_cap).num_ports * MIN_MSIX_P_PORT) 52 53 #define MLX4_MAX_100M_UNITS_VAL 255 /* 54 * work around: can't set values 55 * greater then this value when 56 * using 100 Mbps units. 57 */ 58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 60 #define MLX4_RATELIMIT_DEFAULT 0x00ff 61 62 #define MLX4_ROCE_MAX_GIDS 128 63 #define MLX4_ROCE_PF_GIDS 16 64 65 enum { 66 MLX4_FLAG_MSI_X = 1 << 0, 67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 68 MLX4_FLAG_MASTER = 1 << 2, 69 MLX4_FLAG_SLAVE = 1 << 3, 70 MLX4_FLAG_SRIOV = 1 << 4, 71 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 72 MLX4_FLAG_BONDED = 1 << 7 73 }; 74 75 enum { 76 MLX4_PORT_CAP_IS_SM = 1 << 1, 77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 78 }; 79 80 enum { 81 MLX4_MAX_PORTS = 2, 82 MLX4_MAX_PORT_PKEYS = 128 83 }; 84 85 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 86 * These qkeys must not be allowed for general use. This is a 64k range, 87 * and to test for violation, we use the mask (protect against future chg). 88 */ 89 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 90 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 91 92 enum { 93 MLX4_BOARD_ID_LEN = 64 94 }; 95 96 enum { 97 MLX4_MAX_NUM_PF = 16, 98 MLX4_MAX_NUM_VF = 126, 99 MLX4_MAX_NUM_VF_P_PORT = 64, 100 MLX4_MFUNC_MAX = 128, 101 MLX4_MAX_EQ_NUM = 1024, 102 MLX4_MFUNC_EQ_NUM = 4, 103 MLX4_MFUNC_MAX_EQES = 8, 104 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 105 }; 106 107 /* Driver supports 3 diffrent device methods to manage traffic steering: 108 * -device managed - High level API for ib and eth flow steering. FW is 109 * managing flow steering tables. 110 * - B0 steering mode - Common low level API for ib and (if supported) eth. 111 * - A0 steering mode - Limited low level API for eth. In case of IB, 112 * B0 mode is in use. 113 */ 114 enum { 115 MLX4_STEERING_MODE_A0, 116 MLX4_STEERING_MODE_B0, 117 MLX4_STEERING_MODE_DEVICE_MANAGED 118 }; 119 120 enum { 121 MLX4_STEERING_DMFS_A0_DEFAULT, 122 MLX4_STEERING_DMFS_A0_DYNAMIC, 123 MLX4_STEERING_DMFS_A0_STATIC, 124 MLX4_STEERING_DMFS_A0_DISABLE, 125 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 126 }; 127 128 static inline const char *mlx4_steering_mode_str(int steering_mode) 129 { 130 switch (steering_mode) { 131 case MLX4_STEERING_MODE_A0: 132 return "A0 steering"; 133 134 case MLX4_STEERING_MODE_B0: 135 return "B0 steering"; 136 137 case MLX4_STEERING_MODE_DEVICE_MANAGED: 138 return "Device managed flow steering"; 139 140 default: 141 return "Unrecognize steering mode"; 142 } 143 } 144 145 enum { 146 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 147 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 148 }; 149 150 enum { 151 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 152 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 153 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 154 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 155 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 156 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 157 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 158 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 159 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 160 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 161 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 162 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 163 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 164 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 165 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 166 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 167 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 168 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 169 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 170 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 171 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 172 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 173 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 174 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 175 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 176 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 177 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 178 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 179 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 180 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 181 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 182 }; 183 184 enum { 185 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 186 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 187 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 188 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 189 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 190 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 191 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 192 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 193 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 194 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 195 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 196 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 197 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 198 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 199 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 200 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 201 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 203 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 204 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 205 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 206 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 207 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 208 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 209 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 210 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 211 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 212 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 213 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 214 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 215 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 216 }; 217 218 enum { 219 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 220 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 221 }; 222 223 enum { 224 MLX4_VF_CAP_FLAG_RESET = 1 << 0 225 }; 226 227 /* bit enums for an 8-bit flags field indicating special use 228 * QPs which require special handling in qp_reserve_range. 229 * Currently, this only includes QPs used by the ETH interface, 230 * where we expect to use blueflame. These QPs must not have 231 * bits 6 and 7 set in their qp number. 232 * 233 * This enum may use only bits 0..7. 234 */ 235 enum { 236 MLX4_RESERVE_A0_QP = 1 << 6, 237 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 238 }; 239 240 enum { 241 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 242 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 243 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 244 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 245 }; 246 247 enum { 248 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 249 }; 250 251 enum { 252 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 253 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 254 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 255 }; 256 257 258 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 259 260 enum { 261 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 262 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 263 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 264 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 265 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 266 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 267 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 268 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 269 }; 270 271 enum { 272 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP 273 }; 274 275 enum mlx4_event { 276 MLX4_EVENT_TYPE_COMP = 0x00, 277 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 278 MLX4_EVENT_TYPE_COMM_EST = 0x02, 279 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 280 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 281 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 282 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 283 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 284 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 285 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 286 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 287 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 288 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 289 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 290 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 291 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 292 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 293 MLX4_EVENT_TYPE_CMD = 0x0a, 294 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 295 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 296 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 297 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 298 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 299 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 300 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 301 MLX4_EVENT_TYPE_NONE = 0xff, 302 }; 303 304 enum { 305 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 306 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 307 }; 308 309 enum { 310 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 311 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 312 }; 313 314 enum { 315 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 316 }; 317 318 enum slave_port_state { 319 SLAVE_PORT_DOWN = 0, 320 SLAVE_PENDING_UP, 321 SLAVE_PORT_UP, 322 }; 323 324 enum slave_port_gen_event { 325 SLAVE_PORT_GEN_EVENT_DOWN = 0, 326 SLAVE_PORT_GEN_EVENT_UP, 327 SLAVE_PORT_GEN_EVENT_NONE, 328 }; 329 330 enum slave_port_state_event { 331 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 332 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 333 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 334 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 335 }; 336 337 enum { 338 MLX4_PERM_LOCAL_READ = 1 << 10, 339 MLX4_PERM_LOCAL_WRITE = 1 << 11, 340 MLX4_PERM_REMOTE_READ = 1 << 12, 341 MLX4_PERM_REMOTE_WRITE = 1 << 13, 342 MLX4_PERM_ATOMIC = 1 << 14, 343 MLX4_PERM_BIND_MW = 1 << 15, 344 MLX4_PERM_MASK = 0xFC00 345 }; 346 347 enum { 348 MLX4_OPCODE_NOP = 0x00, 349 MLX4_OPCODE_SEND_INVAL = 0x01, 350 MLX4_OPCODE_RDMA_WRITE = 0x08, 351 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 352 MLX4_OPCODE_SEND = 0x0a, 353 MLX4_OPCODE_SEND_IMM = 0x0b, 354 MLX4_OPCODE_LSO = 0x0e, 355 MLX4_OPCODE_RDMA_READ = 0x10, 356 MLX4_OPCODE_ATOMIC_CS = 0x11, 357 MLX4_OPCODE_ATOMIC_FA = 0x12, 358 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 359 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 360 MLX4_OPCODE_BIND_MW = 0x18, 361 MLX4_OPCODE_FMR = 0x19, 362 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 363 MLX4_OPCODE_CONFIG_CMD = 0x1f, 364 365 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 366 MLX4_RECV_OPCODE_SEND = 0x01, 367 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 368 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 369 370 MLX4_CQE_OPCODE_ERROR = 0x1e, 371 MLX4_CQE_OPCODE_RESIZE = 0x16, 372 }; 373 374 enum { 375 MLX4_STAT_RATE_OFFSET = 5 376 }; 377 378 enum mlx4_protocol { 379 MLX4_PROT_IB_IPV6 = 0, 380 MLX4_PROT_ETH, 381 MLX4_PROT_IB_IPV4, 382 MLX4_PROT_FCOE 383 }; 384 385 enum { 386 MLX4_MTT_FLAG_PRESENT = 1 387 }; 388 389 enum mlx4_qp_region { 390 MLX4_QP_REGION_FW = 0, 391 MLX4_QP_REGION_RSS_RAW_ETH, 392 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 393 MLX4_QP_REGION_ETH_ADDR, 394 MLX4_QP_REGION_FC_ADDR, 395 MLX4_QP_REGION_FC_EXCH, 396 MLX4_NUM_QP_REGION 397 }; 398 399 enum mlx4_port_type { 400 MLX4_PORT_TYPE_NONE = 0, 401 MLX4_PORT_TYPE_IB = 1, 402 MLX4_PORT_TYPE_ETH = 2, 403 MLX4_PORT_TYPE_AUTO = 3 404 }; 405 406 enum mlx4_special_vlan_idx { 407 MLX4_NO_VLAN_IDX = 0, 408 MLX4_VLAN_MISS_IDX, 409 MLX4_VLAN_REGULAR 410 }; 411 412 enum mlx4_steer_type { 413 MLX4_MC_STEER = 0, 414 MLX4_UC_STEER, 415 MLX4_NUM_STEERS 416 }; 417 418 enum { 419 MLX4_NUM_FEXCH = 64 * 1024, 420 }; 421 422 enum { 423 MLX4_MAX_FAST_REG_PAGES = 511, 424 }; 425 426 enum { 427 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 428 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 429 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 430 }; 431 432 /* Port mgmt change event handling */ 433 enum { 434 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 435 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 436 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 437 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 438 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 439 }; 440 441 enum { 442 MLX4_DEVICE_STATE_UP = 1 << 0, 443 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 444 }; 445 446 enum { 447 MLX4_INTERFACE_STATE_UP = 1 << 0, 448 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 449 }; 450 451 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 452 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 453 454 enum mlx4_module_id { 455 MLX4_MODULE_ID_SFP = 0x3, 456 MLX4_MODULE_ID_QSFP = 0xC, 457 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 458 MLX4_MODULE_ID_QSFP28 = 0x11, 459 }; 460 461 enum { /* rl */ 462 MLX4_QP_RATE_LIMIT_NONE = 0, 463 MLX4_QP_RATE_LIMIT_KBS = 1, 464 MLX4_QP_RATE_LIMIT_MBS = 2, 465 MLX4_QP_RATE_LIMIT_GBS = 3 466 }; 467 468 struct mlx4_rate_limit_caps { 469 u16 num_rates; /* Number of different rates */ 470 u8 min_unit; 471 u16 min_val; 472 u8 max_unit; 473 u16 max_val; 474 }; 475 476 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 477 { 478 return (major << 32) | (minor << 16) | subminor; 479 } 480 481 struct mlx4_phys_caps { 482 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 483 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 484 u32 num_phys_eqs; 485 u32 base_sqpn; 486 u32 base_proxy_sqpn; 487 u32 base_tunnel_sqpn; 488 }; 489 490 struct mlx4_caps { 491 u64 fw_ver; 492 u32 function; 493 int num_ports; 494 int vl_cap[MLX4_MAX_PORTS + 1]; 495 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 496 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 497 u64 def_mac[MLX4_MAX_PORTS + 1]; 498 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 499 int gid_table_len[MLX4_MAX_PORTS + 1]; 500 int pkey_table_len[MLX4_MAX_PORTS + 1]; 501 int trans_type[MLX4_MAX_PORTS + 1]; 502 int vendor_oui[MLX4_MAX_PORTS + 1]; 503 int wavelength[MLX4_MAX_PORTS + 1]; 504 u64 trans_code[MLX4_MAX_PORTS + 1]; 505 int local_ca_ack_delay; 506 int num_uars; 507 u32 uar_page_size; 508 int bf_reg_size; 509 int bf_regs_per_page; 510 int max_sq_sg; 511 int max_rq_sg; 512 int num_qps; 513 int max_wqes; 514 int max_sq_desc_sz; 515 int max_rq_desc_sz; 516 int max_qp_init_rdma; 517 int max_qp_dest_rdma; 518 u32 *qp0_qkey; 519 u32 *qp0_proxy; 520 u32 *qp1_proxy; 521 u32 *qp0_tunnel; 522 u32 *qp1_tunnel; 523 int num_srqs; 524 int max_srq_wqes; 525 int max_srq_sge; 526 int reserved_srqs; 527 int num_cqs; 528 int max_cqes; 529 int reserved_cqs; 530 int num_sys_eqs; 531 int num_eqs; 532 int reserved_eqs; 533 int num_comp_vectors; 534 int num_mpts; 535 int max_fmr_maps; 536 int num_mtts; 537 int fmr_reserved_mtts; 538 int reserved_mtts; 539 int reserved_mrws; 540 int reserved_uars; 541 int num_mgms; 542 int num_amgms; 543 int reserved_mcgs; 544 int num_qp_per_mgm; 545 int steering_mode; 546 int dmfs_high_steer_mode; 547 int fs_log_max_ucast_qp_range_size; 548 int num_pds; 549 int reserved_pds; 550 int max_xrcds; 551 int reserved_xrcds; 552 int mtt_entry_sz; 553 u32 max_msg_sz; 554 u32 page_size_cap; 555 u64 flags; 556 u64 flags2; 557 u32 bmme_flags; 558 u32 reserved_lkey; 559 u16 stat_rate_support; 560 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 561 int max_gso_sz; 562 int max_rss_tbl_sz; 563 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 564 int reserved_qps; 565 int reserved_qps_base[MLX4_NUM_QP_REGION]; 566 int log_num_macs; 567 int log_num_vlans; 568 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 569 u8 supported_type[MLX4_MAX_PORTS + 1]; 570 u8 suggested_type[MLX4_MAX_PORTS + 1]; 571 u8 default_sense[MLX4_MAX_PORTS + 1]; 572 u32 port_mask[MLX4_MAX_PORTS + 1]; 573 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 574 u32 max_counters; 575 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 576 u16 sqp_demux; 577 u32 eqe_size; 578 u32 cqe_size; 579 u8 eqe_factor; 580 u32 userspace_caps; /* userspace must be aware of these */ 581 u32 function_caps; /* VFs must be aware of these */ 582 u16 hca_core_clock; 583 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 584 int tunnel_offload_mode; 585 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 586 u8 phv_bit[MLX4_MAX_PORTS + 1]; 587 u8 alloc_res_qp_mask; 588 u32 dmfs_high_rate_qpn_base; 589 u32 dmfs_high_rate_qpn_range; 590 u32 vf_caps; 591 struct mlx4_rate_limit_caps rl_caps; 592 }; 593 594 struct mlx4_buf_list { 595 void *buf; 596 dma_addr_t map; 597 }; 598 599 struct mlx4_buf { 600 struct mlx4_buf_list direct; 601 struct mlx4_buf_list *page_list; 602 int nbufs; 603 int npages; 604 int page_shift; 605 }; 606 607 struct mlx4_mtt { 608 u32 offset; 609 int order; 610 int page_shift; 611 }; 612 613 enum { 614 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 615 }; 616 617 struct mlx4_db_pgdir { 618 struct list_head list; 619 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 620 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 621 unsigned long *bits[2]; 622 __be32 *db_page; 623 dma_addr_t db_dma; 624 }; 625 626 struct mlx4_ib_user_db_page; 627 628 struct mlx4_db { 629 __be32 *db; 630 union { 631 struct mlx4_db_pgdir *pgdir; 632 struct mlx4_ib_user_db_page *user_page; 633 } u; 634 dma_addr_t dma; 635 int index; 636 int order; 637 }; 638 639 struct mlx4_hwq_resources { 640 struct mlx4_db db; 641 struct mlx4_mtt mtt; 642 struct mlx4_buf buf; 643 }; 644 645 struct mlx4_mr { 646 struct mlx4_mtt mtt; 647 u64 iova; 648 u64 size; 649 u32 key; 650 u32 pd; 651 u32 access; 652 int enabled; 653 }; 654 655 enum mlx4_mw_type { 656 MLX4_MW_TYPE_1 = 1, 657 MLX4_MW_TYPE_2 = 2, 658 }; 659 660 struct mlx4_mw { 661 u32 key; 662 u32 pd; 663 enum mlx4_mw_type type; 664 int enabled; 665 }; 666 667 struct mlx4_fmr { 668 struct mlx4_mr mr; 669 struct mlx4_mpt_entry *mpt; 670 __be64 *mtts; 671 dma_addr_t dma_handle; 672 int max_pages; 673 int max_maps; 674 int maps; 675 u8 page_shift; 676 }; 677 678 struct mlx4_uar { 679 unsigned long pfn; 680 int index; 681 struct list_head bf_list; 682 unsigned free_bf_bmap; 683 void __iomem *map; 684 void __iomem *bf_map; 685 }; 686 687 struct mlx4_bf { 688 unsigned int offset; 689 int buf_size; 690 struct mlx4_uar *uar; 691 void __iomem *reg; 692 }; 693 694 struct mlx4_cq { 695 void (*comp) (struct mlx4_cq *); 696 void (*event) (struct mlx4_cq *, enum mlx4_event); 697 698 struct mlx4_uar *uar; 699 700 u32 cons_index; 701 702 u16 irq; 703 __be32 *set_ci_db; 704 __be32 *arm_db; 705 int arm_sn; 706 707 int cqn; 708 unsigned vector; 709 710 atomic_t refcount; 711 struct completion free; 712 struct { 713 struct list_head list; 714 void (*comp)(struct mlx4_cq *); 715 void *priv; 716 } tasklet_ctx; 717 int reset_notify_added; 718 struct list_head reset_notify; 719 }; 720 721 struct mlx4_qp { 722 void (*event) (struct mlx4_qp *, enum mlx4_event); 723 724 int qpn; 725 726 atomic_t refcount; 727 struct completion free; 728 }; 729 730 struct mlx4_srq { 731 void (*event) (struct mlx4_srq *, enum mlx4_event); 732 733 int srqn; 734 int max; 735 int max_gs; 736 int wqe_shift; 737 738 atomic_t refcount; 739 struct completion free; 740 }; 741 742 struct mlx4_av { 743 __be32 port_pd; 744 u8 reserved1; 745 u8 g_slid; 746 __be16 dlid; 747 u8 reserved2; 748 u8 gid_index; 749 u8 stat_rate; 750 u8 hop_limit; 751 __be32 sl_tclass_flowlabel; 752 u8 dgid[16]; 753 }; 754 755 struct mlx4_eth_av { 756 __be32 port_pd; 757 u8 reserved1; 758 u8 smac_idx; 759 u16 reserved2; 760 u8 reserved3; 761 u8 gid_index; 762 u8 stat_rate; 763 u8 hop_limit; 764 __be32 sl_tclass_flowlabel; 765 u8 dgid[16]; 766 u8 s_mac[6]; 767 u8 reserved4[2]; 768 __be16 vlan; 769 u8 mac[ETH_ALEN]; 770 }; 771 772 union mlx4_ext_av { 773 struct mlx4_av ib; 774 struct mlx4_eth_av eth; 775 }; 776 777 /* Counters should be saturate once they reach their maximum value */ 778 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 779 if ((value) > U32_MAX) \ 780 counter = cpu_to_be32(U32_MAX); \ 781 else \ 782 counter = cpu_to_be32(value); \ 783 } while (0) 784 785 struct mlx4_counter { 786 u8 reserved1[3]; 787 u8 counter_mode; 788 __be32 num_ifc; 789 u32 reserved2[2]; 790 __be64 rx_frames; 791 __be64 rx_bytes; 792 __be64 tx_frames; 793 __be64 tx_bytes; 794 }; 795 796 struct mlx4_quotas { 797 int qp; 798 int cq; 799 int srq; 800 int mpt; 801 int mtt; 802 int counter; 803 int xrcd; 804 }; 805 806 struct mlx4_vf_dev { 807 u8 min_port; 808 u8 n_ports; 809 }; 810 811 struct mlx4_dev_persistent { 812 struct pci_dev *pdev; 813 struct mlx4_dev *dev; 814 int nvfs[MLX4_MAX_PORTS + 1]; 815 int num_vfs; 816 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 817 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 818 struct work_struct catas_work; 819 struct workqueue_struct *catas_wq; 820 struct mutex device_state_mutex; /* protect HW state */ 821 u8 state; 822 struct mutex interface_state_mutex; /* protect SW state */ 823 u8 interface_state; 824 }; 825 826 struct mlx4_dev { 827 struct mlx4_dev_persistent *persist; 828 unsigned long flags; 829 unsigned long num_slaves; 830 struct mlx4_caps caps; 831 struct mlx4_phys_caps phys_caps; 832 struct mlx4_quotas quotas; 833 struct radix_tree_root qp_table_tree; 834 u8 rev_id; 835 char board_id[MLX4_BOARD_ID_LEN]; 836 int numa_node; 837 int oper_log_mgm_entry_size; 838 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 839 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 840 struct mlx4_vf_dev *dev_vfs; 841 }; 842 843 struct mlx4_clock_params { 844 u64 offset; 845 u8 bar; 846 u8 size; 847 }; 848 849 struct mlx4_eqe { 850 u8 reserved1; 851 u8 type; 852 u8 reserved2; 853 u8 subtype; 854 union { 855 u32 raw[6]; 856 struct { 857 __be32 cqn; 858 } __packed comp; 859 struct { 860 u16 reserved1; 861 __be16 token; 862 u32 reserved2; 863 u8 reserved3[3]; 864 u8 status; 865 __be64 out_param; 866 } __packed cmd; 867 struct { 868 __be32 qpn; 869 } __packed qp; 870 struct { 871 __be32 srqn; 872 } __packed srq; 873 struct { 874 __be32 cqn; 875 u32 reserved1; 876 u8 reserved2[3]; 877 u8 syndrome; 878 } __packed cq_err; 879 struct { 880 u32 reserved1[2]; 881 __be32 port; 882 } __packed port_change; 883 struct { 884 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 885 u32 reserved; 886 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 887 } __packed comm_channel_arm; 888 struct { 889 u8 port; 890 u8 reserved[3]; 891 __be64 mac; 892 } __packed mac_update; 893 struct { 894 __be32 slave_id; 895 } __packed flr_event; 896 struct { 897 __be16 current_temperature; 898 __be16 warning_threshold; 899 } __packed warming; 900 struct { 901 u8 reserved[3]; 902 u8 port; 903 union { 904 struct { 905 __be16 mstr_sm_lid; 906 __be16 port_lid; 907 __be32 changed_attr; 908 u8 reserved[3]; 909 u8 mstr_sm_sl; 910 __be64 gid_prefix; 911 } __packed port_info; 912 struct { 913 __be32 block_ptr; 914 __be32 tbl_entries_mask; 915 } __packed tbl_change_info; 916 } params; 917 } __packed port_mgmt_change; 918 struct { 919 u8 reserved[3]; 920 u8 port; 921 u32 reserved1[5]; 922 } __packed bad_cable; 923 } event; 924 u8 slave_id; 925 u8 reserved3[2]; 926 u8 owner; 927 } __packed; 928 929 struct mlx4_init_port_param { 930 int set_guid0; 931 int set_node_guid; 932 int set_si_guid; 933 u16 mtu; 934 int port_width_cap; 935 u16 vl_cap; 936 u16 max_gid; 937 u16 max_pkey; 938 u64 guid0; 939 u64 node_guid; 940 u64 si_guid; 941 }; 942 943 #define MAD_IFC_DATA_SZ 192 944 /* MAD IFC Mailbox */ 945 struct mlx4_mad_ifc { 946 u8 base_version; 947 u8 mgmt_class; 948 u8 class_version; 949 u8 method; 950 __be16 status; 951 __be16 class_specific; 952 __be64 tid; 953 __be16 attr_id; 954 __be16 resv; 955 __be32 attr_mod; 956 __be64 mkey; 957 __be16 dr_slid; 958 __be16 dr_dlid; 959 u8 reserved[28]; 960 u8 data[MAD_IFC_DATA_SZ]; 961 } __packed; 962 963 #define mlx4_foreach_port(port, dev, type) \ 964 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 965 if ((type) == (dev)->caps.port_mask[(port)]) 966 967 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 968 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 969 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 970 971 #define mlx4_foreach_ib_transport_port(port, dev) \ 972 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 973 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 974 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 975 976 #define MLX4_INVALID_SLAVE_ID 0xFF 977 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 978 979 void handle_port_mgmt_change_event(struct work_struct *work); 980 981 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 982 { 983 return dev->caps.function; 984 } 985 986 static inline int mlx4_is_master(struct mlx4_dev *dev) 987 { 988 return dev->flags & MLX4_FLAG_MASTER; 989 } 990 991 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 992 { 993 return dev->phys_caps.base_sqpn + 8 + 994 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 995 } 996 997 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 998 { 999 return (qpn < dev->phys_caps.base_sqpn + 8 + 1000 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1001 qpn >= dev->phys_caps.base_sqpn) || 1002 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1003 } 1004 1005 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1006 { 1007 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1008 1009 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1010 return 1; 1011 1012 return 0; 1013 } 1014 1015 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1016 { 1017 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1018 } 1019 1020 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1021 { 1022 return dev->flags & MLX4_FLAG_SLAVE; 1023 } 1024 1025 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1026 { 1027 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1028 } 1029 1030 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1031 struct mlx4_buf *buf, gfp_t gfp); 1032 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1033 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1034 { 1035 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1036 return buf->direct.buf + offset; 1037 else 1038 return buf->page_list[offset >> PAGE_SHIFT].buf + 1039 (offset & (PAGE_SIZE - 1)); 1040 } 1041 1042 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1043 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1044 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1045 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1046 1047 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1048 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1049 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1050 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1051 1052 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1053 struct mlx4_mtt *mtt); 1054 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1055 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1056 1057 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1058 int npages, int page_shift, struct mlx4_mr *mr); 1059 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1060 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1061 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1062 struct mlx4_mw *mw); 1063 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1064 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1065 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1066 int start_index, int npages, u64 *page_list); 1067 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1068 struct mlx4_buf *buf, gfp_t gfp); 1069 1070 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1071 gfp_t gfp); 1072 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1073 1074 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1075 int size, int max_direct); 1076 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1077 int size); 1078 1079 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1080 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1081 unsigned vector, int collapsed, int timestamp_en); 1082 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1083 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1084 int *base, u8 flags); 1085 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1086 1087 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1088 gfp_t gfp); 1089 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1090 1091 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1092 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1093 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1094 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1095 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1096 1097 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1098 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1099 1100 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1101 int block_mcast_loopback, enum mlx4_protocol prot); 1102 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1103 enum mlx4_protocol prot); 1104 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1105 u8 port, int block_mcast_loopback, 1106 enum mlx4_protocol protocol, u64 *reg_id); 1107 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1108 enum mlx4_protocol protocol, u64 reg_id); 1109 1110 enum { 1111 MLX4_DOMAIN_UVERBS = 0x1000, 1112 MLX4_DOMAIN_ETHTOOL = 0x2000, 1113 MLX4_DOMAIN_RFS = 0x3000, 1114 MLX4_DOMAIN_NIC = 0x5000, 1115 }; 1116 1117 enum mlx4_net_trans_rule_id { 1118 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1119 MLX4_NET_TRANS_RULE_ID_IB, 1120 MLX4_NET_TRANS_RULE_ID_IPV6, 1121 MLX4_NET_TRANS_RULE_ID_IPV4, 1122 MLX4_NET_TRANS_RULE_ID_TCP, 1123 MLX4_NET_TRANS_RULE_ID_UDP, 1124 MLX4_NET_TRANS_RULE_ID_VXLAN, 1125 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1126 }; 1127 1128 extern const u16 __sw_id_hw[]; 1129 1130 static inline int map_hw_to_sw_id(u16 header_id) 1131 { 1132 1133 int i; 1134 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1135 if (header_id == __sw_id_hw[i]) 1136 return i; 1137 } 1138 return -EINVAL; 1139 } 1140 1141 enum mlx4_net_trans_promisc_mode { 1142 MLX4_FS_REGULAR = 1, 1143 MLX4_FS_ALL_DEFAULT, 1144 MLX4_FS_MC_DEFAULT, 1145 MLX4_FS_UC_SNIFFER, 1146 MLX4_FS_MC_SNIFFER, 1147 MLX4_FS_MODE_NUM, /* should be last */ 1148 }; 1149 1150 struct mlx4_spec_eth { 1151 u8 dst_mac[ETH_ALEN]; 1152 u8 dst_mac_msk[ETH_ALEN]; 1153 u8 src_mac[ETH_ALEN]; 1154 u8 src_mac_msk[ETH_ALEN]; 1155 u8 ether_type_enable; 1156 __be16 ether_type; 1157 __be16 vlan_id_msk; 1158 __be16 vlan_id; 1159 }; 1160 1161 struct mlx4_spec_tcp_udp { 1162 __be16 dst_port; 1163 __be16 dst_port_msk; 1164 __be16 src_port; 1165 __be16 src_port_msk; 1166 }; 1167 1168 struct mlx4_spec_ipv4 { 1169 __be32 dst_ip; 1170 __be32 dst_ip_msk; 1171 __be32 src_ip; 1172 __be32 src_ip_msk; 1173 }; 1174 1175 struct mlx4_spec_ib { 1176 __be32 l3_qpn; 1177 __be32 qpn_msk; 1178 u8 dst_gid[16]; 1179 u8 dst_gid_msk[16]; 1180 }; 1181 1182 struct mlx4_spec_vxlan { 1183 __be32 vni; 1184 __be32 vni_mask; 1185 1186 }; 1187 1188 struct mlx4_spec_list { 1189 struct list_head list; 1190 enum mlx4_net_trans_rule_id id; 1191 union { 1192 struct mlx4_spec_eth eth; 1193 struct mlx4_spec_ib ib; 1194 struct mlx4_spec_ipv4 ipv4; 1195 struct mlx4_spec_tcp_udp tcp_udp; 1196 struct mlx4_spec_vxlan vxlan; 1197 }; 1198 }; 1199 1200 enum mlx4_net_trans_hw_rule_queue { 1201 MLX4_NET_TRANS_Q_FIFO, 1202 MLX4_NET_TRANS_Q_LIFO, 1203 }; 1204 1205 struct mlx4_net_trans_rule { 1206 struct list_head list; 1207 enum mlx4_net_trans_hw_rule_queue queue_mode; 1208 bool exclusive; 1209 bool allow_loopback; 1210 enum mlx4_net_trans_promisc_mode promisc_mode; 1211 u8 port; 1212 u16 priority; 1213 u32 qpn; 1214 }; 1215 1216 struct mlx4_net_trans_rule_hw_ctrl { 1217 __be16 prio; 1218 u8 type; 1219 u8 flags; 1220 u8 rsvd1; 1221 u8 funcid; 1222 u8 vep; 1223 u8 port; 1224 __be32 qpn; 1225 __be32 rsvd2; 1226 }; 1227 1228 struct mlx4_net_trans_rule_hw_ib { 1229 u8 size; 1230 u8 rsvd1; 1231 __be16 id; 1232 u32 rsvd2; 1233 __be32 l3_qpn; 1234 __be32 qpn_mask; 1235 u8 dst_gid[16]; 1236 u8 dst_gid_msk[16]; 1237 } __packed; 1238 1239 struct mlx4_net_trans_rule_hw_eth { 1240 u8 size; 1241 u8 rsvd; 1242 __be16 id; 1243 u8 rsvd1[6]; 1244 u8 dst_mac[6]; 1245 u16 rsvd2; 1246 u8 dst_mac_msk[6]; 1247 u16 rsvd3; 1248 u8 src_mac[6]; 1249 u16 rsvd4; 1250 u8 src_mac_msk[6]; 1251 u8 rsvd5; 1252 u8 ether_type_enable; 1253 __be16 ether_type; 1254 __be16 vlan_tag_msk; 1255 __be16 vlan_tag; 1256 } __packed; 1257 1258 struct mlx4_net_trans_rule_hw_tcp_udp { 1259 u8 size; 1260 u8 rsvd; 1261 __be16 id; 1262 __be16 rsvd1[3]; 1263 __be16 dst_port; 1264 __be16 rsvd2; 1265 __be16 dst_port_msk; 1266 __be16 rsvd3; 1267 __be16 src_port; 1268 __be16 rsvd4; 1269 __be16 src_port_msk; 1270 } __packed; 1271 1272 struct mlx4_net_trans_rule_hw_ipv4 { 1273 u8 size; 1274 u8 rsvd; 1275 __be16 id; 1276 __be32 rsvd1; 1277 __be32 dst_ip; 1278 __be32 dst_ip_msk; 1279 __be32 src_ip; 1280 __be32 src_ip_msk; 1281 } __packed; 1282 1283 struct mlx4_net_trans_rule_hw_vxlan { 1284 u8 size; 1285 u8 rsvd; 1286 __be16 id; 1287 __be32 rsvd1; 1288 __be32 vni; 1289 __be32 vni_mask; 1290 } __packed; 1291 1292 struct _rule_hw { 1293 union { 1294 struct { 1295 u8 size; 1296 u8 rsvd; 1297 __be16 id; 1298 }; 1299 struct mlx4_net_trans_rule_hw_eth eth; 1300 struct mlx4_net_trans_rule_hw_ib ib; 1301 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1302 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1303 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1304 }; 1305 }; 1306 1307 enum { 1308 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1309 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1310 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1311 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1312 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1313 }; 1314 1315 1316 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1317 enum mlx4_net_trans_promisc_mode mode); 1318 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1319 enum mlx4_net_trans_promisc_mode mode); 1320 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1321 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1322 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1323 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1324 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1325 1326 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1327 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1328 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1329 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1330 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1331 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1332 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1333 u8 promisc); 1334 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1335 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1336 u8 ignore_fcs_value); 1337 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1338 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1339 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1340 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1341 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1342 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1343 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1344 1345 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1346 int npages, u64 iova, u32 *lkey, u32 *rkey); 1347 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1348 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1349 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1350 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1351 u32 *lkey, u32 *rkey); 1352 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1353 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1354 int mlx4_test_interrupts(struct mlx4_dev *dev); 1355 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1356 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1357 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1358 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1359 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1360 1361 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1362 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1363 1364 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1365 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1366 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1367 1368 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1369 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1370 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1371 1372 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1373 int port); 1374 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1375 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1376 int mlx4_flow_attach(struct mlx4_dev *dev, 1377 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1378 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1379 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1380 enum mlx4_net_trans_promisc_mode flow_type); 1381 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1382 enum mlx4_net_trans_rule_id id); 1383 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1384 1385 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1386 int port, int qpn, u16 prio, u64 *reg_id); 1387 1388 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1389 int i, int val); 1390 1391 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1392 1393 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1394 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1395 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1396 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1397 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1398 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1399 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1400 1401 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1402 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1403 1404 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1405 int *slave_id); 1406 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1407 u8 *gid); 1408 1409 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1410 u32 max_range_qpn); 1411 1412 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1413 1414 struct mlx4_active_ports { 1415 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1416 }; 1417 /* Returns a bitmap of the physical ports which are assigned to slave */ 1418 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1419 1420 /* Returns the physical port that represents the virtual port of the slave, */ 1421 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1422 /* mapping is returned. */ 1423 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1424 1425 struct mlx4_slaves_pport { 1426 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1427 }; 1428 /* Returns a bitmap of all slaves that are assigned to port. */ 1429 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1430 int port); 1431 1432 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1433 /* the ports that are set in crit_ports. */ 1434 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1435 struct mlx4_dev *dev, 1436 const struct mlx4_active_ports *crit_ports); 1437 1438 /* Returns the slave's virtual port that represents the physical port. */ 1439 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1440 1441 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1442 1443 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1444 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1445 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1446 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1447 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1448 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1449 int enable); 1450 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1451 struct mlx4_mpt_entry ***mpt_entry); 1452 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1453 struct mlx4_mpt_entry **mpt_entry); 1454 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1455 u32 pdn); 1456 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1457 struct mlx4_mpt_entry *mpt_entry, 1458 u32 access); 1459 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1460 struct mlx4_mpt_entry **mpt_entry); 1461 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1462 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1463 u64 iova, u64 size, int npages, 1464 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1465 1466 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1467 u16 offset, u16 size, u8 *data); 1468 1469 /* Returns true if running in low memory profile (kdump kernel) */ 1470 static inline bool mlx4_low_memory_profile(void) 1471 { 1472 return is_kdump_kernel(); 1473 } 1474 1475 /* ACCESS REG commands */ 1476 enum mlx4_access_reg_method { 1477 MLX4_ACCESS_REG_QUERY = 0x1, 1478 MLX4_ACCESS_REG_WRITE = 0x2, 1479 }; 1480 1481 /* ACCESS PTYS Reg command */ 1482 enum mlx4_ptys_proto { 1483 MLX4_PTYS_IB = 1<<0, 1484 MLX4_PTYS_EN = 1<<2, 1485 }; 1486 1487 struct mlx4_ptys_reg { 1488 u8 resrvd1; 1489 u8 local_port; 1490 u8 resrvd2; 1491 u8 proto_mask; 1492 __be32 resrvd3[2]; 1493 __be32 eth_proto_cap; 1494 __be16 ib_width_cap; 1495 __be16 ib_speed_cap; 1496 __be32 resrvd4; 1497 __be32 eth_proto_admin; 1498 __be16 ib_width_admin; 1499 __be16 ib_speed_admin; 1500 __be32 resrvd5; 1501 __be32 eth_proto_oper; 1502 __be16 ib_width_oper; 1503 __be16 ib_speed_oper; 1504 __be32 resrvd6; 1505 __be32 eth_proto_lp_adv; 1506 } __packed; 1507 1508 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1509 enum mlx4_access_reg_method method, 1510 struct mlx4_ptys_reg *ptys_reg); 1511 1512 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1513 struct mlx4_clock_params *params); 1514 1515 #endif /* MLX4_DEVICE_H */ 1516