1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/pci.h> 37 #include <linux/completion.h> 38 #include <linux/radix-tree.h> 39 #include <linux/cpu_rmap.h> 40 41 #include <linux/atomic.h> 42 43 #define MAX_MSIX_P_PORT 17 44 #define MAX_MSIX 64 45 #define MSIX_LEGACY_SZ 4 46 #define MIN_MSIX_P_PORT 5 47 48 enum { 49 MLX4_FLAG_MSI_X = 1 << 0, 50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 51 MLX4_FLAG_MASTER = 1 << 2, 52 MLX4_FLAG_SLAVE = 1 << 3, 53 MLX4_FLAG_SRIOV = 1 << 4, 54 }; 55 56 enum { 57 MLX4_PORT_CAP_IS_SM = 1 << 1, 58 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 59 }; 60 61 enum { 62 MLX4_MAX_PORTS = 2, 63 MLX4_MAX_PORT_PKEYS = 128 64 }; 65 66 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 67 * These qkeys must not be allowed for general use. This is a 64k range, 68 * and to test for violation, we use the mask (protect against future chg). 69 */ 70 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 71 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 72 73 enum { 74 MLX4_BOARD_ID_LEN = 64 75 }; 76 77 enum { 78 MLX4_MAX_NUM_PF = 16, 79 MLX4_MAX_NUM_VF = 64, 80 MLX4_MFUNC_MAX = 80, 81 MLX4_MAX_EQ_NUM = 1024, 82 MLX4_MFUNC_EQ_NUM = 4, 83 MLX4_MFUNC_MAX_EQES = 8, 84 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 85 }; 86 87 /* Driver supports 3 diffrent device methods to manage traffic steering: 88 * -device managed - High level API for ib and eth flow steering. FW is 89 * managing flow steering tables. 90 * - B0 steering mode - Common low level API for ib and (if supported) eth. 91 * - A0 steering mode - Limited low level API for eth. In case of IB, 92 * B0 mode is in use. 93 */ 94 enum { 95 MLX4_STEERING_MODE_A0, 96 MLX4_STEERING_MODE_B0, 97 MLX4_STEERING_MODE_DEVICE_MANAGED 98 }; 99 100 static inline const char *mlx4_steering_mode_str(int steering_mode) 101 { 102 switch (steering_mode) { 103 case MLX4_STEERING_MODE_A0: 104 return "A0 steering"; 105 106 case MLX4_STEERING_MODE_B0: 107 return "B0 steering"; 108 109 case MLX4_STEERING_MODE_DEVICE_MANAGED: 110 return "Device managed flow steering"; 111 112 default: 113 return "Unrecognize steering mode"; 114 } 115 } 116 117 enum { 118 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 119 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 120 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 121 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 122 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 123 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 124 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 125 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 126 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 127 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 128 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 129 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 130 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 131 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 132 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 133 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 134 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 135 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 136 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 137 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 138 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 139 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 142 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 143 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 144 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 145 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 146 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 147 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 148 }; 149 150 enum { 151 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 152 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 153 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 154 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 155 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4 156 }; 157 158 enum { 159 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 160 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 161 }; 162 163 enum { 164 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 165 }; 166 167 enum { 168 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 169 }; 170 171 172 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 173 174 enum { 175 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 176 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 177 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 178 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 179 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 180 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 181 }; 182 183 enum mlx4_event { 184 MLX4_EVENT_TYPE_COMP = 0x00, 185 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 186 MLX4_EVENT_TYPE_COMM_EST = 0x02, 187 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 188 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 189 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 190 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 191 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 192 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 193 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 194 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 195 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 196 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 197 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 198 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 199 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 200 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 201 MLX4_EVENT_TYPE_CMD = 0x0a, 202 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 203 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 204 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 205 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 206 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 207 MLX4_EVENT_TYPE_NONE = 0xff, 208 }; 209 210 enum { 211 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 212 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 213 }; 214 215 enum { 216 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 217 }; 218 219 enum slave_port_state { 220 SLAVE_PORT_DOWN = 0, 221 SLAVE_PENDING_UP, 222 SLAVE_PORT_UP, 223 }; 224 225 enum slave_port_gen_event { 226 SLAVE_PORT_GEN_EVENT_DOWN = 0, 227 SLAVE_PORT_GEN_EVENT_UP, 228 SLAVE_PORT_GEN_EVENT_NONE, 229 }; 230 231 enum slave_port_state_event { 232 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 233 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 234 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 235 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 236 }; 237 238 enum { 239 MLX4_PERM_LOCAL_READ = 1 << 10, 240 MLX4_PERM_LOCAL_WRITE = 1 << 11, 241 MLX4_PERM_REMOTE_READ = 1 << 12, 242 MLX4_PERM_REMOTE_WRITE = 1 << 13, 243 MLX4_PERM_ATOMIC = 1 << 14, 244 MLX4_PERM_BIND_MW = 1 << 15, 245 }; 246 247 enum { 248 MLX4_OPCODE_NOP = 0x00, 249 MLX4_OPCODE_SEND_INVAL = 0x01, 250 MLX4_OPCODE_RDMA_WRITE = 0x08, 251 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 252 MLX4_OPCODE_SEND = 0x0a, 253 MLX4_OPCODE_SEND_IMM = 0x0b, 254 MLX4_OPCODE_LSO = 0x0e, 255 MLX4_OPCODE_RDMA_READ = 0x10, 256 MLX4_OPCODE_ATOMIC_CS = 0x11, 257 MLX4_OPCODE_ATOMIC_FA = 0x12, 258 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 259 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 260 MLX4_OPCODE_BIND_MW = 0x18, 261 MLX4_OPCODE_FMR = 0x19, 262 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 263 MLX4_OPCODE_CONFIG_CMD = 0x1f, 264 265 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 266 MLX4_RECV_OPCODE_SEND = 0x01, 267 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 268 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 269 270 MLX4_CQE_OPCODE_ERROR = 0x1e, 271 MLX4_CQE_OPCODE_RESIZE = 0x16, 272 }; 273 274 enum { 275 MLX4_STAT_RATE_OFFSET = 5 276 }; 277 278 enum mlx4_protocol { 279 MLX4_PROT_IB_IPV6 = 0, 280 MLX4_PROT_ETH, 281 MLX4_PROT_IB_IPV4, 282 MLX4_PROT_FCOE 283 }; 284 285 enum { 286 MLX4_MTT_FLAG_PRESENT = 1 287 }; 288 289 enum mlx4_qp_region { 290 MLX4_QP_REGION_FW = 0, 291 MLX4_QP_REGION_ETH_ADDR, 292 MLX4_QP_REGION_FC_ADDR, 293 MLX4_QP_REGION_FC_EXCH, 294 MLX4_NUM_QP_REGION 295 }; 296 297 enum mlx4_port_type { 298 MLX4_PORT_TYPE_NONE = 0, 299 MLX4_PORT_TYPE_IB = 1, 300 MLX4_PORT_TYPE_ETH = 2, 301 MLX4_PORT_TYPE_AUTO = 3 302 }; 303 304 enum mlx4_special_vlan_idx { 305 MLX4_NO_VLAN_IDX = 0, 306 MLX4_VLAN_MISS_IDX, 307 MLX4_VLAN_REGULAR 308 }; 309 310 enum mlx4_steer_type { 311 MLX4_MC_STEER = 0, 312 MLX4_UC_STEER, 313 MLX4_NUM_STEERS 314 }; 315 316 enum { 317 MLX4_NUM_FEXCH = 64 * 1024, 318 }; 319 320 enum { 321 MLX4_MAX_FAST_REG_PAGES = 511, 322 }; 323 324 enum { 325 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 326 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 327 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 328 }; 329 330 /* Port mgmt change event handling */ 331 enum { 332 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 333 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 334 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 335 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 336 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 337 }; 338 339 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 340 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 341 342 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 343 { 344 return (major << 32) | (minor << 16) | subminor; 345 } 346 347 struct mlx4_phys_caps { 348 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 349 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 350 u32 num_phys_eqs; 351 u32 base_sqpn; 352 u32 base_proxy_sqpn; 353 u32 base_tunnel_sqpn; 354 }; 355 356 struct mlx4_caps { 357 u64 fw_ver; 358 u32 function; 359 int num_ports; 360 int vl_cap[MLX4_MAX_PORTS + 1]; 361 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 362 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 363 u64 def_mac[MLX4_MAX_PORTS + 1]; 364 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 365 int gid_table_len[MLX4_MAX_PORTS + 1]; 366 int pkey_table_len[MLX4_MAX_PORTS + 1]; 367 int trans_type[MLX4_MAX_PORTS + 1]; 368 int vendor_oui[MLX4_MAX_PORTS + 1]; 369 int wavelength[MLX4_MAX_PORTS + 1]; 370 u64 trans_code[MLX4_MAX_PORTS + 1]; 371 int local_ca_ack_delay; 372 int num_uars; 373 u32 uar_page_size; 374 int bf_reg_size; 375 int bf_regs_per_page; 376 int max_sq_sg; 377 int max_rq_sg; 378 int num_qps; 379 int max_wqes; 380 int max_sq_desc_sz; 381 int max_rq_desc_sz; 382 int max_qp_init_rdma; 383 int max_qp_dest_rdma; 384 u32 *qp0_proxy; 385 u32 *qp1_proxy; 386 u32 *qp0_tunnel; 387 u32 *qp1_tunnel; 388 int num_srqs; 389 int max_srq_wqes; 390 int max_srq_sge; 391 int reserved_srqs; 392 int num_cqs; 393 int max_cqes; 394 int reserved_cqs; 395 int num_eqs; 396 int reserved_eqs; 397 int num_comp_vectors; 398 int comp_pool; 399 int num_mpts; 400 int max_fmr_maps; 401 int num_mtts; 402 int fmr_reserved_mtts; 403 int reserved_mtts; 404 int reserved_mrws; 405 int reserved_uars; 406 int num_mgms; 407 int num_amgms; 408 int reserved_mcgs; 409 int num_qp_per_mgm; 410 int steering_mode; 411 int fs_log_max_ucast_qp_range_size; 412 int num_pds; 413 int reserved_pds; 414 int max_xrcds; 415 int reserved_xrcds; 416 int mtt_entry_sz; 417 u32 max_msg_sz; 418 u32 page_size_cap; 419 u64 flags; 420 u64 flags2; 421 u32 bmme_flags; 422 u32 reserved_lkey; 423 u16 stat_rate_support; 424 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 425 int max_gso_sz; 426 int max_rss_tbl_sz; 427 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 428 int reserved_qps; 429 int reserved_qps_base[MLX4_NUM_QP_REGION]; 430 int log_num_macs; 431 int log_num_vlans; 432 int log_num_prios; 433 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 434 u8 supported_type[MLX4_MAX_PORTS + 1]; 435 u8 suggested_type[MLX4_MAX_PORTS + 1]; 436 u8 default_sense[MLX4_MAX_PORTS + 1]; 437 u32 port_mask[MLX4_MAX_PORTS + 1]; 438 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 439 u32 max_counters; 440 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 441 u16 sqp_demux; 442 u32 eqe_size; 443 u32 cqe_size; 444 u8 eqe_factor; 445 u32 userspace_caps; /* userspace must be aware of these */ 446 u32 function_caps; /* VFs must be aware of these */ 447 }; 448 449 struct mlx4_buf_list { 450 void *buf; 451 dma_addr_t map; 452 }; 453 454 struct mlx4_buf { 455 struct mlx4_buf_list direct; 456 struct mlx4_buf_list *page_list; 457 int nbufs; 458 int npages; 459 int page_shift; 460 }; 461 462 struct mlx4_mtt { 463 u32 offset; 464 int order; 465 int page_shift; 466 }; 467 468 enum { 469 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 470 }; 471 472 struct mlx4_db_pgdir { 473 struct list_head list; 474 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 475 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 476 unsigned long *bits[2]; 477 __be32 *db_page; 478 dma_addr_t db_dma; 479 }; 480 481 struct mlx4_ib_user_db_page; 482 483 struct mlx4_db { 484 __be32 *db; 485 union { 486 struct mlx4_db_pgdir *pgdir; 487 struct mlx4_ib_user_db_page *user_page; 488 } u; 489 dma_addr_t dma; 490 int index; 491 int order; 492 }; 493 494 struct mlx4_hwq_resources { 495 struct mlx4_db db; 496 struct mlx4_mtt mtt; 497 struct mlx4_buf buf; 498 }; 499 500 struct mlx4_mr { 501 struct mlx4_mtt mtt; 502 u64 iova; 503 u64 size; 504 u32 key; 505 u32 pd; 506 u32 access; 507 int enabled; 508 }; 509 510 enum mlx4_mw_type { 511 MLX4_MW_TYPE_1 = 1, 512 MLX4_MW_TYPE_2 = 2, 513 }; 514 515 struct mlx4_mw { 516 u32 key; 517 u32 pd; 518 enum mlx4_mw_type type; 519 int enabled; 520 }; 521 522 struct mlx4_fmr { 523 struct mlx4_mr mr; 524 struct mlx4_mpt_entry *mpt; 525 __be64 *mtts; 526 dma_addr_t dma_handle; 527 int max_pages; 528 int max_maps; 529 int maps; 530 u8 page_shift; 531 }; 532 533 struct mlx4_uar { 534 unsigned long pfn; 535 int index; 536 struct list_head bf_list; 537 unsigned free_bf_bmap; 538 void __iomem *map; 539 void __iomem *bf_map; 540 }; 541 542 struct mlx4_bf { 543 unsigned long offset; 544 int buf_size; 545 struct mlx4_uar *uar; 546 void __iomem *reg; 547 }; 548 549 struct mlx4_cq { 550 void (*comp) (struct mlx4_cq *); 551 void (*event) (struct mlx4_cq *, enum mlx4_event); 552 553 struct mlx4_uar *uar; 554 555 u32 cons_index; 556 557 __be32 *set_ci_db; 558 __be32 *arm_db; 559 int arm_sn; 560 561 int cqn; 562 unsigned vector; 563 564 atomic_t refcount; 565 struct completion free; 566 }; 567 568 struct mlx4_qp { 569 void (*event) (struct mlx4_qp *, enum mlx4_event); 570 571 int qpn; 572 573 atomic_t refcount; 574 struct completion free; 575 }; 576 577 struct mlx4_srq { 578 void (*event) (struct mlx4_srq *, enum mlx4_event); 579 580 int srqn; 581 int max; 582 int max_gs; 583 int wqe_shift; 584 585 atomic_t refcount; 586 struct completion free; 587 }; 588 589 struct mlx4_av { 590 __be32 port_pd; 591 u8 reserved1; 592 u8 g_slid; 593 __be16 dlid; 594 u8 reserved2; 595 u8 gid_index; 596 u8 stat_rate; 597 u8 hop_limit; 598 __be32 sl_tclass_flowlabel; 599 u8 dgid[16]; 600 }; 601 602 struct mlx4_eth_av { 603 __be32 port_pd; 604 u8 reserved1; 605 u8 smac_idx; 606 u16 reserved2; 607 u8 reserved3; 608 u8 gid_index; 609 u8 stat_rate; 610 u8 hop_limit; 611 __be32 sl_tclass_flowlabel; 612 u8 dgid[16]; 613 u32 reserved4[2]; 614 __be16 vlan; 615 u8 mac[6]; 616 }; 617 618 union mlx4_ext_av { 619 struct mlx4_av ib; 620 struct mlx4_eth_av eth; 621 }; 622 623 struct mlx4_counter { 624 u8 reserved1[3]; 625 u8 counter_mode; 626 __be32 num_ifc; 627 u32 reserved2[2]; 628 __be64 rx_frames; 629 __be64 rx_bytes; 630 __be64 tx_frames; 631 __be64 tx_bytes; 632 }; 633 634 struct mlx4_dev { 635 struct pci_dev *pdev; 636 unsigned long flags; 637 unsigned long num_slaves; 638 struct mlx4_caps caps; 639 struct mlx4_phys_caps phys_caps; 640 struct radix_tree_root qp_table_tree; 641 u8 rev_id; 642 char board_id[MLX4_BOARD_ID_LEN]; 643 int num_vfs; 644 int oper_log_mgm_entry_size; 645 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 646 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 647 }; 648 649 struct mlx4_eqe { 650 u8 reserved1; 651 u8 type; 652 u8 reserved2; 653 u8 subtype; 654 union { 655 u32 raw[6]; 656 struct { 657 __be32 cqn; 658 } __packed comp; 659 struct { 660 u16 reserved1; 661 __be16 token; 662 u32 reserved2; 663 u8 reserved3[3]; 664 u8 status; 665 __be64 out_param; 666 } __packed cmd; 667 struct { 668 __be32 qpn; 669 } __packed qp; 670 struct { 671 __be32 srqn; 672 } __packed srq; 673 struct { 674 __be32 cqn; 675 u32 reserved1; 676 u8 reserved2[3]; 677 u8 syndrome; 678 } __packed cq_err; 679 struct { 680 u32 reserved1[2]; 681 __be32 port; 682 } __packed port_change; 683 struct { 684 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 685 u32 reserved; 686 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 687 } __packed comm_channel_arm; 688 struct { 689 u8 port; 690 u8 reserved[3]; 691 __be64 mac; 692 } __packed mac_update; 693 struct { 694 __be32 slave_id; 695 } __packed flr_event; 696 struct { 697 __be16 current_temperature; 698 __be16 warning_threshold; 699 } __packed warming; 700 struct { 701 u8 reserved[3]; 702 u8 port; 703 union { 704 struct { 705 __be16 mstr_sm_lid; 706 __be16 port_lid; 707 __be32 changed_attr; 708 u8 reserved[3]; 709 u8 mstr_sm_sl; 710 __be64 gid_prefix; 711 } __packed port_info; 712 struct { 713 __be32 block_ptr; 714 __be32 tbl_entries_mask; 715 } __packed tbl_change_info; 716 } params; 717 } __packed port_mgmt_change; 718 } event; 719 u8 slave_id; 720 u8 reserved3[2]; 721 u8 owner; 722 } __packed; 723 724 struct mlx4_init_port_param { 725 int set_guid0; 726 int set_node_guid; 727 int set_si_guid; 728 u16 mtu; 729 int port_width_cap; 730 u16 vl_cap; 731 u16 max_gid; 732 u16 max_pkey; 733 u64 guid0; 734 u64 node_guid; 735 u64 si_guid; 736 }; 737 738 #define mlx4_foreach_port(port, dev, type) \ 739 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 740 if ((type) == (dev)->caps.port_mask[(port)]) 741 742 #define mlx4_foreach_non_ib_transport_port(port, dev) \ 743 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 744 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 745 746 #define mlx4_foreach_ib_transport_port(port, dev) \ 747 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 748 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 749 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 750 751 #define MLX4_INVALID_SLAVE_ID 0xFF 752 753 void handle_port_mgmt_change_event(struct work_struct *work); 754 755 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 756 { 757 return dev->caps.function; 758 } 759 760 static inline int mlx4_is_master(struct mlx4_dev *dev) 761 { 762 return dev->flags & MLX4_FLAG_MASTER; 763 } 764 765 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 766 { 767 return (qpn < dev->phys_caps.base_sqpn + 8 + 768 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 769 } 770 771 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 772 { 773 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 774 775 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 776 return 1; 777 778 return 0; 779 } 780 781 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 782 { 783 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 784 } 785 786 static inline int mlx4_is_slave(struct mlx4_dev *dev) 787 { 788 return dev->flags & MLX4_FLAG_SLAVE; 789 } 790 791 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 792 struct mlx4_buf *buf); 793 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 794 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 795 { 796 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 797 return buf->direct.buf + offset; 798 else 799 return buf->page_list[offset >> PAGE_SHIFT].buf + 800 (offset & (PAGE_SIZE - 1)); 801 } 802 803 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 804 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 805 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 806 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 807 808 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 809 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 810 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 811 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 812 813 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 814 struct mlx4_mtt *mtt); 815 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 816 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 817 818 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 819 int npages, int page_shift, struct mlx4_mr *mr); 820 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 821 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 822 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 823 struct mlx4_mw *mw); 824 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 825 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 826 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 827 int start_index, int npages, u64 *page_list); 828 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 829 struct mlx4_buf *buf); 830 831 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 832 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 833 834 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 835 int size, int max_direct); 836 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 837 int size); 838 839 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 840 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 841 unsigned vector, int collapsed); 842 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 843 844 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 845 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 846 847 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 848 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 849 850 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 851 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 852 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 853 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 854 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 855 856 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 857 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 858 859 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 860 int block_mcast_loopback, enum mlx4_protocol prot); 861 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 862 enum mlx4_protocol prot); 863 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 864 u8 port, int block_mcast_loopback, 865 enum mlx4_protocol protocol, u64 *reg_id); 866 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 867 enum mlx4_protocol protocol, u64 reg_id); 868 869 enum { 870 MLX4_DOMAIN_UVERBS = 0x1000, 871 MLX4_DOMAIN_ETHTOOL = 0x2000, 872 MLX4_DOMAIN_RFS = 0x3000, 873 MLX4_DOMAIN_NIC = 0x5000, 874 }; 875 876 enum mlx4_net_trans_rule_id { 877 MLX4_NET_TRANS_RULE_ID_ETH = 0, 878 MLX4_NET_TRANS_RULE_ID_IB, 879 MLX4_NET_TRANS_RULE_ID_IPV6, 880 MLX4_NET_TRANS_RULE_ID_IPV4, 881 MLX4_NET_TRANS_RULE_ID_TCP, 882 MLX4_NET_TRANS_RULE_ID_UDP, 883 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 884 }; 885 886 extern const u16 __sw_id_hw[]; 887 888 static inline int map_hw_to_sw_id(u16 header_id) 889 { 890 891 int i; 892 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 893 if (header_id == __sw_id_hw[i]) 894 return i; 895 } 896 return -EINVAL; 897 } 898 899 enum mlx4_net_trans_promisc_mode { 900 MLX4_FS_PROMISC_NONE = 0, 901 MLX4_FS_PROMISC_UPLINK, 902 /* For future use. Not implemented yet */ 903 MLX4_FS_PROMISC_FUNCTION_PORT, 904 MLX4_FS_PROMISC_ALL_MULTI, 905 }; 906 907 struct mlx4_spec_eth { 908 u8 dst_mac[6]; 909 u8 dst_mac_msk[6]; 910 u8 src_mac[6]; 911 u8 src_mac_msk[6]; 912 u8 ether_type_enable; 913 __be16 ether_type; 914 __be16 vlan_id_msk; 915 __be16 vlan_id; 916 }; 917 918 struct mlx4_spec_tcp_udp { 919 __be16 dst_port; 920 __be16 dst_port_msk; 921 __be16 src_port; 922 __be16 src_port_msk; 923 }; 924 925 struct mlx4_spec_ipv4 { 926 __be32 dst_ip; 927 __be32 dst_ip_msk; 928 __be32 src_ip; 929 __be32 src_ip_msk; 930 }; 931 932 struct mlx4_spec_ib { 933 __be32 r_qpn; 934 __be32 qpn_msk; 935 u8 dst_gid[16]; 936 u8 dst_gid_msk[16]; 937 }; 938 939 struct mlx4_spec_list { 940 struct list_head list; 941 enum mlx4_net_trans_rule_id id; 942 union { 943 struct mlx4_spec_eth eth; 944 struct mlx4_spec_ib ib; 945 struct mlx4_spec_ipv4 ipv4; 946 struct mlx4_spec_tcp_udp tcp_udp; 947 }; 948 }; 949 950 enum mlx4_net_trans_hw_rule_queue { 951 MLX4_NET_TRANS_Q_FIFO, 952 MLX4_NET_TRANS_Q_LIFO, 953 }; 954 955 struct mlx4_net_trans_rule { 956 struct list_head list; 957 enum mlx4_net_trans_hw_rule_queue queue_mode; 958 bool exclusive; 959 bool allow_loopback; 960 enum mlx4_net_trans_promisc_mode promisc_mode; 961 u8 port; 962 u16 priority; 963 u32 qpn; 964 }; 965 966 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 967 enum mlx4_net_trans_promisc_mode mode); 968 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 969 enum mlx4_net_trans_promisc_mode mode); 970 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 971 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 972 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 973 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 974 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 975 976 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 977 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 978 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 979 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 980 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); 981 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 982 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 983 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 984 u8 promisc); 985 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 986 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 987 u8 *pg, u16 *ratelimit); 988 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 989 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 990 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 991 992 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 993 int npages, u64 iova, u32 *lkey, u32 *rkey); 994 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 995 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 996 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 997 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 998 u32 *lkey, u32 *rkey); 999 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1000 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1001 int mlx4_test_interrupts(struct mlx4_dev *dev); 1002 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1003 int *vector); 1004 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1005 1006 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1007 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1008 1009 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1010 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1011 1012 int mlx4_flow_attach(struct mlx4_dev *dev, 1013 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1014 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1015 1016 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1017 int i, int val); 1018 1019 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1020 1021 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1022 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1023 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1024 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1025 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1026 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1027 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1028 1029 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1030 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1031 1032 #endif /* MLX4_DEVICE_H */ 1033