1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define DEFAULT_UAR_PAGE_SHIFT 12 48 49 #define MAX_MSIX_P_PORT 17 50 #define MAX_MSIX 64 51 #define MIN_MSIX_P_PORT 5 52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 53 (dev_cap).num_ports * MIN_MSIX_P_PORT) 54 55 #define MLX4_MAX_100M_UNITS_VAL 255 /* 56 * work around: can't set values 57 * greater then this value when 58 * using 100 Mbps units. 59 */ 60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 62 #define MLX4_RATELIMIT_DEFAULT 0x00ff 63 64 #define MLX4_ROCE_MAX_GIDS 128 65 #define MLX4_ROCE_PF_GIDS 16 66 67 enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 74 MLX4_FLAG_BONDED = 1 << 7 75 }; 76 77 enum { 78 MLX4_PORT_CAP_IS_SM = 1 << 1, 79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 80 }; 81 82 enum { 83 MLX4_MAX_PORTS = 2, 84 MLX4_MAX_PORT_PKEYS = 128, 85 MLX4_MAX_PORT_GIDS = 128 86 }; 87 88 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 89 * These qkeys must not be allowed for general use. This is a 64k range, 90 * and to test for violation, we use the mask (protect against future chg). 91 */ 92 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 93 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 94 95 enum { 96 MLX4_BOARD_ID_LEN = 64 97 }; 98 99 enum { 100 MLX4_MAX_NUM_PF = 16, 101 MLX4_MAX_NUM_VF = 126, 102 MLX4_MAX_NUM_VF_P_PORT = 64, 103 MLX4_MFUNC_MAX = 128, 104 MLX4_MAX_EQ_NUM = 1024, 105 MLX4_MFUNC_EQ_NUM = 4, 106 MLX4_MFUNC_MAX_EQES = 8, 107 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 108 }; 109 110 /* Driver supports 3 diffrent device methods to manage traffic steering: 111 * -device managed - High level API for ib and eth flow steering. FW is 112 * managing flow steering tables. 113 * - B0 steering mode - Common low level API for ib and (if supported) eth. 114 * - A0 steering mode - Limited low level API for eth. In case of IB, 115 * B0 mode is in use. 116 */ 117 enum { 118 MLX4_STEERING_MODE_A0, 119 MLX4_STEERING_MODE_B0, 120 MLX4_STEERING_MODE_DEVICE_MANAGED 121 }; 122 123 enum { 124 MLX4_STEERING_DMFS_A0_DEFAULT, 125 MLX4_STEERING_DMFS_A0_DYNAMIC, 126 MLX4_STEERING_DMFS_A0_STATIC, 127 MLX4_STEERING_DMFS_A0_DISABLE, 128 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 129 }; 130 131 static inline const char *mlx4_steering_mode_str(int steering_mode) 132 { 133 switch (steering_mode) { 134 case MLX4_STEERING_MODE_A0: 135 return "A0 steering"; 136 137 case MLX4_STEERING_MODE_B0: 138 return "B0 steering"; 139 140 case MLX4_STEERING_MODE_DEVICE_MANAGED: 141 return "Device managed flow steering"; 142 143 default: 144 return "Unrecognize steering mode"; 145 } 146 } 147 148 enum { 149 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 150 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 151 }; 152 153 enum { 154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 185 }; 186 187 enum { 188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 219 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 220 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 221 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 222 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, 223 }; 224 225 enum { 226 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 227 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 228 }; 229 230 enum { 231 MLX4_VF_CAP_FLAG_RESET = 1 << 0 232 }; 233 234 /* bit enums for an 8-bit flags field indicating special use 235 * QPs which require special handling in qp_reserve_range. 236 * Currently, this only includes QPs used by the ETH interface, 237 * where we expect to use blueflame. These QPs must not have 238 * bits 6 and 7 set in their qp number. 239 * 240 * This enum may use only bits 0..7. 241 */ 242 enum { 243 MLX4_RESERVE_A0_QP = 1 << 6, 244 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 245 }; 246 247 enum { 248 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 249 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 250 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 251 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 252 }; 253 254 enum { 255 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 256 }; 257 258 enum { 259 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 260 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 261 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 262 }; 263 264 265 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 266 267 enum { 268 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 269 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 270 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 271 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 272 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 273 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 274 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 275 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 276 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 277 }; 278 279 enum { 280 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 281 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 282 }; 283 284 enum mlx4_event { 285 MLX4_EVENT_TYPE_COMP = 0x00, 286 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 287 MLX4_EVENT_TYPE_COMM_EST = 0x02, 288 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 289 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 290 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 291 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 292 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 293 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 294 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 295 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 296 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 297 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 298 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 299 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 300 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 301 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 302 MLX4_EVENT_TYPE_CMD = 0x0a, 303 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 304 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 305 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 306 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 307 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 308 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 309 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 310 MLX4_EVENT_TYPE_NONE = 0xff, 311 }; 312 313 enum { 314 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 315 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 316 }; 317 318 enum { 319 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 320 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 321 }; 322 323 enum { 324 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 325 }; 326 327 enum slave_port_state { 328 SLAVE_PORT_DOWN = 0, 329 SLAVE_PENDING_UP, 330 SLAVE_PORT_UP, 331 }; 332 333 enum slave_port_gen_event { 334 SLAVE_PORT_GEN_EVENT_DOWN = 0, 335 SLAVE_PORT_GEN_EVENT_UP, 336 SLAVE_PORT_GEN_EVENT_NONE, 337 }; 338 339 enum slave_port_state_event { 340 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 341 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 342 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 343 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 344 }; 345 346 enum { 347 MLX4_PERM_LOCAL_READ = 1 << 10, 348 MLX4_PERM_LOCAL_WRITE = 1 << 11, 349 MLX4_PERM_REMOTE_READ = 1 << 12, 350 MLX4_PERM_REMOTE_WRITE = 1 << 13, 351 MLX4_PERM_ATOMIC = 1 << 14, 352 MLX4_PERM_BIND_MW = 1 << 15, 353 MLX4_PERM_MASK = 0xFC00 354 }; 355 356 enum { 357 MLX4_OPCODE_NOP = 0x00, 358 MLX4_OPCODE_SEND_INVAL = 0x01, 359 MLX4_OPCODE_RDMA_WRITE = 0x08, 360 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 361 MLX4_OPCODE_SEND = 0x0a, 362 MLX4_OPCODE_SEND_IMM = 0x0b, 363 MLX4_OPCODE_LSO = 0x0e, 364 MLX4_OPCODE_RDMA_READ = 0x10, 365 MLX4_OPCODE_ATOMIC_CS = 0x11, 366 MLX4_OPCODE_ATOMIC_FA = 0x12, 367 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 368 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 369 MLX4_OPCODE_BIND_MW = 0x18, 370 MLX4_OPCODE_FMR = 0x19, 371 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 372 MLX4_OPCODE_CONFIG_CMD = 0x1f, 373 374 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 375 MLX4_RECV_OPCODE_SEND = 0x01, 376 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 377 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 378 379 MLX4_CQE_OPCODE_ERROR = 0x1e, 380 MLX4_CQE_OPCODE_RESIZE = 0x16, 381 }; 382 383 enum { 384 MLX4_STAT_RATE_OFFSET = 5 385 }; 386 387 enum mlx4_protocol { 388 MLX4_PROT_IB_IPV6 = 0, 389 MLX4_PROT_ETH, 390 MLX4_PROT_IB_IPV4, 391 MLX4_PROT_FCOE 392 }; 393 394 enum { 395 MLX4_MTT_FLAG_PRESENT = 1 396 }; 397 398 enum mlx4_qp_region { 399 MLX4_QP_REGION_FW = 0, 400 MLX4_QP_REGION_RSS_RAW_ETH, 401 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 402 MLX4_QP_REGION_ETH_ADDR, 403 MLX4_QP_REGION_FC_ADDR, 404 MLX4_QP_REGION_FC_EXCH, 405 MLX4_NUM_QP_REGION 406 }; 407 408 enum mlx4_port_type { 409 MLX4_PORT_TYPE_NONE = 0, 410 MLX4_PORT_TYPE_IB = 1, 411 MLX4_PORT_TYPE_ETH = 2, 412 MLX4_PORT_TYPE_AUTO = 3 413 }; 414 415 enum mlx4_special_vlan_idx { 416 MLX4_NO_VLAN_IDX = 0, 417 MLX4_VLAN_MISS_IDX, 418 MLX4_VLAN_REGULAR 419 }; 420 421 enum mlx4_steer_type { 422 MLX4_MC_STEER = 0, 423 MLX4_UC_STEER, 424 MLX4_NUM_STEERS 425 }; 426 427 enum { 428 MLX4_NUM_FEXCH = 64 * 1024, 429 }; 430 431 enum { 432 MLX4_MAX_FAST_REG_PAGES = 511, 433 }; 434 435 enum { 436 /* 437 * Max wqe size for rdma read is 512 bytes, so this 438 * limits our max_sge_rd as the wqe needs to fit: 439 * - ctrl segment (16 bytes) 440 * - rdma segment (16 bytes) 441 * - scatter elements (16 bytes each) 442 */ 443 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 444 }; 445 446 enum { 447 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 448 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 449 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 450 }; 451 452 /* Port mgmt change event handling */ 453 enum { 454 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 455 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 456 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 457 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 458 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 459 }; 460 461 enum { 462 MLX4_DEVICE_STATE_UP = 1 << 0, 463 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 464 }; 465 466 enum { 467 MLX4_INTERFACE_STATE_UP = 1 << 0, 468 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 469 }; 470 471 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 472 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 473 474 enum mlx4_module_id { 475 MLX4_MODULE_ID_SFP = 0x3, 476 MLX4_MODULE_ID_QSFP = 0xC, 477 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 478 MLX4_MODULE_ID_QSFP28 = 0x11, 479 }; 480 481 enum { /* rl */ 482 MLX4_QP_RATE_LIMIT_NONE = 0, 483 MLX4_QP_RATE_LIMIT_KBS = 1, 484 MLX4_QP_RATE_LIMIT_MBS = 2, 485 MLX4_QP_RATE_LIMIT_GBS = 3 486 }; 487 488 struct mlx4_rate_limit_caps { 489 u16 num_rates; /* Number of different rates */ 490 u8 min_unit; 491 u16 min_val; 492 u8 max_unit; 493 u16 max_val; 494 }; 495 496 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 497 { 498 return (major << 32) | (minor << 16) | subminor; 499 } 500 501 struct mlx4_phys_caps { 502 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 503 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 504 u32 num_phys_eqs; 505 u32 base_sqpn; 506 u32 base_proxy_sqpn; 507 u32 base_tunnel_sqpn; 508 }; 509 510 struct mlx4_caps { 511 u64 fw_ver; 512 u32 function; 513 int num_ports; 514 int vl_cap[MLX4_MAX_PORTS + 1]; 515 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 516 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 517 u64 def_mac[MLX4_MAX_PORTS + 1]; 518 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 519 int gid_table_len[MLX4_MAX_PORTS + 1]; 520 int pkey_table_len[MLX4_MAX_PORTS + 1]; 521 int trans_type[MLX4_MAX_PORTS + 1]; 522 int vendor_oui[MLX4_MAX_PORTS + 1]; 523 int wavelength[MLX4_MAX_PORTS + 1]; 524 u64 trans_code[MLX4_MAX_PORTS + 1]; 525 int local_ca_ack_delay; 526 int num_uars; 527 u32 uar_page_size; 528 int bf_reg_size; 529 int bf_regs_per_page; 530 int max_sq_sg; 531 int max_rq_sg; 532 int num_qps; 533 int max_wqes; 534 int max_sq_desc_sz; 535 int max_rq_desc_sz; 536 int max_qp_init_rdma; 537 int max_qp_dest_rdma; 538 u32 *qp0_qkey; 539 u32 *qp0_proxy; 540 u32 *qp1_proxy; 541 u32 *qp0_tunnel; 542 u32 *qp1_tunnel; 543 int num_srqs; 544 int max_srq_wqes; 545 int max_srq_sge; 546 int reserved_srqs; 547 int num_cqs; 548 int max_cqes; 549 int reserved_cqs; 550 int num_sys_eqs; 551 int num_eqs; 552 int reserved_eqs; 553 int num_comp_vectors; 554 int num_mpts; 555 int max_fmr_maps; 556 int num_mtts; 557 int fmr_reserved_mtts; 558 int reserved_mtts; 559 int reserved_mrws; 560 int reserved_uars; 561 int num_mgms; 562 int num_amgms; 563 int reserved_mcgs; 564 int num_qp_per_mgm; 565 int steering_mode; 566 int dmfs_high_steer_mode; 567 int fs_log_max_ucast_qp_range_size; 568 int num_pds; 569 int reserved_pds; 570 int max_xrcds; 571 int reserved_xrcds; 572 int mtt_entry_sz; 573 u32 max_msg_sz; 574 u32 page_size_cap; 575 u64 flags; 576 u64 flags2; 577 u32 bmme_flags; 578 u32 reserved_lkey; 579 u16 stat_rate_support; 580 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 581 int max_gso_sz; 582 int max_rss_tbl_sz; 583 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 584 int reserved_qps; 585 int reserved_qps_base[MLX4_NUM_QP_REGION]; 586 int log_num_macs; 587 int log_num_vlans; 588 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 589 u8 supported_type[MLX4_MAX_PORTS + 1]; 590 u8 suggested_type[MLX4_MAX_PORTS + 1]; 591 u8 default_sense[MLX4_MAX_PORTS + 1]; 592 u32 port_mask[MLX4_MAX_PORTS + 1]; 593 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 594 u32 max_counters; 595 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 596 u16 sqp_demux; 597 u32 eqe_size; 598 u32 cqe_size; 599 u8 eqe_factor; 600 u32 userspace_caps; /* userspace must be aware of these */ 601 u32 function_caps; /* VFs must be aware of these */ 602 u16 hca_core_clock; 603 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 604 int tunnel_offload_mode; 605 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 606 u8 phv_bit[MLX4_MAX_PORTS + 1]; 607 u8 alloc_res_qp_mask; 608 u32 dmfs_high_rate_qpn_base; 609 u32 dmfs_high_rate_qpn_range; 610 u32 vf_caps; 611 struct mlx4_rate_limit_caps rl_caps; 612 }; 613 614 struct mlx4_buf_list { 615 void *buf; 616 dma_addr_t map; 617 }; 618 619 struct mlx4_buf { 620 struct mlx4_buf_list direct; 621 struct mlx4_buf_list *page_list; 622 int nbufs; 623 int npages; 624 int page_shift; 625 }; 626 627 struct mlx4_mtt { 628 u32 offset; 629 int order; 630 int page_shift; 631 }; 632 633 enum { 634 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 635 }; 636 637 struct mlx4_db_pgdir { 638 struct list_head list; 639 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 640 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 641 unsigned long *bits[2]; 642 __be32 *db_page; 643 dma_addr_t db_dma; 644 }; 645 646 struct mlx4_ib_user_db_page; 647 648 struct mlx4_db { 649 __be32 *db; 650 union { 651 struct mlx4_db_pgdir *pgdir; 652 struct mlx4_ib_user_db_page *user_page; 653 } u; 654 dma_addr_t dma; 655 int index; 656 int order; 657 }; 658 659 struct mlx4_hwq_resources { 660 struct mlx4_db db; 661 struct mlx4_mtt mtt; 662 struct mlx4_buf buf; 663 }; 664 665 struct mlx4_mr { 666 struct mlx4_mtt mtt; 667 u64 iova; 668 u64 size; 669 u32 key; 670 u32 pd; 671 u32 access; 672 int enabled; 673 }; 674 675 enum mlx4_mw_type { 676 MLX4_MW_TYPE_1 = 1, 677 MLX4_MW_TYPE_2 = 2, 678 }; 679 680 struct mlx4_mw { 681 u32 key; 682 u32 pd; 683 enum mlx4_mw_type type; 684 int enabled; 685 }; 686 687 struct mlx4_fmr { 688 struct mlx4_mr mr; 689 struct mlx4_mpt_entry *mpt; 690 __be64 *mtts; 691 dma_addr_t dma_handle; 692 int max_pages; 693 int max_maps; 694 int maps; 695 u8 page_shift; 696 }; 697 698 struct mlx4_uar { 699 unsigned long pfn; 700 int index; 701 struct list_head bf_list; 702 unsigned free_bf_bmap; 703 void __iomem *map; 704 void __iomem *bf_map; 705 }; 706 707 struct mlx4_bf { 708 unsigned int offset; 709 int buf_size; 710 struct mlx4_uar *uar; 711 void __iomem *reg; 712 }; 713 714 struct mlx4_cq { 715 void (*comp) (struct mlx4_cq *); 716 void (*event) (struct mlx4_cq *, enum mlx4_event); 717 718 struct mlx4_uar *uar; 719 720 u32 cons_index; 721 722 u16 irq; 723 __be32 *set_ci_db; 724 __be32 *arm_db; 725 int arm_sn; 726 727 int cqn; 728 unsigned vector; 729 730 atomic_t refcount; 731 struct completion free; 732 struct { 733 struct list_head list; 734 void (*comp)(struct mlx4_cq *); 735 void *priv; 736 } tasklet_ctx; 737 int reset_notify_added; 738 struct list_head reset_notify; 739 }; 740 741 struct mlx4_qp { 742 void (*event) (struct mlx4_qp *, enum mlx4_event); 743 744 int qpn; 745 746 atomic_t refcount; 747 struct completion free; 748 }; 749 750 struct mlx4_srq { 751 void (*event) (struct mlx4_srq *, enum mlx4_event); 752 753 int srqn; 754 int max; 755 int max_gs; 756 int wqe_shift; 757 758 atomic_t refcount; 759 struct completion free; 760 }; 761 762 struct mlx4_av { 763 __be32 port_pd; 764 u8 reserved1; 765 u8 g_slid; 766 __be16 dlid; 767 u8 reserved2; 768 u8 gid_index; 769 u8 stat_rate; 770 u8 hop_limit; 771 __be32 sl_tclass_flowlabel; 772 u8 dgid[16]; 773 }; 774 775 struct mlx4_eth_av { 776 __be32 port_pd; 777 u8 reserved1; 778 u8 smac_idx; 779 u16 reserved2; 780 u8 reserved3; 781 u8 gid_index; 782 u8 stat_rate; 783 u8 hop_limit; 784 __be32 sl_tclass_flowlabel; 785 u8 dgid[16]; 786 u8 s_mac[6]; 787 u8 reserved4[2]; 788 __be16 vlan; 789 u8 mac[ETH_ALEN]; 790 }; 791 792 union mlx4_ext_av { 793 struct mlx4_av ib; 794 struct mlx4_eth_av eth; 795 }; 796 797 /* Counters should be saturate once they reach their maximum value */ 798 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 799 if ((value) > U32_MAX) \ 800 counter = cpu_to_be32(U32_MAX); \ 801 else \ 802 counter = cpu_to_be32(value); \ 803 } while (0) 804 805 struct mlx4_counter { 806 u8 reserved1[3]; 807 u8 counter_mode; 808 __be32 num_ifc; 809 u32 reserved2[2]; 810 __be64 rx_frames; 811 __be64 rx_bytes; 812 __be64 tx_frames; 813 __be64 tx_bytes; 814 }; 815 816 struct mlx4_quotas { 817 int qp; 818 int cq; 819 int srq; 820 int mpt; 821 int mtt; 822 int counter; 823 int xrcd; 824 }; 825 826 struct mlx4_vf_dev { 827 u8 min_port; 828 u8 n_ports; 829 }; 830 831 enum mlx4_pci_status { 832 MLX4_PCI_STATUS_DISABLED, 833 MLX4_PCI_STATUS_ENABLED, 834 }; 835 836 struct mlx4_dev_persistent { 837 struct pci_dev *pdev; 838 struct mlx4_dev *dev; 839 int nvfs[MLX4_MAX_PORTS + 1]; 840 int num_vfs; 841 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 842 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 843 struct work_struct catas_work; 844 struct workqueue_struct *catas_wq; 845 struct mutex device_state_mutex; /* protect HW state */ 846 u8 state; 847 struct mutex interface_state_mutex; /* protect SW state */ 848 u8 interface_state; 849 struct mutex pci_status_mutex; /* sync pci state */ 850 enum mlx4_pci_status pci_status; 851 }; 852 853 struct mlx4_dev { 854 struct mlx4_dev_persistent *persist; 855 unsigned long flags; 856 unsigned long num_slaves; 857 struct mlx4_caps caps; 858 struct mlx4_phys_caps phys_caps; 859 struct mlx4_quotas quotas; 860 struct radix_tree_root qp_table_tree; 861 u8 rev_id; 862 u8 port_random_macs; 863 char board_id[MLX4_BOARD_ID_LEN]; 864 int numa_node; 865 int oper_log_mgm_entry_size; 866 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 867 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 868 struct mlx4_vf_dev *dev_vfs; 869 u8 uar_page_shift; 870 }; 871 872 struct mlx4_clock_params { 873 u64 offset; 874 u8 bar; 875 u8 size; 876 }; 877 878 struct mlx4_eqe { 879 u8 reserved1; 880 u8 type; 881 u8 reserved2; 882 u8 subtype; 883 union { 884 u32 raw[6]; 885 struct { 886 __be32 cqn; 887 } __packed comp; 888 struct { 889 u16 reserved1; 890 __be16 token; 891 u32 reserved2; 892 u8 reserved3[3]; 893 u8 status; 894 __be64 out_param; 895 } __packed cmd; 896 struct { 897 __be32 qpn; 898 } __packed qp; 899 struct { 900 __be32 srqn; 901 } __packed srq; 902 struct { 903 __be32 cqn; 904 u32 reserved1; 905 u8 reserved2[3]; 906 u8 syndrome; 907 } __packed cq_err; 908 struct { 909 u32 reserved1[2]; 910 __be32 port; 911 } __packed port_change; 912 struct { 913 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 914 u32 reserved; 915 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 916 } __packed comm_channel_arm; 917 struct { 918 u8 port; 919 u8 reserved[3]; 920 __be64 mac; 921 } __packed mac_update; 922 struct { 923 __be32 slave_id; 924 } __packed flr_event; 925 struct { 926 __be16 current_temperature; 927 __be16 warning_threshold; 928 } __packed warming; 929 struct { 930 u8 reserved[3]; 931 u8 port; 932 union { 933 struct { 934 __be16 mstr_sm_lid; 935 __be16 port_lid; 936 __be32 changed_attr; 937 u8 reserved[3]; 938 u8 mstr_sm_sl; 939 __be64 gid_prefix; 940 } __packed port_info; 941 struct { 942 __be32 block_ptr; 943 __be32 tbl_entries_mask; 944 } __packed tbl_change_info; 945 } params; 946 } __packed port_mgmt_change; 947 struct { 948 u8 reserved[3]; 949 u8 port; 950 u32 reserved1[5]; 951 } __packed bad_cable; 952 } event; 953 u8 slave_id; 954 u8 reserved3[2]; 955 u8 owner; 956 } __packed; 957 958 struct mlx4_init_port_param { 959 int set_guid0; 960 int set_node_guid; 961 int set_si_guid; 962 u16 mtu; 963 int port_width_cap; 964 u16 vl_cap; 965 u16 max_gid; 966 u16 max_pkey; 967 u64 guid0; 968 u64 node_guid; 969 u64 si_guid; 970 }; 971 972 #define MAD_IFC_DATA_SZ 192 973 /* MAD IFC Mailbox */ 974 struct mlx4_mad_ifc { 975 u8 base_version; 976 u8 mgmt_class; 977 u8 class_version; 978 u8 method; 979 __be16 status; 980 __be16 class_specific; 981 __be64 tid; 982 __be16 attr_id; 983 __be16 resv; 984 __be32 attr_mod; 985 __be64 mkey; 986 __be16 dr_slid; 987 __be16 dr_dlid; 988 u8 reserved[28]; 989 u8 data[MAD_IFC_DATA_SZ]; 990 } __packed; 991 992 #define mlx4_foreach_port(port, dev, type) \ 993 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 994 if ((type) == (dev)->caps.port_mask[(port)]) 995 996 #define mlx4_foreach_ib_transport_port(port, dev) \ 997 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 998 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 999 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \ 1000 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)) 1001 1002 #define MLX4_INVALID_SLAVE_ID 0xFF 1003 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 1004 1005 void handle_port_mgmt_change_event(struct work_struct *work); 1006 1007 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1008 { 1009 return dev->caps.function; 1010 } 1011 1012 static inline int mlx4_is_master(struct mlx4_dev *dev) 1013 { 1014 return dev->flags & MLX4_FLAG_MASTER; 1015 } 1016 1017 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1018 { 1019 return dev->phys_caps.base_sqpn + 8 + 1020 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1021 } 1022 1023 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1024 { 1025 return (qpn < dev->phys_caps.base_sqpn + 8 + 1026 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1027 qpn >= dev->phys_caps.base_sqpn) || 1028 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1029 } 1030 1031 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1032 { 1033 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1034 1035 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1036 return 1; 1037 1038 return 0; 1039 } 1040 1041 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1042 { 1043 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1044 } 1045 1046 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1047 { 1048 return dev->flags & MLX4_FLAG_SLAVE; 1049 } 1050 1051 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1052 { 1053 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1054 } 1055 1056 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1057 struct mlx4_buf *buf, gfp_t gfp); 1058 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1059 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1060 { 1061 if (buf->nbufs == 1) 1062 return buf->direct.buf + offset; 1063 else 1064 return buf->page_list[offset >> PAGE_SHIFT].buf + 1065 (offset & (PAGE_SIZE - 1)); 1066 } 1067 1068 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1069 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1070 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1071 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1072 1073 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1074 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1075 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1076 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1077 1078 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1079 struct mlx4_mtt *mtt); 1080 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1081 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1082 1083 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1084 int npages, int page_shift, struct mlx4_mr *mr); 1085 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1086 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1087 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1088 struct mlx4_mw *mw); 1089 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1090 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1091 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1092 int start_index, int npages, u64 *page_list); 1093 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1094 struct mlx4_buf *buf, gfp_t gfp); 1095 1096 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1097 gfp_t gfp); 1098 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1099 1100 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1101 int size); 1102 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1103 int size); 1104 1105 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1106 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1107 unsigned vector, int collapsed, int timestamp_en); 1108 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1109 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1110 int *base, u8 flags); 1111 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1112 1113 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1114 gfp_t gfp); 1115 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1116 1117 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1118 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1119 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1120 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1121 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1122 1123 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1124 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1125 1126 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1127 int block_mcast_loopback, enum mlx4_protocol prot); 1128 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1129 enum mlx4_protocol prot); 1130 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1131 u8 port, int block_mcast_loopback, 1132 enum mlx4_protocol protocol, u64 *reg_id); 1133 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1134 enum mlx4_protocol protocol, u64 reg_id); 1135 1136 enum { 1137 MLX4_DOMAIN_UVERBS = 0x1000, 1138 MLX4_DOMAIN_ETHTOOL = 0x2000, 1139 MLX4_DOMAIN_RFS = 0x3000, 1140 MLX4_DOMAIN_NIC = 0x5000, 1141 }; 1142 1143 enum mlx4_net_trans_rule_id { 1144 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1145 MLX4_NET_TRANS_RULE_ID_IB, 1146 MLX4_NET_TRANS_RULE_ID_IPV6, 1147 MLX4_NET_TRANS_RULE_ID_IPV4, 1148 MLX4_NET_TRANS_RULE_ID_TCP, 1149 MLX4_NET_TRANS_RULE_ID_UDP, 1150 MLX4_NET_TRANS_RULE_ID_VXLAN, 1151 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1152 }; 1153 1154 extern const u16 __sw_id_hw[]; 1155 1156 static inline int map_hw_to_sw_id(u16 header_id) 1157 { 1158 1159 int i; 1160 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1161 if (header_id == __sw_id_hw[i]) 1162 return i; 1163 } 1164 return -EINVAL; 1165 } 1166 1167 enum mlx4_net_trans_promisc_mode { 1168 MLX4_FS_REGULAR = 1, 1169 MLX4_FS_ALL_DEFAULT, 1170 MLX4_FS_MC_DEFAULT, 1171 MLX4_FS_MIRROR_RX_PORT, 1172 MLX4_FS_MIRROR_SX_PORT, 1173 MLX4_FS_UC_SNIFFER, 1174 MLX4_FS_MC_SNIFFER, 1175 MLX4_FS_MODE_NUM, /* should be last */ 1176 }; 1177 1178 struct mlx4_spec_eth { 1179 u8 dst_mac[ETH_ALEN]; 1180 u8 dst_mac_msk[ETH_ALEN]; 1181 u8 src_mac[ETH_ALEN]; 1182 u8 src_mac_msk[ETH_ALEN]; 1183 u8 ether_type_enable; 1184 __be16 ether_type; 1185 __be16 vlan_id_msk; 1186 __be16 vlan_id; 1187 }; 1188 1189 struct mlx4_spec_tcp_udp { 1190 __be16 dst_port; 1191 __be16 dst_port_msk; 1192 __be16 src_port; 1193 __be16 src_port_msk; 1194 }; 1195 1196 struct mlx4_spec_ipv4 { 1197 __be32 dst_ip; 1198 __be32 dst_ip_msk; 1199 __be32 src_ip; 1200 __be32 src_ip_msk; 1201 }; 1202 1203 struct mlx4_spec_ib { 1204 __be32 l3_qpn; 1205 __be32 qpn_msk; 1206 u8 dst_gid[16]; 1207 u8 dst_gid_msk[16]; 1208 }; 1209 1210 struct mlx4_spec_vxlan { 1211 __be32 vni; 1212 __be32 vni_mask; 1213 1214 }; 1215 1216 struct mlx4_spec_list { 1217 struct list_head list; 1218 enum mlx4_net_trans_rule_id id; 1219 union { 1220 struct mlx4_spec_eth eth; 1221 struct mlx4_spec_ib ib; 1222 struct mlx4_spec_ipv4 ipv4; 1223 struct mlx4_spec_tcp_udp tcp_udp; 1224 struct mlx4_spec_vxlan vxlan; 1225 }; 1226 }; 1227 1228 enum mlx4_net_trans_hw_rule_queue { 1229 MLX4_NET_TRANS_Q_FIFO, 1230 MLX4_NET_TRANS_Q_LIFO, 1231 }; 1232 1233 struct mlx4_net_trans_rule { 1234 struct list_head list; 1235 enum mlx4_net_trans_hw_rule_queue queue_mode; 1236 bool exclusive; 1237 bool allow_loopback; 1238 enum mlx4_net_trans_promisc_mode promisc_mode; 1239 u8 port; 1240 u16 priority; 1241 u32 qpn; 1242 }; 1243 1244 struct mlx4_net_trans_rule_hw_ctrl { 1245 __be16 prio; 1246 u8 type; 1247 u8 flags; 1248 u8 rsvd1; 1249 u8 funcid; 1250 u8 vep; 1251 u8 port; 1252 __be32 qpn; 1253 __be32 rsvd2; 1254 }; 1255 1256 struct mlx4_net_trans_rule_hw_ib { 1257 u8 size; 1258 u8 rsvd1; 1259 __be16 id; 1260 u32 rsvd2; 1261 __be32 l3_qpn; 1262 __be32 qpn_mask; 1263 u8 dst_gid[16]; 1264 u8 dst_gid_msk[16]; 1265 } __packed; 1266 1267 struct mlx4_net_trans_rule_hw_eth { 1268 u8 size; 1269 u8 rsvd; 1270 __be16 id; 1271 u8 rsvd1[6]; 1272 u8 dst_mac[6]; 1273 u16 rsvd2; 1274 u8 dst_mac_msk[6]; 1275 u16 rsvd3; 1276 u8 src_mac[6]; 1277 u16 rsvd4; 1278 u8 src_mac_msk[6]; 1279 u8 rsvd5; 1280 u8 ether_type_enable; 1281 __be16 ether_type; 1282 __be16 vlan_tag_msk; 1283 __be16 vlan_tag; 1284 } __packed; 1285 1286 struct mlx4_net_trans_rule_hw_tcp_udp { 1287 u8 size; 1288 u8 rsvd; 1289 __be16 id; 1290 __be16 rsvd1[3]; 1291 __be16 dst_port; 1292 __be16 rsvd2; 1293 __be16 dst_port_msk; 1294 __be16 rsvd3; 1295 __be16 src_port; 1296 __be16 rsvd4; 1297 __be16 src_port_msk; 1298 } __packed; 1299 1300 struct mlx4_net_trans_rule_hw_ipv4 { 1301 u8 size; 1302 u8 rsvd; 1303 __be16 id; 1304 __be32 rsvd1; 1305 __be32 dst_ip; 1306 __be32 dst_ip_msk; 1307 __be32 src_ip; 1308 __be32 src_ip_msk; 1309 } __packed; 1310 1311 struct mlx4_net_trans_rule_hw_vxlan { 1312 u8 size; 1313 u8 rsvd; 1314 __be16 id; 1315 __be32 rsvd1; 1316 __be32 vni; 1317 __be32 vni_mask; 1318 } __packed; 1319 1320 struct _rule_hw { 1321 union { 1322 struct { 1323 u8 size; 1324 u8 rsvd; 1325 __be16 id; 1326 }; 1327 struct mlx4_net_trans_rule_hw_eth eth; 1328 struct mlx4_net_trans_rule_hw_ib ib; 1329 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1330 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1331 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1332 }; 1333 }; 1334 1335 enum { 1336 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1337 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1338 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1339 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1340 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1341 }; 1342 1343 1344 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1345 enum mlx4_net_trans_promisc_mode mode); 1346 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1347 enum mlx4_net_trans_promisc_mode mode); 1348 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1349 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1350 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1351 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1352 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1353 1354 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1355 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1356 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1357 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1358 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1359 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1360 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1361 u8 promisc); 1362 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1363 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1364 u8 ignore_fcs_value); 1365 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1366 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1367 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1368 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1369 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1370 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1371 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1372 1373 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1374 int npages, u64 iova, u32 *lkey, u32 *rkey); 1375 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1376 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1377 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1378 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1379 u32 *lkey, u32 *rkey); 1380 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1381 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1382 int mlx4_test_interrupts(struct mlx4_dev *dev); 1383 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1384 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1385 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1386 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1387 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1388 1389 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1390 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1391 1392 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1393 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1394 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1395 1396 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1397 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1398 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1399 1400 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1401 int port); 1402 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1403 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1404 int mlx4_flow_attach(struct mlx4_dev *dev, 1405 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1406 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1407 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1408 enum mlx4_net_trans_promisc_mode flow_type); 1409 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1410 enum mlx4_net_trans_rule_id id); 1411 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1412 1413 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1414 int port, int qpn, u16 prio, u64 *reg_id); 1415 1416 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1417 int i, int val); 1418 1419 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1420 1421 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1422 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1423 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1424 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1425 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1426 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1427 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1428 1429 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1430 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1431 1432 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1433 int *slave_id); 1434 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1435 u8 *gid); 1436 1437 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1438 u32 max_range_qpn); 1439 1440 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1441 1442 struct mlx4_active_ports { 1443 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1444 }; 1445 /* Returns a bitmap of the physical ports which are assigned to slave */ 1446 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1447 1448 /* Returns the physical port that represents the virtual port of the slave, */ 1449 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1450 /* mapping is returned. */ 1451 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1452 1453 struct mlx4_slaves_pport { 1454 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1455 }; 1456 /* Returns a bitmap of all slaves that are assigned to port. */ 1457 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1458 int port); 1459 1460 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1461 /* the ports that are set in crit_ports. */ 1462 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1463 struct mlx4_dev *dev, 1464 const struct mlx4_active_ports *crit_ports); 1465 1466 /* Returns the slave's virtual port that represents the physical port. */ 1467 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1468 1469 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1470 1471 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1472 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1473 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1474 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1475 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1476 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1477 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1478 int enable); 1479 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1480 struct mlx4_mpt_entry ***mpt_entry); 1481 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1482 struct mlx4_mpt_entry **mpt_entry); 1483 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1484 u32 pdn); 1485 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1486 struct mlx4_mpt_entry *mpt_entry, 1487 u32 access); 1488 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1489 struct mlx4_mpt_entry **mpt_entry); 1490 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1491 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1492 u64 iova, u64 size, int npages, 1493 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1494 1495 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1496 u16 offset, u16 size, u8 *data); 1497 1498 /* Returns true if running in low memory profile (kdump kernel) */ 1499 static inline bool mlx4_low_memory_profile(void) 1500 { 1501 return is_kdump_kernel(); 1502 } 1503 1504 /* ACCESS REG commands */ 1505 enum mlx4_access_reg_method { 1506 MLX4_ACCESS_REG_QUERY = 0x1, 1507 MLX4_ACCESS_REG_WRITE = 0x2, 1508 }; 1509 1510 /* ACCESS PTYS Reg command */ 1511 enum mlx4_ptys_proto { 1512 MLX4_PTYS_IB = 1<<0, 1513 MLX4_PTYS_EN = 1<<2, 1514 }; 1515 1516 struct mlx4_ptys_reg { 1517 u8 resrvd1; 1518 u8 local_port; 1519 u8 resrvd2; 1520 u8 proto_mask; 1521 __be32 resrvd3[2]; 1522 __be32 eth_proto_cap; 1523 __be16 ib_width_cap; 1524 __be16 ib_speed_cap; 1525 __be32 resrvd4; 1526 __be32 eth_proto_admin; 1527 __be16 ib_width_admin; 1528 __be16 ib_speed_admin; 1529 __be32 resrvd5; 1530 __be32 eth_proto_oper; 1531 __be16 ib_width_oper; 1532 __be16 ib_speed_oper; 1533 __be32 resrvd6; 1534 __be32 eth_proto_lp_adv; 1535 } __packed; 1536 1537 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1538 enum mlx4_access_reg_method method, 1539 struct mlx4_ptys_reg *ptys_reg); 1540 1541 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1542 struct mlx4_clock_params *params); 1543 1544 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1545 { 1546 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1547 } 1548 1549 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1550 { 1551 /* The first 128 UARs are used for EQ doorbells */ 1552 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1553 } 1554 #endif /* MLX4_DEVICE_H */ 1555