1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/atomic.h> 44 45 #include <linux/timecounter.h> 46 47 #define DEFAULT_UAR_PAGE_SHIFT 12 48 49 #define MAX_MSIX_P_PORT 17 50 #define MAX_MSIX 64 51 #define MIN_MSIX_P_PORT 5 52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 53 (dev_cap).num_ports * MIN_MSIX_P_PORT) 54 55 #define MLX4_MAX_100M_UNITS_VAL 255 /* 56 * work around: can't set values 57 * greater then this value when 58 * using 100 Mbps units. 59 */ 60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 62 #define MLX4_RATELIMIT_DEFAULT 0x00ff 63 64 #define MLX4_ROCE_MAX_GIDS 128 65 #define MLX4_ROCE_PF_GIDS 16 66 67 enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 74 MLX4_FLAG_BONDED = 1 << 7 75 }; 76 77 enum { 78 MLX4_PORT_CAP_IS_SM = 1 << 1, 79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 80 }; 81 82 enum { 83 MLX4_MAX_PORTS = 2, 84 MLX4_MAX_PORT_PKEYS = 128, 85 MLX4_MAX_PORT_GIDS = 128 86 }; 87 88 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 89 * These qkeys must not be allowed for general use. This is a 64k range, 90 * and to test for violation, we use the mask (protect against future chg). 91 */ 92 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 93 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 94 95 enum { 96 MLX4_BOARD_ID_LEN = 64 97 }; 98 99 enum { 100 MLX4_MAX_NUM_PF = 16, 101 MLX4_MAX_NUM_VF = 126, 102 MLX4_MAX_NUM_VF_P_PORT = 64, 103 MLX4_MFUNC_MAX = 128, 104 MLX4_MAX_EQ_NUM = 1024, 105 MLX4_MFUNC_EQ_NUM = 4, 106 MLX4_MFUNC_MAX_EQES = 8, 107 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 108 }; 109 110 /* Driver supports 3 diffrent device methods to manage traffic steering: 111 * -device managed - High level API for ib and eth flow steering. FW is 112 * managing flow steering tables. 113 * - B0 steering mode - Common low level API for ib and (if supported) eth. 114 * - A0 steering mode - Limited low level API for eth. In case of IB, 115 * B0 mode is in use. 116 */ 117 enum { 118 MLX4_STEERING_MODE_A0, 119 MLX4_STEERING_MODE_B0, 120 MLX4_STEERING_MODE_DEVICE_MANAGED 121 }; 122 123 enum { 124 MLX4_STEERING_DMFS_A0_DEFAULT, 125 MLX4_STEERING_DMFS_A0_DYNAMIC, 126 MLX4_STEERING_DMFS_A0_STATIC, 127 MLX4_STEERING_DMFS_A0_DISABLE, 128 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 129 }; 130 131 static inline const char *mlx4_steering_mode_str(int steering_mode) 132 { 133 switch (steering_mode) { 134 case MLX4_STEERING_MODE_A0: 135 return "A0 steering"; 136 137 case MLX4_STEERING_MODE_B0: 138 return "B0 steering"; 139 140 case MLX4_STEERING_MODE_DEVICE_MANAGED: 141 return "Device managed flow steering"; 142 143 default: 144 return "Unrecognize steering mode"; 145 } 146 } 147 148 enum { 149 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 150 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 151 }; 152 153 enum { 154 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 155 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 156 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 157 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 158 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 159 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 160 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 161 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 162 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 163 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 164 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 165 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 166 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 167 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 168 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 169 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 170 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 171 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 172 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 173 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 174 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 175 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 176 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 177 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 178 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 179 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 180 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 181 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 182 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 183 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 184 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 185 }; 186 187 enum { 188 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 189 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 190 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 191 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 192 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 193 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 194 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 195 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 196 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 197 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 198 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 199 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 200 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 201 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 202 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 203 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 204 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 205 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 206 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 207 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 208 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 209 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 210 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 211 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 212 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 213 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 214 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 215 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 216 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 217 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 218 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 219 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 220 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 221 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 222 }; 223 224 enum { 225 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 226 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 227 }; 228 229 enum { 230 MLX4_VF_CAP_FLAG_RESET = 1 << 0 231 }; 232 233 /* bit enums for an 8-bit flags field indicating special use 234 * QPs which require special handling in qp_reserve_range. 235 * Currently, this only includes QPs used by the ETH interface, 236 * where we expect to use blueflame. These QPs must not have 237 * bits 6 and 7 set in their qp number. 238 * 239 * This enum may use only bits 0..7. 240 */ 241 enum { 242 MLX4_RESERVE_A0_QP = 1 << 6, 243 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 244 }; 245 246 enum { 247 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 248 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 249 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 250 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 251 }; 252 253 enum { 254 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 255 }; 256 257 enum { 258 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 259 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 260 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 261 }; 262 263 264 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 265 266 enum { 267 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 268 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 269 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 270 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 271 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 272 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 273 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 274 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 275 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 276 }; 277 278 enum { 279 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 280 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 281 }; 282 283 enum mlx4_event { 284 MLX4_EVENT_TYPE_COMP = 0x00, 285 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 286 MLX4_EVENT_TYPE_COMM_EST = 0x02, 287 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 288 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 289 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 290 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 291 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 292 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 293 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 294 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 295 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 296 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 297 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 298 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 299 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 300 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 301 MLX4_EVENT_TYPE_CMD = 0x0a, 302 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 303 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 304 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 305 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 306 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 307 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 308 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 309 MLX4_EVENT_TYPE_NONE = 0xff, 310 }; 311 312 enum { 313 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 314 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 315 }; 316 317 enum { 318 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 319 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 320 }; 321 322 enum { 323 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 324 }; 325 326 enum slave_port_state { 327 SLAVE_PORT_DOWN = 0, 328 SLAVE_PENDING_UP, 329 SLAVE_PORT_UP, 330 }; 331 332 enum slave_port_gen_event { 333 SLAVE_PORT_GEN_EVENT_DOWN = 0, 334 SLAVE_PORT_GEN_EVENT_UP, 335 SLAVE_PORT_GEN_EVENT_NONE, 336 }; 337 338 enum slave_port_state_event { 339 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 340 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 341 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 342 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 343 }; 344 345 enum { 346 MLX4_PERM_LOCAL_READ = 1 << 10, 347 MLX4_PERM_LOCAL_WRITE = 1 << 11, 348 MLX4_PERM_REMOTE_READ = 1 << 12, 349 MLX4_PERM_REMOTE_WRITE = 1 << 13, 350 MLX4_PERM_ATOMIC = 1 << 14, 351 MLX4_PERM_BIND_MW = 1 << 15, 352 MLX4_PERM_MASK = 0xFC00 353 }; 354 355 enum { 356 MLX4_OPCODE_NOP = 0x00, 357 MLX4_OPCODE_SEND_INVAL = 0x01, 358 MLX4_OPCODE_RDMA_WRITE = 0x08, 359 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 360 MLX4_OPCODE_SEND = 0x0a, 361 MLX4_OPCODE_SEND_IMM = 0x0b, 362 MLX4_OPCODE_LSO = 0x0e, 363 MLX4_OPCODE_RDMA_READ = 0x10, 364 MLX4_OPCODE_ATOMIC_CS = 0x11, 365 MLX4_OPCODE_ATOMIC_FA = 0x12, 366 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 367 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 368 MLX4_OPCODE_BIND_MW = 0x18, 369 MLX4_OPCODE_FMR = 0x19, 370 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 371 MLX4_OPCODE_CONFIG_CMD = 0x1f, 372 373 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 374 MLX4_RECV_OPCODE_SEND = 0x01, 375 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 376 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 377 378 MLX4_CQE_OPCODE_ERROR = 0x1e, 379 MLX4_CQE_OPCODE_RESIZE = 0x16, 380 }; 381 382 enum { 383 MLX4_STAT_RATE_OFFSET = 5 384 }; 385 386 enum mlx4_protocol { 387 MLX4_PROT_IB_IPV6 = 0, 388 MLX4_PROT_ETH, 389 MLX4_PROT_IB_IPV4, 390 MLX4_PROT_FCOE 391 }; 392 393 enum { 394 MLX4_MTT_FLAG_PRESENT = 1 395 }; 396 397 enum mlx4_qp_region { 398 MLX4_QP_REGION_FW = 0, 399 MLX4_QP_REGION_RSS_RAW_ETH, 400 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 401 MLX4_QP_REGION_ETH_ADDR, 402 MLX4_QP_REGION_FC_ADDR, 403 MLX4_QP_REGION_FC_EXCH, 404 MLX4_NUM_QP_REGION 405 }; 406 407 enum mlx4_port_type { 408 MLX4_PORT_TYPE_NONE = 0, 409 MLX4_PORT_TYPE_IB = 1, 410 MLX4_PORT_TYPE_ETH = 2, 411 MLX4_PORT_TYPE_AUTO = 3 412 }; 413 414 enum mlx4_special_vlan_idx { 415 MLX4_NO_VLAN_IDX = 0, 416 MLX4_VLAN_MISS_IDX, 417 MLX4_VLAN_REGULAR 418 }; 419 420 enum mlx4_steer_type { 421 MLX4_MC_STEER = 0, 422 MLX4_UC_STEER, 423 MLX4_NUM_STEERS 424 }; 425 426 enum { 427 MLX4_NUM_FEXCH = 64 * 1024, 428 }; 429 430 enum { 431 MLX4_MAX_FAST_REG_PAGES = 511, 432 }; 433 434 enum { 435 /* 436 * Max wqe size for rdma read is 512 bytes, so this 437 * limits our max_sge_rd as the wqe needs to fit: 438 * - ctrl segment (16 bytes) 439 * - rdma segment (16 bytes) 440 * - scatter elements (16 bytes each) 441 */ 442 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 443 }; 444 445 enum { 446 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 447 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 448 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 449 }; 450 451 /* Port mgmt change event handling */ 452 enum { 453 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 454 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 455 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 456 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 457 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 458 }; 459 460 enum { 461 MLX4_DEVICE_STATE_UP = 1 << 0, 462 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 463 }; 464 465 enum { 466 MLX4_INTERFACE_STATE_UP = 1 << 0, 467 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 468 }; 469 470 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 471 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 472 473 enum mlx4_module_id { 474 MLX4_MODULE_ID_SFP = 0x3, 475 MLX4_MODULE_ID_QSFP = 0xC, 476 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 477 MLX4_MODULE_ID_QSFP28 = 0x11, 478 }; 479 480 enum { /* rl */ 481 MLX4_QP_RATE_LIMIT_NONE = 0, 482 MLX4_QP_RATE_LIMIT_KBS = 1, 483 MLX4_QP_RATE_LIMIT_MBS = 2, 484 MLX4_QP_RATE_LIMIT_GBS = 3 485 }; 486 487 struct mlx4_rate_limit_caps { 488 u16 num_rates; /* Number of different rates */ 489 u8 min_unit; 490 u16 min_val; 491 u8 max_unit; 492 u16 max_val; 493 }; 494 495 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 496 { 497 return (major << 32) | (minor << 16) | subminor; 498 } 499 500 struct mlx4_phys_caps { 501 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 502 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 503 u32 num_phys_eqs; 504 u32 base_sqpn; 505 u32 base_proxy_sqpn; 506 u32 base_tunnel_sqpn; 507 }; 508 509 struct mlx4_caps { 510 u64 fw_ver; 511 u32 function; 512 int num_ports; 513 int vl_cap[MLX4_MAX_PORTS + 1]; 514 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 515 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 516 u64 def_mac[MLX4_MAX_PORTS + 1]; 517 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 518 int gid_table_len[MLX4_MAX_PORTS + 1]; 519 int pkey_table_len[MLX4_MAX_PORTS + 1]; 520 int trans_type[MLX4_MAX_PORTS + 1]; 521 int vendor_oui[MLX4_MAX_PORTS + 1]; 522 int wavelength[MLX4_MAX_PORTS + 1]; 523 u64 trans_code[MLX4_MAX_PORTS + 1]; 524 int local_ca_ack_delay; 525 int num_uars; 526 u32 uar_page_size; 527 int bf_reg_size; 528 int bf_regs_per_page; 529 int max_sq_sg; 530 int max_rq_sg; 531 int num_qps; 532 int max_wqes; 533 int max_sq_desc_sz; 534 int max_rq_desc_sz; 535 int max_qp_init_rdma; 536 int max_qp_dest_rdma; 537 u32 *qp0_qkey; 538 u32 *qp0_proxy; 539 u32 *qp1_proxy; 540 u32 *qp0_tunnel; 541 u32 *qp1_tunnel; 542 int num_srqs; 543 int max_srq_wqes; 544 int max_srq_sge; 545 int reserved_srqs; 546 int num_cqs; 547 int max_cqes; 548 int reserved_cqs; 549 int num_sys_eqs; 550 int num_eqs; 551 int reserved_eqs; 552 int num_comp_vectors; 553 int num_mpts; 554 int max_fmr_maps; 555 int num_mtts; 556 int fmr_reserved_mtts; 557 int reserved_mtts; 558 int reserved_mrws; 559 int reserved_uars; 560 int num_mgms; 561 int num_amgms; 562 int reserved_mcgs; 563 int num_qp_per_mgm; 564 int steering_mode; 565 int dmfs_high_steer_mode; 566 int fs_log_max_ucast_qp_range_size; 567 int num_pds; 568 int reserved_pds; 569 int max_xrcds; 570 int reserved_xrcds; 571 int mtt_entry_sz; 572 u32 max_msg_sz; 573 u32 page_size_cap; 574 u64 flags; 575 u64 flags2; 576 u32 bmme_flags; 577 u32 reserved_lkey; 578 u16 stat_rate_support; 579 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 580 int max_gso_sz; 581 int max_rss_tbl_sz; 582 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 583 int reserved_qps; 584 int reserved_qps_base[MLX4_NUM_QP_REGION]; 585 int log_num_macs; 586 int log_num_vlans; 587 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 588 u8 supported_type[MLX4_MAX_PORTS + 1]; 589 u8 suggested_type[MLX4_MAX_PORTS + 1]; 590 u8 default_sense[MLX4_MAX_PORTS + 1]; 591 u32 port_mask[MLX4_MAX_PORTS + 1]; 592 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 593 u32 max_counters; 594 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 595 u16 sqp_demux; 596 u32 eqe_size; 597 u32 cqe_size; 598 u8 eqe_factor; 599 u32 userspace_caps; /* userspace must be aware of these */ 600 u32 function_caps; /* VFs must be aware of these */ 601 u16 hca_core_clock; 602 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 603 int tunnel_offload_mode; 604 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 605 u8 phv_bit[MLX4_MAX_PORTS + 1]; 606 u8 alloc_res_qp_mask; 607 u32 dmfs_high_rate_qpn_base; 608 u32 dmfs_high_rate_qpn_range; 609 u32 vf_caps; 610 struct mlx4_rate_limit_caps rl_caps; 611 }; 612 613 struct mlx4_buf_list { 614 void *buf; 615 dma_addr_t map; 616 }; 617 618 struct mlx4_buf { 619 struct mlx4_buf_list direct; 620 struct mlx4_buf_list *page_list; 621 int nbufs; 622 int npages; 623 int page_shift; 624 }; 625 626 struct mlx4_mtt { 627 u32 offset; 628 int order; 629 int page_shift; 630 }; 631 632 enum { 633 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 634 }; 635 636 struct mlx4_db_pgdir { 637 struct list_head list; 638 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 639 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 640 unsigned long *bits[2]; 641 __be32 *db_page; 642 dma_addr_t db_dma; 643 }; 644 645 struct mlx4_ib_user_db_page; 646 647 struct mlx4_db { 648 __be32 *db; 649 union { 650 struct mlx4_db_pgdir *pgdir; 651 struct mlx4_ib_user_db_page *user_page; 652 } u; 653 dma_addr_t dma; 654 int index; 655 int order; 656 }; 657 658 struct mlx4_hwq_resources { 659 struct mlx4_db db; 660 struct mlx4_mtt mtt; 661 struct mlx4_buf buf; 662 }; 663 664 struct mlx4_mr { 665 struct mlx4_mtt mtt; 666 u64 iova; 667 u64 size; 668 u32 key; 669 u32 pd; 670 u32 access; 671 int enabled; 672 }; 673 674 enum mlx4_mw_type { 675 MLX4_MW_TYPE_1 = 1, 676 MLX4_MW_TYPE_2 = 2, 677 }; 678 679 struct mlx4_mw { 680 u32 key; 681 u32 pd; 682 enum mlx4_mw_type type; 683 int enabled; 684 }; 685 686 struct mlx4_fmr { 687 struct mlx4_mr mr; 688 struct mlx4_mpt_entry *mpt; 689 __be64 *mtts; 690 dma_addr_t dma_handle; 691 int max_pages; 692 int max_maps; 693 int maps; 694 u8 page_shift; 695 }; 696 697 struct mlx4_uar { 698 unsigned long pfn; 699 int index; 700 struct list_head bf_list; 701 unsigned free_bf_bmap; 702 void __iomem *map; 703 void __iomem *bf_map; 704 }; 705 706 struct mlx4_bf { 707 unsigned int offset; 708 int buf_size; 709 struct mlx4_uar *uar; 710 void __iomem *reg; 711 }; 712 713 struct mlx4_cq { 714 void (*comp) (struct mlx4_cq *); 715 void (*event) (struct mlx4_cq *, enum mlx4_event); 716 717 struct mlx4_uar *uar; 718 719 u32 cons_index; 720 721 u16 irq; 722 __be32 *set_ci_db; 723 __be32 *arm_db; 724 int arm_sn; 725 726 int cqn; 727 unsigned vector; 728 729 atomic_t refcount; 730 struct completion free; 731 struct { 732 struct list_head list; 733 void (*comp)(struct mlx4_cq *); 734 void *priv; 735 } tasklet_ctx; 736 int reset_notify_added; 737 struct list_head reset_notify; 738 }; 739 740 struct mlx4_qp { 741 void (*event) (struct mlx4_qp *, enum mlx4_event); 742 743 int qpn; 744 745 atomic_t refcount; 746 struct completion free; 747 }; 748 749 struct mlx4_srq { 750 void (*event) (struct mlx4_srq *, enum mlx4_event); 751 752 int srqn; 753 int max; 754 int max_gs; 755 int wqe_shift; 756 757 atomic_t refcount; 758 struct completion free; 759 }; 760 761 struct mlx4_av { 762 __be32 port_pd; 763 u8 reserved1; 764 u8 g_slid; 765 __be16 dlid; 766 u8 reserved2; 767 u8 gid_index; 768 u8 stat_rate; 769 u8 hop_limit; 770 __be32 sl_tclass_flowlabel; 771 u8 dgid[16]; 772 }; 773 774 struct mlx4_eth_av { 775 __be32 port_pd; 776 u8 reserved1; 777 u8 smac_idx; 778 u16 reserved2; 779 u8 reserved3; 780 u8 gid_index; 781 u8 stat_rate; 782 u8 hop_limit; 783 __be32 sl_tclass_flowlabel; 784 u8 dgid[16]; 785 u8 s_mac[6]; 786 u8 reserved4[2]; 787 __be16 vlan; 788 u8 mac[ETH_ALEN]; 789 }; 790 791 union mlx4_ext_av { 792 struct mlx4_av ib; 793 struct mlx4_eth_av eth; 794 }; 795 796 /* Counters should be saturate once they reach their maximum value */ 797 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 798 if ((value) > U32_MAX) \ 799 counter = cpu_to_be32(U32_MAX); \ 800 else \ 801 counter = cpu_to_be32(value); \ 802 } while (0) 803 804 struct mlx4_counter { 805 u8 reserved1[3]; 806 u8 counter_mode; 807 __be32 num_ifc; 808 u32 reserved2[2]; 809 __be64 rx_frames; 810 __be64 rx_bytes; 811 __be64 tx_frames; 812 __be64 tx_bytes; 813 }; 814 815 struct mlx4_quotas { 816 int qp; 817 int cq; 818 int srq; 819 int mpt; 820 int mtt; 821 int counter; 822 int xrcd; 823 }; 824 825 struct mlx4_vf_dev { 826 u8 min_port; 827 u8 n_ports; 828 }; 829 830 struct mlx4_dev_persistent { 831 struct pci_dev *pdev; 832 struct mlx4_dev *dev; 833 int nvfs[MLX4_MAX_PORTS + 1]; 834 int num_vfs; 835 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 836 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 837 struct work_struct catas_work; 838 struct workqueue_struct *catas_wq; 839 struct mutex device_state_mutex; /* protect HW state */ 840 u8 state; 841 struct mutex interface_state_mutex; /* protect SW state */ 842 u8 interface_state; 843 }; 844 845 struct mlx4_dev { 846 struct mlx4_dev_persistent *persist; 847 unsigned long flags; 848 unsigned long num_slaves; 849 struct mlx4_caps caps; 850 struct mlx4_phys_caps phys_caps; 851 struct mlx4_quotas quotas; 852 struct radix_tree_root qp_table_tree; 853 u8 rev_id; 854 u8 port_random_macs; 855 char board_id[MLX4_BOARD_ID_LEN]; 856 int numa_node; 857 int oper_log_mgm_entry_size; 858 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 859 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 860 struct mlx4_vf_dev *dev_vfs; 861 u8 uar_page_shift; 862 }; 863 864 struct mlx4_clock_params { 865 u64 offset; 866 u8 bar; 867 u8 size; 868 }; 869 870 struct mlx4_eqe { 871 u8 reserved1; 872 u8 type; 873 u8 reserved2; 874 u8 subtype; 875 union { 876 u32 raw[6]; 877 struct { 878 __be32 cqn; 879 } __packed comp; 880 struct { 881 u16 reserved1; 882 __be16 token; 883 u32 reserved2; 884 u8 reserved3[3]; 885 u8 status; 886 __be64 out_param; 887 } __packed cmd; 888 struct { 889 __be32 qpn; 890 } __packed qp; 891 struct { 892 __be32 srqn; 893 } __packed srq; 894 struct { 895 __be32 cqn; 896 u32 reserved1; 897 u8 reserved2[3]; 898 u8 syndrome; 899 } __packed cq_err; 900 struct { 901 u32 reserved1[2]; 902 __be32 port; 903 } __packed port_change; 904 struct { 905 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 906 u32 reserved; 907 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 908 } __packed comm_channel_arm; 909 struct { 910 u8 port; 911 u8 reserved[3]; 912 __be64 mac; 913 } __packed mac_update; 914 struct { 915 __be32 slave_id; 916 } __packed flr_event; 917 struct { 918 __be16 current_temperature; 919 __be16 warning_threshold; 920 } __packed warming; 921 struct { 922 u8 reserved[3]; 923 u8 port; 924 union { 925 struct { 926 __be16 mstr_sm_lid; 927 __be16 port_lid; 928 __be32 changed_attr; 929 u8 reserved[3]; 930 u8 mstr_sm_sl; 931 __be64 gid_prefix; 932 } __packed port_info; 933 struct { 934 __be32 block_ptr; 935 __be32 tbl_entries_mask; 936 } __packed tbl_change_info; 937 } params; 938 } __packed port_mgmt_change; 939 struct { 940 u8 reserved[3]; 941 u8 port; 942 u32 reserved1[5]; 943 } __packed bad_cable; 944 } event; 945 u8 slave_id; 946 u8 reserved3[2]; 947 u8 owner; 948 } __packed; 949 950 struct mlx4_init_port_param { 951 int set_guid0; 952 int set_node_guid; 953 int set_si_guid; 954 u16 mtu; 955 int port_width_cap; 956 u16 vl_cap; 957 u16 max_gid; 958 u16 max_pkey; 959 u64 guid0; 960 u64 node_guid; 961 u64 si_guid; 962 }; 963 964 #define MAD_IFC_DATA_SZ 192 965 /* MAD IFC Mailbox */ 966 struct mlx4_mad_ifc { 967 u8 base_version; 968 u8 mgmt_class; 969 u8 class_version; 970 u8 method; 971 __be16 status; 972 __be16 class_specific; 973 __be64 tid; 974 __be16 attr_id; 975 __be16 resv; 976 __be32 attr_mod; 977 __be64 mkey; 978 __be16 dr_slid; 979 __be16 dr_dlid; 980 u8 reserved[28]; 981 u8 data[MAD_IFC_DATA_SZ]; 982 } __packed; 983 984 #define mlx4_foreach_port(port, dev, type) \ 985 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 986 if ((type) == (dev)->caps.port_mask[(port)]) 987 988 #define mlx4_foreach_ib_transport_port(port, dev) \ 989 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 990 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 991 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \ 992 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)) 993 994 #define MLX4_INVALID_SLAVE_ID 0xFF 995 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 996 997 void handle_port_mgmt_change_event(struct work_struct *work); 998 999 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1000 { 1001 return dev->caps.function; 1002 } 1003 1004 static inline int mlx4_is_master(struct mlx4_dev *dev) 1005 { 1006 return dev->flags & MLX4_FLAG_MASTER; 1007 } 1008 1009 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1010 { 1011 return dev->phys_caps.base_sqpn + 8 + 1012 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1013 } 1014 1015 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1016 { 1017 return (qpn < dev->phys_caps.base_sqpn + 8 + 1018 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1019 qpn >= dev->phys_caps.base_sqpn) || 1020 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1021 } 1022 1023 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1024 { 1025 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1026 1027 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1028 return 1; 1029 1030 return 0; 1031 } 1032 1033 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1034 { 1035 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1036 } 1037 1038 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1039 { 1040 return dev->flags & MLX4_FLAG_SLAVE; 1041 } 1042 1043 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1044 { 1045 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1046 } 1047 1048 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1049 struct mlx4_buf *buf, gfp_t gfp); 1050 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1051 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1052 { 1053 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1054 return buf->direct.buf + offset; 1055 else 1056 return buf->page_list[offset >> PAGE_SHIFT].buf + 1057 (offset & (PAGE_SIZE - 1)); 1058 } 1059 1060 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1061 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1062 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1063 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1064 1065 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1066 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1067 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1068 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1069 1070 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1071 struct mlx4_mtt *mtt); 1072 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1073 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1074 1075 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1076 int npages, int page_shift, struct mlx4_mr *mr); 1077 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1078 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1079 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1080 struct mlx4_mw *mw); 1081 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1082 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1083 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1084 int start_index, int npages, u64 *page_list); 1085 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1086 struct mlx4_buf *buf, gfp_t gfp); 1087 1088 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1089 gfp_t gfp); 1090 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1091 1092 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1093 int size, int max_direct); 1094 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1095 int size); 1096 1097 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1098 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1099 unsigned vector, int collapsed, int timestamp_en); 1100 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1101 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1102 int *base, u8 flags); 1103 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1104 1105 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1106 gfp_t gfp); 1107 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1108 1109 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1110 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1111 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1112 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1113 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1114 1115 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1116 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1117 1118 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1119 int block_mcast_loopback, enum mlx4_protocol prot); 1120 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1121 enum mlx4_protocol prot); 1122 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1123 u8 port, int block_mcast_loopback, 1124 enum mlx4_protocol protocol, u64 *reg_id); 1125 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1126 enum mlx4_protocol protocol, u64 reg_id); 1127 1128 enum { 1129 MLX4_DOMAIN_UVERBS = 0x1000, 1130 MLX4_DOMAIN_ETHTOOL = 0x2000, 1131 MLX4_DOMAIN_RFS = 0x3000, 1132 MLX4_DOMAIN_NIC = 0x5000, 1133 }; 1134 1135 enum mlx4_net_trans_rule_id { 1136 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1137 MLX4_NET_TRANS_RULE_ID_IB, 1138 MLX4_NET_TRANS_RULE_ID_IPV6, 1139 MLX4_NET_TRANS_RULE_ID_IPV4, 1140 MLX4_NET_TRANS_RULE_ID_TCP, 1141 MLX4_NET_TRANS_RULE_ID_UDP, 1142 MLX4_NET_TRANS_RULE_ID_VXLAN, 1143 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1144 }; 1145 1146 extern const u16 __sw_id_hw[]; 1147 1148 static inline int map_hw_to_sw_id(u16 header_id) 1149 { 1150 1151 int i; 1152 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1153 if (header_id == __sw_id_hw[i]) 1154 return i; 1155 } 1156 return -EINVAL; 1157 } 1158 1159 enum mlx4_net_trans_promisc_mode { 1160 MLX4_FS_REGULAR = 1, 1161 MLX4_FS_ALL_DEFAULT, 1162 MLX4_FS_MC_DEFAULT, 1163 MLX4_FS_UC_SNIFFER, 1164 MLX4_FS_MC_SNIFFER, 1165 MLX4_FS_MODE_NUM, /* should be last */ 1166 }; 1167 1168 struct mlx4_spec_eth { 1169 u8 dst_mac[ETH_ALEN]; 1170 u8 dst_mac_msk[ETH_ALEN]; 1171 u8 src_mac[ETH_ALEN]; 1172 u8 src_mac_msk[ETH_ALEN]; 1173 u8 ether_type_enable; 1174 __be16 ether_type; 1175 __be16 vlan_id_msk; 1176 __be16 vlan_id; 1177 }; 1178 1179 struct mlx4_spec_tcp_udp { 1180 __be16 dst_port; 1181 __be16 dst_port_msk; 1182 __be16 src_port; 1183 __be16 src_port_msk; 1184 }; 1185 1186 struct mlx4_spec_ipv4 { 1187 __be32 dst_ip; 1188 __be32 dst_ip_msk; 1189 __be32 src_ip; 1190 __be32 src_ip_msk; 1191 }; 1192 1193 struct mlx4_spec_ib { 1194 __be32 l3_qpn; 1195 __be32 qpn_msk; 1196 u8 dst_gid[16]; 1197 u8 dst_gid_msk[16]; 1198 }; 1199 1200 struct mlx4_spec_vxlan { 1201 __be32 vni; 1202 __be32 vni_mask; 1203 1204 }; 1205 1206 struct mlx4_spec_list { 1207 struct list_head list; 1208 enum mlx4_net_trans_rule_id id; 1209 union { 1210 struct mlx4_spec_eth eth; 1211 struct mlx4_spec_ib ib; 1212 struct mlx4_spec_ipv4 ipv4; 1213 struct mlx4_spec_tcp_udp tcp_udp; 1214 struct mlx4_spec_vxlan vxlan; 1215 }; 1216 }; 1217 1218 enum mlx4_net_trans_hw_rule_queue { 1219 MLX4_NET_TRANS_Q_FIFO, 1220 MLX4_NET_TRANS_Q_LIFO, 1221 }; 1222 1223 struct mlx4_net_trans_rule { 1224 struct list_head list; 1225 enum mlx4_net_trans_hw_rule_queue queue_mode; 1226 bool exclusive; 1227 bool allow_loopback; 1228 enum mlx4_net_trans_promisc_mode promisc_mode; 1229 u8 port; 1230 u16 priority; 1231 u32 qpn; 1232 }; 1233 1234 struct mlx4_net_trans_rule_hw_ctrl { 1235 __be16 prio; 1236 u8 type; 1237 u8 flags; 1238 u8 rsvd1; 1239 u8 funcid; 1240 u8 vep; 1241 u8 port; 1242 __be32 qpn; 1243 __be32 rsvd2; 1244 }; 1245 1246 struct mlx4_net_trans_rule_hw_ib { 1247 u8 size; 1248 u8 rsvd1; 1249 __be16 id; 1250 u32 rsvd2; 1251 __be32 l3_qpn; 1252 __be32 qpn_mask; 1253 u8 dst_gid[16]; 1254 u8 dst_gid_msk[16]; 1255 } __packed; 1256 1257 struct mlx4_net_trans_rule_hw_eth { 1258 u8 size; 1259 u8 rsvd; 1260 __be16 id; 1261 u8 rsvd1[6]; 1262 u8 dst_mac[6]; 1263 u16 rsvd2; 1264 u8 dst_mac_msk[6]; 1265 u16 rsvd3; 1266 u8 src_mac[6]; 1267 u16 rsvd4; 1268 u8 src_mac_msk[6]; 1269 u8 rsvd5; 1270 u8 ether_type_enable; 1271 __be16 ether_type; 1272 __be16 vlan_tag_msk; 1273 __be16 vlan_tag; 1274 } __packed; 1275 1276 struct mlx4_net_trans_rule_hw_tcp_udp { 1277 u8 size; 1278 u8 rsvd; 1279 __be16 id; 1280 __be16 rsvd1[3]; 1281 __be16 dst_port; 1282 __be16 rsvd2; 1283 __be16 dst_port_msk; 1284 __be16 rsvd3; 1285 __be16 src_port; 1286 __be16 rsvd4; 1287 __be16 src_port_msk; 1288 } __packed; 1289 1290 struct mlx4_net_trans_rule_hw_ipv4 { 1291 u8 size; 1292 u8 rsvd; 1293 __be16 id; 1294 __be32 rsvd1; 1295 __be32 dst_ip; 1296 __be32 dst_ip_msk; 1297 __be32 src_ip; 1298 __be32 src_ip_msk; 1299 } __packed; 1300 1301 struct mlx4_net_trans_rule_hw_vxlan { 1302 u8 size; 1303 u8 rsvd; 1304 __be16 id; 1305 __be32 rsvd1; 1306 __be32 vni; 1307 __be32 vni_mask; 1308 } __packed; 1309 1310 struct _rule_hw { 1311 union { 1312 struct { 1313 u8 size; 1314 u8 rsvd; 1315 __be16 id; 1316 }; 1317 struct mlx4_net_trans_rule_hw_eth eth; 1318 struct mlx4_net_trans_rule_hw_ib ib; 1319 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1320 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1321 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1322 }; 1323 }; 1324 1325 enum { 1326 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1327 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1328 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1329 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1330 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1331 }; 1332 1333 1334 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1335 enum mlx4_net_trans_promisc_mode mode); 1336 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1337 enum mlx4_net_trans_promisc_mode mode); 1338 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1339 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1340 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1341 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1342 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1343 1344 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1345 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1346 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1347 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1348 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1349 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1350 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1351 u8 promisc); 1352 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1353 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1354 u8 ignore_fcs_value); 1355 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1356 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1357 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1358 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1359 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1360 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1361 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1362 1363 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1364 int npages, u64 iova, u32 *lkey, u32 *rkey); 1365 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1366 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1367 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1368 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1369 u32 *lkey, u32 *rkey); 1370 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1371 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1372 int mlx4_test_interrupts(struct mlx4_dev *dev); 1373 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1374 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1375 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1376 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1377 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1378 1379 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1380 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1381 1382 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1383 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1384 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1385 1386 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1387 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1388 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1389 1390 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1391 int port); 1392 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1393 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1394 int mlx4_flow_attach(struct mlx4_dev *dev, 1395 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1396 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1397 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1398 enum mlx4_net_trans_promisc_mode flow_type); 1399 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1400 enum mlx4_net_trans_rule_id id); 1401 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1402 1403 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1404 int port, int qpn, u16 prio, u64 *reg_id); 1405 1406 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1407 int i, int val); 1408 1409 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1410 1411 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1412 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1413 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1414 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1415 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1416 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1417 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1418 1419 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1420 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1421 1422 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1423 int *slave_id); 1424 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1425 u8 *gid); 1426 1427 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1428 u32 max_range_qpn); 1429 1430 cycle_t mlx4_read_clock(struct mlx4_dev *dev); 1431 1432 struct mlx4_active_ports { 1433 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1434 }; 1435 /* Returns a bitmap of the physical ports which are assigned to slave */ 1436 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1437 1438 /* Returns the physical port that represents the virtual port of the slave, */ 1439 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1440 /* mapping is returned. */ 1441 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1442 1443 struct mlx4_slaves_pport { 1444 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1445 }; 1446 /* Returns a bitmap of all slaves that are assigned to port. */ 1447 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1448 int port); 1449 1450 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1451 /* the ports that are set in crit_ports. */ 1452 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1453 struct mlx4_dev *dev, 1454 const struct mlx4_active_ports *crit_ports); 1455 1456 /* Returns the slave's virtual port that represents the physical port. */ 1457 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1458 1459 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1460 1461 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1462 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1463 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1464 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1465 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1466 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1467 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1468 int enable); 1469 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1470 struct mlx4_mpt_entry ***mpt_entry); 1471 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1472 struct mlx4_mpt_entry **mpt_entry); 1473 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1474 u32 pdn); 1475 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1476 struct mlx4_mpt_entry *mpt_entry, 1477 u32 access); 1478 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1479 struct mlx4_mpt_entry **mpt_entry); 1480 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1481 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1482 u64 iova, u64 size, int npages, 1483 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1484 1485 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1486 u16 offset, u16 size, u8 *data); 1487 1488 /* Returns true if running in low memory profile (kdump kernel) */ 1489 static inline bool mlx4_low_memory_profile(void) 1490 { 1491 return is_kdump_kernel(); 1492 } 1493 1494 /* ACCESS REG commands */ 1495 enum mlx4_access_reg_method { 1496 MLX4_ACCESS_REG_QUERY = 0x1, 1497 MLX4_ACCESS_REG_WRITE = 0x2, 1498 }; 1499 1500 /* ACCESS PTYS Reg command */ 1501 enum mlx4_ptys_proto { 1502 MLX4_PTYS_IB = 1<<0, 1503 MLX4_PTYS_EN = 1<<2, 1504 }; 1505 1506 struct mlx4_ptys_reg { 1507 u8 resrvd1; 1508 u8 local_port; 1509 u8 resrvd2; 1510 u8 proto_mask; 1511 __be32 resrvd3[2]; 1512 __be32 eth_proto_cap; 1513 __be16 ib_width_cap; 1514 __be16 ib_speed_cap; 1515 __be32 resrvd4; 1516 __be32 eth_proto_admin; 1517 __be16 ib_width_admin; 1518 __be16 ib_speed_admin; 1519 __be32 resrvd5; 1520 __be32 eth_proto_oper; 1521 __be16 ib_width_oper; 1522 __be16 ib_speed_oper; 1523 __be32 resrvd6; 1524 __be32 eth_proto_lp_adv; 1525 } __packed; 1526 1527 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1528 enum mlx4_access_reg_method method, 1529 struct mlx4_ptys_reg *ptys_reg); 1530 1531 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1532 struct mlx4_clock_params *params); 1533 1534 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1535 { 1536 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1537 } 1538 1539 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1540 { 1541 /* The first 128 UARs are used for EQ doorbells */ 1542 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1543 } 1544 #endif /* MLX4_DEVICE_H */ 1545