1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_DEVICE_H 34 #define MLX4_DEVICE_H 35 36 #include <linux/if_ether.h> 37 #include <linux/pci.h> 38 #include <linux/completion.h> 39 #include <linux/radix-tree.h> 40 #include <linux/cpu_rmap.h> 41 #include <linux/crash_dump.h> 42 43 #include <linux/refcount.h> 44 45 #include <linux/timecounter.h> 46 47 #define DEFAULT_UAR_PAGE_SHIFT 12 48 49 #define MAX_MSIX_P_PORT 17 50 #define MAX_MSIX 64 51 #define MIN_MSIX_P_PORT 5 52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 53 (dev_cap).num_ports * MIN_MSIX_P_PORT) 54 55 #define MLX4_MAX_100M_UNITS_VAL 255 /* 56 * work around: can't set values 57 * greater then this value when 58 * using 100 Mbps units. 59 */ 60 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 61 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 62 #define MLX4_RATELIMIT_DEFAULT 0x00ff 63 64 #define MLX4_ROCE_MAX_GIDS 128 65 #define MLX4_ROCE_PF_GIDS 16 66 67 enum { 68 MLX4_FLAG_MSI_X = 1 << 0, 69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 70 MLX4_FLAG_MASTER = 1 << 2, 71 MLX4_FLAG_SLAVE = 1 << 3, 72 MLX4_FLAG_SRIOV = 1 << 4, 73 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 74 MLX4_FLAG_BONDED = 1 << 7, 75 MLX4_FLAG_SECURE_HOST = 1 << 8, 76 }; 77 78 enum { 79 MLX4_PORT_CAP_IS_SM = 1 << 1, 80 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 81 }; 82 83 enum { 84 MLX4_MAX_PORTS = 2, 85 MLX4_MAX_PORT_PKEYS = 128, 86 MLX4_MAX_PORT_GIDS = 128 87 }; 88 89 /* base qkey for use in sriov tunnel-qp/proxy-qp communication. 90 * These qkeys must not be allowed for general use. This is a 64k range, 91 * and to test for violation, we use the mask (protect against future chg). 92 */ 93 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 94 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 95 96 enum { 97 MLX4_BOARD_ID_LEN = 64 98 }; 99 100 enum { 101 MLX4_MAX_NUM_PF = 16, 102 MLX4_MAX_NUM_VF = 126, 103 MLX4_MAX_NUM_VF_P_PORT = 64, 104 MLX4_MFUNC_MAX = 128, 105 MLX4_MAX_EQ_NUM = 1024, 106 MLX4_MFUNC_EQ_NUM = 4, 107 MLX4_MFUNC_MAX_EQES = 8, 108 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 109 }; 110 111 /* Driver supports 3 different device methods to manage traffic steering: 112 * -device managed - High level API for ib and eth flow steering. FW is 113 * managing flow steering tables. 114 * - B0 steering mode - Common low level API for ib and (if supported) eth. 115 * - A0 steering mode - Limited low level API for eth. In case of IB, 116 * B0 mode is in use. 117 */ 118 enum { 119 MLX4_STEERING_MODE_A0, 120 MLX4_STEERING_MODE_B0, 121 MLX4_STEERING_MODE_DEVICE_MANAGED 122 }; 123 124 enum { 125 MLX4_STEERING_DMFS_A0_DEFAULT, 126 MLX4_STEERING_DMFS_A0_DYNAMIC, 127 MLX4_STEERING_DMFS_A0_STATIC, 128 MLX4_STEERING_DMFS_A0_DISABLE, 129 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 130 }; 131 132 static inline const char *mlx4_steering_mode_str(int steering_mode) 133 { 134 switch (steering_mode) { 135 case MLX4_STEERING_MODE_A0: 136 return "A0 steering"; 137 138 case MLX4_STEERING_MODE_B0: 139 return "B0 steering"; 140 141 case MLX4_STEERING_MODE_DEVICE_MANAGED: 142 return "Device managed flow steering"; 143 144 default: 145 return "Unrecognize steering mode"; 146 } 147 } 148 149 enum { 150 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 151 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 152 }; 153 154 enum { 155 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 156 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 157 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 158 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 159 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 160 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 161 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 162 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 163 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 164 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 165 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 166 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 167 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 168 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 169 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 170 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 171 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 172 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 173 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 174 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 175 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 176 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 177 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 178 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 179 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 180 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 181 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 182 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 183 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 184 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 185 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 186 }; 187 188 enum { 189 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 190 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 191 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 192 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 193 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 194 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 195 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 196 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 197 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 198 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 199 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 200 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 201 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 202 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 203 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 204 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 205 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 206 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 207 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 208 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 209 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 210 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 211 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 212 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 213 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 214 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 215 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 216 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 217 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 218 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 219 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 220 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 221 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 222 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 223 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, 224 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35, 225 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36, 226 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37, 227 MLX4_DEV_CAP_FLAG2_USER_MAC_EN = 1ULL << 38, 228 }; 229 230 enum { 231 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 232 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 233 }; 234 235 enum { 236 MLX4_VF_CAP_FLAG_RESET = 1 << 0 237 }; 238 239 /* bit enums for an 8-bit flags field indicating special use 240 * QPs which require special handling in qp_reserve_range. 241 * Currently, this only includes QPs used by the ETH interface, 242 * where we expect to use blueflame. These QPs must not have 243 * bits 6 and 7 set in their qp number. 244 * 245 * This enum may use only bits 0..7. 246 */ 247 enum { 248 MLX4_RESERVE_A0_QP = 1 << 6, 249 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 250 }; 251 252 enum { 253 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 254 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 255 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 256 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 257 }; 258 259 enum { 260 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 261 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 262 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 263 }; 264 265 266 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 267 268 enum { 269 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 270 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 271 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 272 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 273 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 274 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 275 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 276 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 277 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 278 }; 279 280 enum { 281 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 282 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 283 }; 284 285 enum mlx4_event { 286 MLX4_EVENT_TYPE_COMP = 0x00, 287 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 288 MLX4_EVENT_TYPE_COMM_EST = 0x02, 289 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 290 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 291 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 292 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 293 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 294 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 295 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 296 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 297 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 298 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 299 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 300 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 301 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 302 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 303 MLX4_EVENT_TYPE_CMD = 0x0a, 304 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 305 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 306 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 307 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 308 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 309 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 310 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 311 MLX4_EVENT_TYPE_NONE = 0xff, 312 }; 313 314 enum { 315 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 316 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 317 }; 318 319 enum { 320 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 321 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 322 }; 323 324 enum { 325 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 326 }; 327 328 enum slave_port_state { 329 SLAVE_PORT_DOWN = 0, 330 SLAVE_PENDING_UP, 331 SLAVE_PORT_UP, 332 }; 333 334 enum slave_port_gen_event { 335 SLAVE_PORT_GEN_EVENT_DOWN = 0, 336 SLAVE_PORT_GEN_EVENT_UP, 337 SLAVE_PORT_GEN_EVENT_NONE, 338 }; 339 340 enum slave_port_state_event { 341 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 342 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 343 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 344 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 345 }; 346 347 enum { 348 MLX4_PERM_LOCAL_READ = 1 << 10, 349 MLX4_PERM_LOCAL_WRITE = 1 << 11, 350 MLX4_PERM_REMOTE_READ = 1 << 12, 351 MLX4_PERM_REMOTE_WRITE = 1 << 13, 352 MLX4_PERM_ATOMIC = 1 << 14, 353 MLX4_PERM_BIND_MW = 1 << 15, 354 MLX4_PERM_MASK = 0xFC00 355 }; 356 357 enum { 358 MLX4_OPCODE_NOP = 0x00, 359 MLX4_OPCODE_SEND_INVAL = 0x01, 360 MLX4_OPCODE_RDMA_WRITE = 0x08, 361 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 362 MLX4_OPCODE_SEND = 0x0a, 363 MLX4_OPCODE_SEND_IMM = 0x0b, 364 MLX4_OPCODE_LSO = 0x0e, 365 MLX4_OPCODE_RDMA_READ = 0x10, 366 MLX4_OPCODE_ATOMIC_CS = 0x11, 367 MLX4_OPCODE_ATOMIC_FA = 0x12, 368 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 369 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 370 MLX4_OPCODE_BIND_MW = 0x18, 371 MLX4_OPCODE_FMR = 0x19, 372 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 373 MLX4_OPCODE_CONFIG_CMD = 0x1f, 374 375 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 376 MLX4_RECV_OPCODE_SEND = 0x01, 377 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 378 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 379 380 MLX4_CQE_OPCODE_ERROR = 0x1e, 381 MLX4_CQE_OPCODE_RESIZE = 0x16, 382 }; 383 384 enum { 385 MLX4_STAT_RATE_OFFSET = 5 386 }; 387 388 enum mlx4_protocol { 389 MLX4_PROT_IB_IPV6 = 0, 390 MLX4_PROT_ETH, 391 MLX4_PROT_IB_IPV4, 392 MLX4_PROT_FCOE 393 }; 394 395 enum { 396 MLX4_MTT_FLAG_PRESENT = 1 397 }; 398 399 enum mlx4_qp_region { 400 MLX4_QP_REGION_FW = 0, 401 MLX4_QP_REGION_RSS_RAW_ETH, 402 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 403 MLX4_QP_REGION_ETH_ADDR, 404 MLX4_QP_REGION_FC_ADDR, 405 MLX4_QP_REGION_FC_EXCH, 406 MLX4_NUM_QP_REGION 407 }; 408 409 enum mlx4_port_type { 410 MLX4_PORT_TYPE_NONE = 0, 411 MLX4_PORT_TYPE_IB = 1, 412 MLX4_PORT_TYPE_ETH = 2, 413 MLX4_PORT_TYPE_AUTO = 3 414 }; 415 416 enum mlx4_special_vlan_idx { 417 MLX4_NO_VLAN_IDX = 0, 418 MLX4_VLAN_MISS_IDX, 419 MLX4_VLAN_REGULAR 420 }; 421 422 enum mlx4_steer_type { 423 MLX4_MC_STEER = 0, 424 MLX4_UC_STEER, 425 MLX4_NUM_STEERS 426 }; 427 428 enum mlx4_resource_usage { 429 MLX4_RES_USAGE_NONE, 430 MLX4_RES_USAGE_DRIVER, 431 MLX4_RES_USAGE_USER_VERBS, 432 }; 433 434 enum { 435 MLX4_NUM_FEXCH = 64 * 1024, 436 }; 437 438 enum { 439 MLX4_MAX_FAST_REG_PAGES = 511, 440 }; 441 442 enum { 443 /* 444 * Max wqe size for rdma read is 512 bytes, so this 445 * limits our max_sge_rd as the wqe needs to fit: 446 * - ctrl segment (16 bytes) 447 * - rdma segment (16 bytes) 448 * - scatter elements (16 bytes each) 449 */ 450 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 451 }; 452 453 enum { 454 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 455 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 456 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 457 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17, 458 }; 459 460 /* Port mgmt change event handling */ 461 enum { 462 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 463 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 464 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 465 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 466 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 467 }; 468 469 union sl2vl_tbl_to_u64 { 470 u8 sl8[8]; 471 u64 sl64; 472 }; 473 474 enum { 475 MLX4_DEVICE_STATE_UP = 1 << 0, 476 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 477 }; 478 479 enum { 480 MLX4_INTERFACE_STATE_UP = 1 << 0, 481 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 482 MLX4_INTERFACE_STATE_NOWAIT = 1 << 2, 483 }; 484 485 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 486 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 487 488 enum mlx4_module_id { 489 MLX4_MODULE_ID_SFP = 0x3, 490 MLX4_MODULE_ID_QSFP = 0xC, 491 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 492 MLX4_MODULE_ID_QSFP28 = 0x11, 493 }; 494 495 enum { /* rl */ 496 MLX4_QP_RATE_LIMIT_NONE = 0, 497 MLX4_QP_RATE_LIMIT_KBS = 1, 498 MLX4_QP_RATE_LIMIT_MBS = 2, 499 MLX4_QP_RATE_LIMIT_GBS = 3 500 }; 501 502 struct mlx4_rate_limit_caps { 503 u16 num_rates; /* Number of different rates */ 504 u8 min_unit; 505 u16 min_val; 506 u8 max_unit; 507 u16 max_val; 508 }; 509 510 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 511 { 512 return (major << 32) | (minor << 16) | subminor; 513 } 514 515 struct mlx4_phys_caps { 516 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 517 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 518 u32 num_phys_eqs; 519 u32 base_sqpn; 520 u32 base_proxy_sqpn; 521 u32 base_tunnel_sqpn; 522 }; 523 524 struct mlx4_spec_qps { 525 u32 qp0_qkey; 526 u32 qp0_proxy; 527 u32 qp0_tunnel; 528 u32 qp1_proxy; 529 u32 qp1_tunnel; 530 }; 531 532 struct mlx4_caps { 533 u64 fw_ver; 534 u32 function; 535 int num_ports; 536 int vl_cap[MLX4_MAX_PORTS + 1]; 537 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 538 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 539 u64 def_mac[MLX4_MAX_PORTS + 1]; 540 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 541 int gid_table_len[MLX4_MAX_PORTS + 1]; 542 int pkey_table_len[MLX4_MAX_PORTS + 1]; 543 int trans_type[MLX4_MAX_PORTS + 1]; 544 int vendor_oui[MLX4_MAX_PORTS + 1]; 545 int wavelength[MLX4_MAX_PORTS + 1]; 546 u64 trans_code[MLX4_MAX_PORTS + 1]; 547 int local_ca_ack_delay; 548 int num_uars; 549 u32 uar_page_size; 550 int bf_reg_size; 551 int bf_regs_per_page; 552 int max_sq_sg; 553 int max_rq_sg; 554 int num_qps; 555 int max_wqes; 556 int max_sq_desc_sz; 557 int max_rq_desc_sz; 558 int max_qp_init_rdma; 559 int max_qp_dest_rdma; 560 int max_tc_eth; 561 struct mlx4_spec_qps *spec_qps; 562 int num_srqs; 563 int max_srq_wqes; 564 int max_srq_sge; 565 int reserved_srqs; 566 int num_cqs; 567 int max_cqes; 568 int reserved_cqs; 569 int num_sys_eqs; 570 int num_eqs; 571 int reserved_eqs; 572 int num_comp_vectors; 573 int num_mpts; 574 int max_fmr_maps; 575 int num_mtts; 576 int fmr_reserved_mtts; 577 int reserved_mtts; 578 int reserved_mrws; 579 int reserved_uars; 580 int num_mgms; 581 int num_amgms; 582 int reserved_mcgs; 583 int num_qp_per_mgm; 584 int steering_mode; 585 int dmfs_high_steer_mode; 586 int fs_log_max_ucast_qp_range_size; 587 int num_pds; 588 int reserved_pds; 589 int max_xrcds; 590 int reserved_xrcds; 591 int mtt_entry_sz; 592 u32 max_msg_sz; 593 u32 page_size_cap; 594 u64 flags; 595 u64 flags2; 596 u32 bmme_flags; 597 u32 reserved_lkey; 598 u16 stat_rate_support; 599 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 600 int max_gso_sz; 601 int max_rss_tbl_sz; 602 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 603 int reserved_qps; 604 int reserved_qps_base[MLX4_NUM_QP_REGION]; 605 int log_num_macs; 606 int log_num_vlans; 607 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 608 u8 supported_type[MLX4_MAX_PORTS + 1]; 609 u8 suggested_type[MLX4_MAX_PORTS + 1]; 610 u8 default_sense[MLX4_MAX_PORTS + 1]; 611 u32 port_mask[MLX4_MAX_PORTS + 1]; 612 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 613 u32 max_counters; 614 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 615 u16 sqp_demux; 616 u32 eqe_size; 617 u32 cqe_size; 618 u8 eqe_factor; 619 u32 userspace_caps; /* userspace must be aware of these */ 620 u32 function_caps; /* VFs must be aware of these */ 621 u16 hca_core_clock; 622 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 623 int tunnel_offload_mode; 624 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 625 u8 phv_bit[MLX4_MAX_PORTS + 1]; 626 u8 alloc_res_qp_mask; 627 u32 dmfs_high_rate_qpn_base; 628 u32 dmfs_high_rate_qpn_range; 629 u32 vf_caps; 630 bool wol_port[MLX4_MAX_PORTS + 1]; 631 struct mlx4_rate_limit_caps rl_caps; 632 }; 633 634 struct mlx4_buf_list { 635 void *buf; 636 dma_addr_t map; 637 }; 638 639 struct mlx4_buf { 640 struct mlx4_buf_list direct; 641 struct mlx4_buf_list *page_list; 642 int nbufs; 643 int npages; 644 int page_shift; 645 }; 646 647 struct mlx4_mtt { 648 u32 offset; 649 int order; 650 int page_shift; 651 }; 652 653 enum { 654 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 655 }; 656 657 struct mlx4_db_pgdir { 658 struct list_head list; 659 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 660 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 661 unsigned long *bits[2]; 662 __be32 *db_page; 663 dma_addr_t db_dma; 664 }; 665 666 struct mlx4_ib_user_db_page; 667 668 struct mlx4_db { 669 __be32 *db; 670 union { 671 struct mlx4_db_pgdir *pgdir; 672 struct mlx4_ib_user_db_page *user_page; 673 } u; 674 dma_addr_t dma; 675 int index; 676 int order; 677 }; 678 679 struct mlx4_hwq_resources { 680 struct mlx4_db db; 681 struct mlx4_mtt mtt; 682 struct mlx4_buf buf; 683 }; 684 685 struct mlx4_mr { 686 struct mlx4_mtt mtt; 687 u64 iova; 688 u64 size; 689 u32 key; 690 u32 pd; 691 u32 access; 692 int enabled; 693 }; 694 695 enum mlx4_mw_type { 696 MLX4_MW_TYPE_1 = 1, 697 MLX4_MW_TYPE_2 = 2, 698 }; 699 700 struct mlx4_mw { 701 u32 key; 702 u32 pd; 703 enum mlx4_mw_type type; 704 int enabled; 705 }; 706 707 struct mlx4_fmr { 708 struct mlx4_mr mr; 709 struct mlx4_mpt_entry *mpt; 710 __be64 *mtts; 711 dma_addr_t dma_handle; 712 int max_pages; 713 int max_maps; 714 int maps; 715 u8 page_shift; 716 }; 717 718 struct mlx4_uar { 719 unsigned long pfn; 720 int index; 721 struct list_head bf_list; 722 unsigned free_bf_bmap; 723 void __iomem *map; 724 void __iomem *bf_map; 725 }; 726 727 struct mlx4_bf { 728 unsigned int offset; 729 int buf_size; 730 struct mlx4_uar *uar; 731 void __iomem *reg; 732 }; 733 734 struct mlx4_cq { 735 void (*comp) (struct mlx4_cq *); 736 void (*event) (struct mlx4_cq *, enum mlx4_event); 737 738 struct mlx4_uar *uar; 739 740 u32 cons_index; 741 742 u16 irq; 743 __be32 *set_ci_db; 744 __be32 *arm_db; 745 int arm_sn; 746 747 int cqn; 748 unsigned vector; 749 750 refcount_t refcount; 751 struct completion free; 752 struct { 753 struct list_head list; 754 void (*comp)(struct mlx4_cq *); 755 void *priv; 756 } tasklet_ctx; 757 int reset_notify_added; 758 struct list_head reset_notify; 759 u8 usage; 760 }; 761 762 struct mlx4_qp { 763 void (*event) (struct mlx4_qp *, enum mlx4_event); 764 765 int qpn; 766 767 refcount_t refcount; 768 struct completion free; 769 u8 usage; 770 }; 771 772 struct mlx4_srq { 773 void (*event) (struct mlx4_srq *, enum mlx4_event); 774 775 int srqn; 776 int max; 777 int max_gs; 778 int wqe_shift; 779 780 refcount_t refcount; 781 struct completion free; 782 }; 783 784 struct mlx4_av { 785 __be32 port_pd; 786 u8 reserved1; 787 u8 g_slid; 788 __be16 dlid; 789 u8 reserved2; 790 u8 gid_index; 791 u8 stat_rate; 792 u8 hop_limit; 793 __be32 sl_tclass_flowlabel; 794 u8 dgid[16]; 795 }; 796 797 struct mlx4_eth_av { 798 __be32 port_pd; 799 u8 reserved1; 800 u8 smac_idx; 801 u16 reserved2; 802 u8 reserved3; 803 u8 gid_index; 804 u8 stat_rate; 805 u8 hop_limit; 806 __be32 sl_tclass_flowlabel; 807 u8 dgid[16]; 808 u8 s_mac[6]; 809 u8 reserved4[2]; 810 __be16 vlan; 811 u8 mac[ETH_ALEN]; 812 }; 813 814 union mlx4_ext_av { 815 struct mlx4_av ib; 816 struct mlx4_eth_av eth; 817 }; 818 819 /* Counters should be saturate once they reach their maximum value */ 820 #define ASSIGN_32BIT_COUNTER(counter, value) do { \ 821 if ((value) > U32_MAX) \ 822 counter = cpu_to_be32(U32_MAX); \ 823 else \ 824 counter = cpu_to_be32(value); \ 825 } while (0) 826 827 struct mlx4_counter { 828 u8 reserved1[3]; 829 u8 counter_mode; 830 __be32 num_ifc; 831 u32 reserved2[2]; 832 __be64 rx_frames; 833 __be64 rx_bytes; 834 __be64 tx_frames; 835 __be64 tx_bytes; 836 }; 837 838 struct mlx4_quotas { 839 int qp; 840 int cq; 841 int srq; 842 int mpt; 843 int mtt; 844 int counter; 845 int xrcd; 846 }; 847 848 struct mlx4_vf_dev { 849 u8 min_port; 850 u8 n_ports; 851 }; 852 853 enum mlx4_pci_status { 854 MLX4_PCI_STATUS_DISABLED, 855 MLX4_PCI_STATUS_ENABLED, 856 }; 857 858 struct mlx4_dev_persistent { 859 struct pci_dev *pdev; 860 struct mlx4_dev *dev; 861 int nvfs[MLX4_MAX_PORTS + 1]; 862 int num_vfs; 863 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 864 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 865 struct work_struct catas_work; 866 struct workqueue_struct *catas_wq; 867 struct mutex device_state_mutex; /* protect HW state */ 868 u8 state; 869 struct mutex interface_state_mutex; /* protect SW state */ 870 u8 interface_state; 871 struct mutex pci_status_mutex; /* sync pci state */ 872 enum mlx4_pci_status pci_status; 873 }; 874 875 struct mlx4_dev { 876 struct mlx4_dev_persistent *persist; 877 unsigned long flags; 878 unsigned long num_slaves; 879 struct mlx4_caps caps; 880 struct mlx4_phys_caps phys_caps; 881 struct mlx4_quotas quotas; 882 struct radix_tree_root qp_table_tree; 883 u8 rev_id; 884 u8 port_random_macs; 885 char board_id[MLX4_BOARD_ID_LEN]; 886 int numa_node; 887 int oper_log_mgm_entry_size; 888 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 889 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 890 struct mlx4_vf_dev *dev_vfs; 891 u8 uar_page_shift; 892 }; 893 894 struct mlx4_clock_params { 895 u64 offset; 896 u8 bar; 897 u8 size; 898 }; 899 900 struct mlx4_eqe { 901 u8 reserved1; 902 u8 type; 903 u8 reserved2; 904 u8 subtype; 905 union { 906 u32 raw[6]; 907 struct { 908 __be32 cqn; 909 } __packed comp; 910 struct { 911 u16 reserved1; 912 __be16 token; 913 u32 reserved2; 914 u8 reserved3[3]; 915 u8 status; 916 __be64 out_param; 917 } __packed cmd; 918 struct { 919 __be32 qpn; 920 } __packed qp; 921 struct { 922 __be32 srqn; 923 } __packed srq; 924 struct { 925 __be32 cqn; 926 u32 reserved1; 927 u8 reserved2[3]; 928 u8 syndrome; 929 } __packed cq_err; 930 struct { 931 u32 reserved1[2]; 932 __be32 port; 933 } __packed port_change; 934 struct { 935 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 936 u32 reserved; 937 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 938 } __packed comm_channel_arm; 939 struct { 940 u8 port; 941 u8 reserved[3]; 942 __be64 mac; 943 } __packed mac_update; 944 struct { 945 __be32 slave_id; 946 } __packed flr_event; 947 struct { 948 __be16 current_temperature; 949 __be16 warning_threshold; 950 } __packed warming; 951 struct { 952 u8 reserved[3]; 953 u8 port; 954 union { 955 struct { 956 __be16 mstr_sm_lid; 957 __be16 port_lid; 958 __be32 changed_attr; 959 u8 reserved[3]; 960 u8 mstr_sm_sl; 961 __be64 gid_prefix; 962 } __packed port_info; 963 struct { 964 __be32 block_ptr; 965 __be32 tbl_entries_mask; 966 } __packed tbl_change_info; 967 struct { 968 u8 sl2vl_table[8]; 969 } __packed sl2vl_tbl_change_info; 970 } params; 971 } __packed port_mgmt_change; 972 struct { 973 u8 reserved[3]; 974 u8 port; 975 u32 reserved1[5]; 976 } __packed bad_cable; 977 } event; 978 u8 slave_id; 979 u8 reserved3[2]; 980 u8 owner; 981 } __packed; 982 983 struct mlx4_init_port_param { 984 int set_guid0; 985 int set_node_guid; 986 int set_si_guid; 987 u16 mtu; 988 int port_width_cap; 989 u16 vl_cap; 990 u16 max_gid; 991 u16 max_pkey; 992 u64 guid0; 993 u64 node_guid; 994 u64 si_guid; 995 }; 996 997 #define MAD_IFC_DATA_SZ 192 998 /* MAD IFC Mailbox */ 999 struct mlx4_mad_ifc { 1000 u8 base_version; 1001 u8 mgmt_class; 1002 u8 class_version; 1003 u8 method; 1004 __be16 status; 1005 __be16 class_specific; 1006 __be64 tid; 1007 __be16 attr_id; 1008 __be16 resv; 1009 __be32 attr_mod; 1010 __be64 mkey; 1011 __be16 dr_slid; 1012 __be16 dr_dlid; 1013 u8 reserved[28]; 1014 u8 data[MAD_IFC_DATA_SZ]; 1015 } __packed; 1016 1017 #define mlx4_foreach_port(port, dev, type) \ 1018 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1019 if ((type) == (dev)->caps.port_mask[(port)]) 1020 1021 #define mlx4_foreach_ib_transport_port(port, dev) \ 1022 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1023 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 1024 ((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_ETH)) 1025 1026 #define MLX4_INVALID_SLAVE_ID 0xFF 1027 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 1028 1029 void handle_port_mgmt_change_event(struct work_struct *work); 1030 1031 static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1032 { 1033 return dev->caps.function; 1034 } 1035 1036 static inline int mlx4_is_master(struct mlx4_dev *dev) 1037 { 1038 return dev->flags & MLX4_FLAG_MASTER; 1039 } 1040 1041 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1042 { 1043 return dev->phys_caps.base_sqpn + 8 + 1044 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1045 } 1046 1047 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1048 { 1049 return (qpn < dev->phys_caps.base_sqpn + 8 + 1050 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1051 qpn >= dev->phys_caps.base_sqpn) || 1052 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1053 } 1054 1055 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1056 { 1057 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1058 1059 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1060 return 1; 1061 1062 return 0; 1063 } 1064 1065 static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1066 { 1067 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1068 } 1069 1070 static inline int mlx4_is_slave(struct mlx4_dev *dev) 1071 { 1072 return dev->flags & MLX4_FLAG_SLAVE; 1073 } 1074 1075 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1076 { 1077 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1078 } 1079 1080 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1081 struct mlx4_buf *buf); 1082 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1083 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1084 { 1085 if (buf->nbufs == 1) 1086 return buf->direct.buf + offset; 1087 else 1088 return buf->page_list[offset >> PAGE_SHIFT].buf + 1089 (offset & (PAGE_SIZE - 1)); 1090 } 1091 1092 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1093 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1094 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1095 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1096 1097 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1098 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1099 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1100 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1101 1102 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1103 struct mlx4_mtt *mtt); 1104 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1105 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1106 1107 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1108 int npages, int page_shift, struct mlx4_mr *mr); 1109 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1110 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1111 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1112 struct mlx4_mw *mw); 1113 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1114 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1115 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1116 int start_index, int npages, u64 *page_list); 1117 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1118 struct mlx4_buf *buf); 1119 1120 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 1121 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1122 1123 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1124 int size); 1125 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1126 int size); 1127 1128 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1129 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1130 unsigned vector, int collapsed, int timestamp_en); 1131 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1132 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1133 int *base, u8 flags, u8 usage); 1134 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1135 1136 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 1137 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1138 1139 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1140 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1141 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1142 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1143 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1144 1145 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1146 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1147 1148 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1149 int block_mcast_loopback, enum mlx4_protocol prot); 1150 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1151 enum mlx4_protocol prot); 1152 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1153 u8 port, int block_mcast_loopback, 1154 enum mlx4_protocol protocol, u64 *reg_id); 1155 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1156 enum mlx4_protocol protocol, u64 reg_id); 1157 1158 enum { 1159 MLX4_DOMAIN_UVERBS = 0x1000, 1160 MLX4_DOMAIN_ETHTOOL = 0x2000, 1161 MLX4_DOMAIN_RFS = 0x3000, 1162 MLX4_DOMAIN_NIC = 0x5000, 1163 }; 1164 1165 enum mlx4_net_trans_rule_id { 1166 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1167 MLX4_NET_TRANS_RULE_ID_IB, 1168 MLX4_NET_TRANS_RULE_ID_IPV6, 1169 MLX4_NET_TRANS_RULE_ID_IPV4, 1170 MLX4_NET_TRANS_RULE_ID_TCP, 1171 MLX4_NET_TRANS_RULE_ID_UDP, 1172 MLX4_NET_TRANS_RULE_ID_VXLAN, 1173 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1174 }; 1175 1176 extern const u16 __sw_id_hw[]; 1177 1178 static inline int map_hw_to_sw_id(u16 header_id) 1179 { 1180 1181 int i; 1182 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1183 if (header_id == __sw_id_hw[i]) 1184 return i; 1185 } 1186 return -EINVAL; 1187 } 1188 1189 enum mlx4_net_trans_promisc_mode { 1190 MLX4_FS_REGULAR = 1, 1191 MLX4_FS_ALL_DEFAULT, 1192 MLX4_FS_MC_DEFAULT, 1193 MLX4_FS_MIRROR_RX_PORT, 1194 MLX4_FS_MIRROR_SX_PORT, 1195 MLX4_FS_UC_SNIFFER, 1196 MLX4_FS_MC_SNIFFER, 1197 MLX4_FS_MODE_NUM, /* should be last */ 1198 }; 1199 1200 struct mlx4_spec_eth { 1201 u8 dst_mac[ETH_ALEN]; 1202 u8 dst_mac_msk[ETH_ALEN]; 1203 u8 src_mac[ETH_ALEN]; 1204 u8 src_mac_msk[ETH_ALEN]; 1205 u8 ether_type_enable; 1206 __be16 ether_type; 1207 __be16 vlan_id_msk; 1208 __be16 vlan_id; 1209 }; 1210 1211 struct mlx4_spec_tcp_udp { 1212 __be16 dst_port; 1213 __be16 dst_port_msk; 1214 __be16 src_port; 1215 __be16 src_port_msk; 1216 }; 1217 1218 struct mlx4_spec_ipv4 { 1219 __be32 dst_ip; 1220 __be32 dst_ip_msk; 1221 __be32 src_ip; 1222 __be32 src_ip_msk; 1223 }; 1224 1225 struct mlx4_spec_ib { 1226 __be32 l3_qpn; 1227 __be32 qpn_msk; 1228 u8 dst_gid[16]; 1229 u8 dst_gid_msk[16]; 1230 }; 1231 1232 struct mlx4_spec_vxlan { 1233 __be32 vni; 1234 __be32 vni_mask; 1235 1236 }; 1237 1238 struct mlx4_spec_list { 1239 struct list_head list; 1240 enum mlx4_net_trans_rule_id id; 1241 union { 1242 struct mlx4_spec_eth eth; 1243 struct mlx4_spec_ib ib; 1244 struct mlx4_spec_ipv4 ipv4; 1245 struct mlx4_spec_tcp_udp tcp_udp; 1246 struct mlx4_spec_vxlan vxlan; 1247 }; 1248 }; 1249 1250 enum mlx4_net_trans_hw_rule_queue { 1251 MLX4_NET_TRANS_Q_FIFO, 1252 MLX4_NET_TRANS_Q_LIFO, 1253 }; 1254 1255 struct mlx4_net_trans_rule { 1256 struct list_head list; 1257 enum mlx4_net_trans_hw_rule_queue queue_mode; 1258 bool exclusive; 1259 bool allow_loopback; 1260 enum mlx4_net_trans_promisc_mode promisc_mode; 1261 u8 port; 1262 u16 priority; 1263 u32 qpn; 1264 }; 1265 1266 struct mlx4_net_trans_rule_hw_ctrl { 1267 __be16 prio; 1268 u8 type; 1269 u8 flags; 1270 u8 rsvd1; 1271 u8 funcid; 1272 u8 vep; 1273 u8 port; 1274 __be32 qpn; 1275 __be32 rsvd2; 1276 }; 1277 1278 struct mlx4_net_trans_rule_hw_ib { 1279 u8 size; 1280 u8 rsvd1; 1281 __be16 id; 1282 u32 rsvd2; 1283 __be32 l3_qpn; 1284 __be32 qpn_mask; 1285 u8 dst_gid[16]; 1286 u8 dst_gid_msk[16]; 1287 } __packed; 1288 1289 struct mlx4_net_trans_rule_hw_eth { 1290 u8 size; 1291 u8 rsvd; 1292 __be16 id; 1293 u8 rsvd1[6]; 1294 u8 dst_mac[6]; 1295 u16 rsvd2; 1296 u8 dst_mac_msk[6]; 1297 u16 rsvd3; 1298 u8 src_mac[6]; 1299 u16 rsvd4; 1300 u8 src_mac_msk[6]; 1301 u8 rsvd5; 1302 u8 ether_type_enable; 1303 __be16 ether_type; 1304 __be16 vlan_tag_msk; 1305 __be16 vlan_tag; 1306 } __packed; 1307 1308 struct mlx4_net_trans_rule_hw_tcp_udp { 1309 u8 size; 1310 u8 rsvd; 1311 __be16 id; 1312 __be16 rsvd1[3]; 1313 __be16 dst_port; 1314 __be16 rsvd2; 1315 __be16 dst_port_msk; 1316 __be16 rsvd3; 1317 __be16 src_port; 1318 __be16 rsvd4; 1319 __be16 src_port_msk; 1320 } __packed; 1321 1322 struct mlx4_net_trans_rule_hw_ipv4 { 1323 u8 size; 1324 u8 rsvd; 1325 __be16 id; 1326 __be32 rsvd1; 1327 __be32 dst_ip; 1328 __be32 dst_ip_msk; 1329 __be32 src_ip; 1330 __be32 src_ip_msk; 1331 } __packed; 1332 1333 struct mlx4_net_trans_rule_hw_vxlan { 1334 u8 size; 1335 u8 rsvd; 1336 __be16 id; 1337 __be32 rsvd1; 1338 __be32 vni; 1339 __be32 vni_mask; 1340 } __packed; 1341 1342 struct _rule_hw { 1343 union { 1344 struct { 1345 u8 size; 1346 u8 rsvd; 1347 __be16 id; 1348 }; 1349 struct mlx4_net_trans_rule_hw_eth eth; 1350 struct mlx4_net_trans_rule_hw_ib ib; 1351 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1352 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1353 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1354 }; 1355 }; 1356 1357 enum { 1358 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1359 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1360 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1361 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1362 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1363 }; 1364 1365 enum { 1366 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2, 1367 }; 1368 1369 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1370 enum mlx4_net_trans_promisc_mode mode); 1371 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1372 enum mlx4_net_trans_promisc_mode mode); 1373 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1374 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1375 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1376 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1377 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1378 1379 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1380 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1381 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1382 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1383 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1384 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1385 int mlx4_SET_PORT_user_mac(struct mlx4_dev *dev, u8 port, u8 *user_mac); 1386 int mlx4_SET_PORT_user_mtu(struct mlx4_dev *dev, u8 port, u16 user_mtu); 1387 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1388 u8 promisc); 1389 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1390 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1391 u8 ignore_fcs_value); 1392 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1393 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1394 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1395 int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 1396 bool *vlan_offload_disabled); 1397 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 1398 struct _rule_hw *eth_header); 1399 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1400 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1401 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1402 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1403 1404 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1405 int npages, u64 iova, u32 *lkey, u32 *rkey); 1406 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1407 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1408 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1409 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1410 u32 *lkey, u32 *rkey); 1411 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1412 int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1413 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector); 1414 int mlx4_test_async(struct mlx4_dev *dev); 1415 int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 1416 const u32 offset[], u32 value[], 1417 size_t array_len, u8 port); 1418 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1419 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1420 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port); 1421 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1422 void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1423 1424 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1425 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1426 1427 int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1428 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1429 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1430 1431 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage); 1432 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1433 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1434 1435 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1436 int port); 1437 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1438 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1439 int mlx4_flow_attach(struct mlx4_dev *dev, 1440 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1441 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1442 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1443 enum mlx4_net_trans_promisc_mode flow_type); 1444 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1445 enum mlx4_net_trans_rule_id id); 1446 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1447 1448 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1449 int port, int qpn, u16 prio, u64 *reg_id); 1450 1451 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1452 int i, int val); 1453 1454 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1455 1456 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1457 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1458 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1459 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1460 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1461 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1462 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1463 1464 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1465 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1466 1467 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1468 int *slave_id); 1469 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1470 u8 *gid); 1471 1472 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1473 u32 max_range_qpn); 1474 1475 u64 mlx4_read_clock(struct mlx4_dev *dev); 1476 1477 struct mlx4_active_ports { 1478 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1479 }; 1480 /* Returns a bitmap of the physical ports which are assigned to slave */ 1481 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1482 1483 /* Returns the physical port that represents the virtual port of the slave, */ 1484 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1485 /* mapping is returned. */ 1486 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1487 1488 struct mlx4_slaves_pport { 1489 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1490 }; 1491 /* Returns a bitmap of all slaves that are assigned to port. */ 1492 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1493 int port); 1494 1495 /* Returns a bitmap of all slaves that are assigned exactly to all the */ 1496 /* the ports that are set in crit_ports. */ 1497 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1498 struct mlx4_dev *dev, 1499 const struct mlx4_active_ports *crit_ports); 1500 1501 /* Returns the slave's virtual port that represents the physical port. */ 1502 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1503 1504 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1505 1506 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1507 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1508 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1509 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1510 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1511 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1512 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1513 int enable); 1514 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1515 struct mlx4_mpt_entry ***mpt_entry); 1516 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1517 struct mlx4_mpt_entry **mpt_entry); 1518 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1519 u32 pdn); 1520 int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1521 struct mlx4_mpt_entry *mpt_entry, 1522 u32 access); 1523 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1524 struct mlx4_mpt_entry **mpt_entry); 1525 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1526 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1527 u64 iova, u64 size, int npages, 1528 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1529 1530 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1531 u16 offset, u16 size, u8 *data); 1532 int mlx4_max_tc(struct mlx4_dev *dev); 1533 1534 /* Returns true if running in low memory profile (kdump kernel) */ 1535 static inline bool mlx4_low_memory_profile(void) 1536 { 1537 return is_kdump_kernel(); 1538 } 1539 1540 /* ACCESS REG commands */ 1541 enum mlx4_access_reg_method { 1542 MLX4_ACCESS_REG_QUERY = 0x1, 1543 MLX4_ACCESS_REG_WRITE = 0x2, 1544 }; 1545 1546 /* ACCESS PTYS Reg command */ 1547 enum mlx4_ptys_proto { 1548 MLX4_PTYS_IB = 1<<0, 1549 MLX4_PTYS_EN = 1<<2, 1550 }; 1551 1552 enum mlx4_ptys_flags { 1553 MLX4_PTYS_AN_DISABLE_CAP = 1 << 5, 1554 MLX4_PTYS_AN_DISABLE_ADMIN = 1 << 6, 1555 }; 1556 1557 struct mlx4_ptys_reg { 1558 u8 flags; 1559 u8 local_port; 1560 u8 resrvd2; 1561 u8 proto_mask; 1562 __be32 resrvd3[2]; 1563 __be32 eth_proto_cap; 1564 __be16 ib_width_cap; 1565 __be16 ib_speed_cap; 1566 __be32 resrvd4; 1567 __be32 eth_proto_admin; 1568 __be16 ib_width_admin; 1569 __be16 ib_speed_admin; 1570 __be32 resrvd5; 1571 __be32 eth_proto_oper; 1572 __be16 ib_width_oper; 1573 __be16 ib_speed_oper; 1574 __be32 resrvd6; 1575 __be32 eth_proto_lp_adv; 1576 } __packed; 1577 1578 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1579 enum mlx4_access_reg_method method, 1580 struct mlx4_ptys_reg *ptys_reg); 1581 1582 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1583 struct mlx4_clock_params *params); 1584 1585 static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1586 { 1587 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1588 } 1589 1590 static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1591 { 1592 /* The first 128 UARs are used for EQ doorbells */ 1593 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1594 } 1595 #endif /* MLX4_DEVICE_H */ 1596