1 /* 2 * Copyright (c) 2006 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX4_CMD_H 34 #define MLX4_CMD_H 35 36 #include <linux/dma-mapping.h> 37 #include <linux/if_link.h> 38 39 enum { 40 /* initialization and general commands */ 41 MLX4_CMD_SYS_EN = 0x1, 42 MLX4_CMD_SYS_DIS = 0x2, 43 MLX4_CMD_MAP_FA = 0xfff, 44 MLX4_CMD_UNMAP_FA = 0xffe, 45 MLX4_CMD_RUN_FW = 0xff6, 46 MLX4_CMD_MOD_STAT_CFG = 0x34, 47 MLX4_CMD_QUERY_DEV_CAP = 0x3, 48 MLX4_CMD_QUERY_FW = 0x4, 49 MLX4_CMD_ENABLE_LAM = 0xff8, 50 MLX4_CMD_DISABLE_LAM = 0xff7, 51 MLX4_CMD_QUERY_DDR = 0x5, 52 MLX4_CMD_QUERY_ADAPTER = 0x6, 53 MLX4_CMD_INIT_HCA = 0x7, 54 MLX4_CMD_CLOSE_HCA = 0x8, 55 MLX4_CMD_INIT_PORT = 0x9, 56 MLX4_CMD_CLOSE_PORT = 0xa, 57 MLX4_CMD_QUERY_HCA = 0xb, 58 MLX4_CMD_QUERY_PORT = 0x43, 59 MLX4_CMD_SENSE_PORT = 0x4d, 60 MLX4_CMD_HW_HEALTH_CHECK = 0x50, 61 MLX4_CMD_SET_PORT = 0xc, 62 MLX4_CMD_SET_NODE = 0x5a, 63 MLX4_CMD_QUERY_FUNC = 0x56, 64 MLX4_CMD_ACCESS_DDR = 0x2e, 65 MLX4_CMD_MAP_ICM = 0xffa, 66 MLX4_CMD_UNMAP_ICM = 0xff9, 67 MLX4_CMD_MAP_ICM_AUX = 0xffc, 68 MLX4_CMD_UNMAP_ICM_AUX = 0xffb, 69 MLX4_CMD_SET_ICM_SIZE = 0xffd, 70 MLX4_CMD_ACCESS_REG = 0x3b, 71 MLX4_CMD_ALLOCATE_VPP = 0x80, 72 73 /*master notify fw on finish for slave's flr*/ 74 MLX4_CMD_INFORM_FLR_DONE = 0x5b, 75 MLX4_CMD_VIRT_PORT_MAP = 0x5c, 76 MLX4_CMD_GET_OP_REQ = 0x59, 77 78 /* TPT commands */ 79 MLX4_CMD_SW2HW_MPT = 0xd, 80 MLX4_CMD_QUERY_MPT = 0xe, 81 MLX4_CMD_HW2SW_MPT = 0xf, 82 MLX4_CMD_READ_MTT = 0x10, 83 MLX4_CMD_WRITE_MTT = 0x11, 84 MLX4_CMD_SYNC_TPT = 0x2f, 85 86 /* EQ commands */ 87 MLX4_CMD_MAP_EQ = 0x12, 88 MLX4_CMD_SW2HW_EQ = 0x13, 89 MLX4_CMD_HW2SW_EQ = 0x14, 90 MLX4_CMD_QUERY_EQ = 0x15, 91 92 /* CQ commands */ 93 MLX4_CMD_SW2HW_CQ = 0x16, 94 MLX4_CMD_HW2SW_CQ = 0x17, 95 MLX4_CMD_QUERY_CQ = 0x18, 96 MLX4_CMD_MODIFY_CQ = 0x2c, 97 98 /* SRQ commands */ 99 MLX4_CMD_SW2HW_SRQ = 0x35, 100 MLX4_CMD_HW2SW_SRQ = 0x36, 101 MLX4_CMD_QUERY_SRQ = 0x37, 102 MLX4_CMD_ARM_SRQ = 0x40, 103 104 /* QP/EE commands */ 105 MLX4_CMD_RST2INIT_QP = 0x19, 106 MLX4_CMD_INIT2RTR_QP = 0x1a, 107 MLX4_CMD_RTR2RTS_QP = 0x1b, 108 MLX4_CMD_RTS2RTS_QP = 0x1c, 109 MLX4_CMD_SQERR2RTS_QP = 0x1d, 110 MLX4_CMD_2ERR_QP = 0x1e, 111 MLX4_CMD_RTS2SQD_QP = 0x1f, 112 MLX4_CMD_SQD2SQD_QP = 0x38, 113 MLX4_CMD_SQD2RTS_QP = 0x20, 114 MLX4_CMD_2RST_QP = 0x21, 115 MLX4_CMD_QUERY_QP = 0x22, 116 MLX4_CMD_INIT2INIT_QP = 0x2d, 117 MLX4_CMD_SUSPEND_QP = 0x32, 118 MLX4_CMD_UNSUSPEND_QP = 0x33, 119 MLX4_CMD_UPDATE_QP = 0x61, 120 /* special QP and management commands */ 121 MLX4_CMD_CONF_SPECIAL_QP = 0x23, 122 MLX4_CMD_MAD_IFC = 0x24, 123 MLX4_CMD_MAD_DEMUX = 0x203, 124 125 /* multicast commands */ 126 MLX4_CMD_READ_MCG = 0x25, 127 MLX4_CMD_WRITE_MCG = 0x26, 128 MLX4_CMD_MGID_HASH = 0x27, 129 130 /* miscellaneous commands */ 131 MLX4_CMD_DIAG_RPRT = 0x30, 132 MLX4_CMD_NOP = 0x31, 133 MLX4_CMD_CONFIG_DEV = 0x3a, 134 MLX4_CMD_ACCESS_MEM = 0x2e, 135 MLX4_CMD_SET_VEP = 0x52, 136 137 /* Ethernet specific commands */ 138 MLX4_CMD_SET_VLAN_FLTR = 0x47, 139 MLX4_CMD_SET_MCAST_FLTR = 0x48, 140 MLX4_CMD_DUMP_ETH_STATS = 0x49, 141 142 /* Communication channel commands */ 143 MLX4_CMD_ARM_COMM_CHANNEL = 0x57, 144 MLX4_CMD_GEN_EQE = 0x58, 145 146 /* virtual commands */ 147 MLX4_CMD_ALLOC_RES = 0xf00, 148 MLX4_CMD_FREE_RES = 0xf01, 149 MLX4_CMD_MCAST_ATTACH = 0xf05, 150 MLX4_CMD_UCAST_ATTACH = 0xf06, 151 MLX4_CMD_PROMISC = 0xf08, 152 MLX4_CMD_QUERY_FUNC_CAP = 0xf0a, 153 MLX4_CMD_QP_ATTACH = 0xf0b, 154 155 /* debug commands */ 156 MLX4_CMD_QUERY_DEBUG_MSG = 0x2a, 157 MLX4_CMD_SET_DEBUG_MSG = 0x2b, 158 159 /* statistics commands */ 160 MLX4_CMD_QUERY_IF_STAT = 0X54, 161 MLX4_CMD_SET_IF_STAT = 0X55, 162 163 /* register/delete flow steering network rules */ 164 MLX4_QP_FLOW_STEERING_ATTACH = 0x65, 165 MLX4_QP_FLOW_STEERING_DETACH = 0x66, 166 MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64, 167 168 /* Update and read QCN parameters */ 169 MLX4_CMD_CONGESTION_CTRL_OPCODE = 0x68, 170 }; 171 172 enum { 173 MLX4_CMD_TIME_CLASS_A = 60000, 174 MLX4_CMD_TIME_CLASS_B = 60000, 175 MLX4_CMD_TIME_CLASS_C = 60000, 176 }; 177 178 enum { 179 /* virtual to physical port mapping opcode modifiers */ 180 MLX4_GET_PORT_VIRT2PHY = 0x0, 181 MLX4_SET_PORT_VIRT2PHY = 0x1, 182 }; 183 184 enum { 185 MLX4_MAILBOX_SIZE = 4096, 186 MLX4_ACCESS_MEM_ALIGN = 256, 187 }; 188 189 enum { 190 /* set port opcode modifiers */ 191 MLX4_SET_PORT_GENERAL = 0x0, 192 MLX4_SET_PORT_RQP_CALC = 0x1, 193 MLX4_SET_PORT_MAC_TABLE = 0x2, 194 MLX4_SET_PORT_VLAN_TABLE = 0x3, 195 MLX4_SET_PORT_PRIO_MAP = 0x4, 196 MLX4_SET_PORT_GID_TABLE = 0x5, 197 MLX4_SET_PORT_PRIO2TC = 0x8, 198 MLX4_SET_PORT_SCHEDULER = 0x9, 199 MLX4_SET_PORT_VXLAN = 0xB 200 }; 201 202 enum { 203 MLX4_CMD_MAD_DEMUX_CONFIG = 0, 204 MLX4_CMD_MAD_DEMUX_QUERY_STATE = 1, 205 MLX4_CMD_MAD_DEMUX_QUERY_RESTR = 2, /* Query mad demux restrictions */ 206 }; 207 208 enum { 209 MLX4_CMD_WRAPPED, 210 MLX4_CMD_NATIVE 211 }; 212 213 /* 214 * MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP - 215 * Receive checksum value is reported in CQE also for non TCP/UDP packets. 216 * 217 * MLX4_RX_CSUM_MODE_L4 - 218 * L4_CSUM bit in CQE, which indicates whether or not L4 checksum 219 * was validated correctly, is supported. 220 * 221 * MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP - 222 * IP_OK CQE's field is supported also for non TCP/UDP IP packets. 223 * 224 * MLX4_RX_CSUM_MODE_MULTI_VLAN - 225 * Receive Checksum offload is supported for packets with more than 2 vlan headers. 226 */ 227 enum mlx4_rx_csum_mode { 228 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP = 1UL << 0, 229 MLX4_RX_CSUM_MODE_L4 = 1UL << 1, 230 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP = 1UL << 2, 231 MLX4_RX_CSUM_MODE_MULTI_VLAN = 1UL << 3 232 }; 233 234 struct mlx4_config_dev_params { 235 u16 vxlan_udp_dport; 236 u8 rx_csum_flags_port_1; 237 u8 rx_csum_flags_port_2; 238 }; 239 240 enum mlx4_en_congestion_control_algorithm { 241 MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT = 0, 242 }; 243 244 enum mlx4_en_congestion_control_opmod { 245 MLX4_CONGESTION_CONTROL_GET_PARAMS, 246 MLX4_CONGESTION_CONTROL_GET_STATISTICS, 247 MLX4_CONGESTION_CONTROL_SET_PARAMS = 4, 248 }; 249 250 struct mlx4_dev; 251 252 struct mlx4_cmd_mailbox { 253 void *buf; 254 dma_addr_t dma; 255 }; 256 257 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 258 int out_is_imm, u32 in_modifier, u8 op_modifier, 259 u16 op, unsigned long timeout, int native); 260 261 /* Invoke a command with no output parameter */ 262 static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier, 263 u8 op_modifier, u16 op, unsigned long timeout, 264 int native) 265 { 266 return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier, 267 op_modifier, op, timeout, native); 268 } 269 270 /* Invoke a command with an output mailbox */ 271 static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param, 272 u32 in_modifier, u8 op_modifier, u16 op, 273 unsigned long timeout, int native) 274 { 275 return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier, 276 op_modifier, op, timeout, native); 277 } 278 279 /* 280 * Invoke a command with an immediate output parameter (and copy the 281 * output into the caller's out_param pointer after the command 282 * executes). 283 */ 284 static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param, 285 u32 in_modifier, u8 op_modifier, u16 op, 286 unsigned long timeout, int native) 287 { 288 return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier, 289 op_modifier, op, timeout, native); 290 } 291 292 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev); 293 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox); 294 295 u32 mlx4_comm_get_version(void); 296 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac); 297 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos); 298 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting); 299 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf); 300 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state); 301 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 302 struct mlx4_config_dev_params *params); 303 void mlx4_cmd_wake_completions(struct mlx4_dev *dev); 304 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev); 305 /* 306 * mlx4_get_slave_default_vlan - 307 * return true if VST ( default vlan) 308 * if VST, will return vlan & qos (if not NULL) 309 */ 310 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave, 311 u16 *vlan, u8 *qos); 312 313 #define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8) 314 #define COMM_CHAN_EVENT_INTERNAL_ERR (1 << 17) 315 316 #endif /* MLX4_CMD_H */ 317