xref: /linux-6.15/include/linux/mhi.h (revision efe47a18)
10cbf2608SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0 */
20cbf2608SManivannan Sadhasivam /*
30cbf2608SManivannan Sadhasivam  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
40cbf2608SManivannan Sadhasivam  *
50cbf2608SManivannan Sadhasivam  */
60cbf2608SManivannan Sadhasivam #ifndef _MHI_H_
70cbf2608SManivannan Sadhasivam #define _MHI_H_
80cbf2608SManivannan Sadhasivam 
90cbf2608SManivannan Sadhasivam #include <linux/device.h>
100cbf2608SManivannan Sadhasivam #include <linux/dma-direction.h>
110cbf2608SManivannan Sadhasivam #include <linux/mutex.h>
12189ff97cSManivannan Sadhasivam #include <linux/skbuff.h>
130cbf2608SManivannan Sadhasivam #include <linux/slab.h>
14e1427f32SClark Williams #include <linux/spinlock.h>
150cbf2608SManivannan Sadhasivam #include <linux/wait.h>
160cbf2608SManivannan Sadhasivam #include <linux/workqueue.h>
170cbf2608SManivannan Sadhasivam 
188e3729bfSBhaumik Bhatt #define MHI_MAX_OEM_PK_HASH_SEGMENTS 16
198e3729bfSBhaumik Bhatt 
200cbf2608SManivannan Sadhasivam struct mhi_chan;
210cbf2608SManivannan Sadhasivam struct mhi_event;
220cbf2608SManivannan Sadhasivam struct mhi_ctxt;
230cbf2608SManivannan Sadhasivam struct mhi_cmd;
240cbf2608SManivannan Sadhasivam struct mhi_buf_info;
250cbf2608SManivannan Sadhasivam 
260cbf2608SManivannan Sadhasivam /**
270cbf2608SManivannan Sadhasivam  * enum mhi_callback - MHI callback
280cbf2608SManivannan Sadhasivam  * @MHI_CB_IDLE: MHI entered idle state
290cbf2608SManivannan Sadhasivam  * @MHI_CB_PENDING_DATA: New data available for client to process
300cbf2608SManivannan Sadhasivam  * @MHI_CB_LPM_ENTER: MHI host entered low power mode
310cbf2608SManivannan Sadhasivam  * @MHI_CB_LPM_EXIT: MHI host about to exit low power mode
320cbf2608SManivannan Sadhasivam  * @MHI_CB_EE_RDDM: MHI device entered RDDM exec env
330cbf2608SManivannan Sadhasivam  * @MHI_CB_EE_MISSION_MODE: MHI device entered Mission Mode exec env
340cbf2608SManivannan Sadhasivam  * @MHI_CB_SYS_ERROR: MHI device entered error state (may recover)
350cbf2608SManivannan Sadhasivam  * @MHI_CB_FATAL_ERROR: MHI device entered fatal error state
361d3173a3SManivannan Sadhasivam  * @MHI_CB_BW_REQ: Received a bandwidth switch request from device
370cbf2608SManivannan Sadhasivam  */
380cbf2608SManivannan Sadhasivam enum mhi_callback {
390cbf2608SManivannan Sadhasivam 	MHI_CB_IDLE,
400cbf2608SManivannan Sadhasivam 	MHI_CB_PENDING_DATA,
410cbf2608SManivannan Sadhasivam 	MHI_CB_LPM_ENTER,
420cbf2608SManivannan Sadhasivam 	MHI_CB_LPM_EXIT,
430cbf2608SManivannan Sadhasivam 	MHI_CB_EE_RDDM,
440cbf2608SManivannan Sadhasivam 	MHI_CB_EE_MISSION_MODE,
450cbf2608SManivannan Sadhasivam 	MHI_CB_SYS_ERROR,
460cbf2608SManivannan Sadhasivam 	MHI_CB_FATAL_ERROR,
471d3173a3SManivannan Sadhasivam 	MHI_CB_BW_REQ,
480cbf2608SManivannan Sadhasivam };
490cbf2608SManivannan Sadhasivam 
500cbf2608SManivannan Sadhasivam /**
510cbf2608SManivannan Sadhasivam  * enum mhi_flags - Transfer flags
520cbf2608SManivannan Sadhasivam  * @MHI_EOB: End of buffer for bulk transfer
530cbf2608SManivannan Sadhasivam  * @MHI_EOT: End of transfer
540cbf2608SManivannan Sadhasivam  * @MHI_CHAIN: Linked transfer
550cbf2608SManivannan Sadhasivam  */
560cbf2608SManivannan Sadhasivam enum mhi_flags {
57115f3251SManivannan Sadhasivam 	MHI_EOB = BIT(0),
58115f3251SManivannan Sadhasivam 	MHI_EOT = BIT(1),
59115f3251SManivannan Sadhasivam 	MHI_CHAIN = BIT(2),
600cbf2608SManivannan Sadhasivam };
610cbf2608SManivannan Sadhasivam 
620cbf2608SManivannan Sadhasivam /**
630cbf2608SManivannan Sadhasivam  * enum mhi_device_type - Device types
640cbf2608SManivannan Sadhasivam  * @MHI_DEVICE_XFER: Handles data transfer
650cbf2608SManivannan Sadhasivam  * @MHI_DEVICE_CONTROLLER: Control device
660cbf2608SManivannan Sadhasivam  */
670cbf2608SManivannan Sadhasivam enum mhi_device_type {
680cbf2608SManivannan Sadhasivam 	MHI_DEVICE_XFER,
690cbf2608SManivannan Sadhasivam 	MHI_DEVICE_CONTROLLER,
700cbf2608SManivannan Sadhasivam };
710cbf2608SManivannan Sadhasivam 
720cbf2608SManivannan Sadhasivam /**
730cbf2608SManivannan Sadhasivam  * enum mhi_ch_type - Channel types
740cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_INVALID: Invalid channel type
750cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_OUTBOUND: Outbound channel to the device
760cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_INBOUND: Inbound channel from the device
770cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_INBOUND_COALESCED: Coalesced channel for the device to combine
780cbf2608SManivannan Sadhasivam  *				   multiple packets and send them as a single
790cbf2608SManivannan Sadhasivam  *				   large packet to reduce CPU consumption
800cbf2608SManivannan Sadhasivam  */
810cbf2608SManivannan Sadhasivam enum mhi_ch_type {
820cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_INVALID = 0,
830cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_OUTBOUND = DMA_TO_DEVICE,
840cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_INBOUND = DMA_FROM_DEVICE,
850cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_INBOUND_COALESCED = 3,
860cbf2608SManivannan Sadhasivam };
870cbf2608SManivannan Sadhasivam 
880cbf2608SManivannan Sadhasivam /**
894d12a897SRandy Dunlap  * struct image_info - Firmware and RDDM table
904d12a897SRandy Dunlap  * @mhi_buf: Buffer for firmware and RDDM table
914d12a897SRandy Dunlap  * @entries: # of entries in table
923000f85bSManivannan Sadhasivam  */
933000f85bSManivannan Sadhasivam struct image_info {
943000f85bSManivannan Sadhasivam 	struct mhi_buf *mhi_buf;
954d12a897SRandy Dunlap 	/* private: from internal.h */
963000f85bSManivannan Sadhasivam 	struct bhi_vec_entry *bhi_vec;
974d12a897SRandy Dunlap 	/* public: */
983000f85bSManivannan Sadhasivam 	u32 entries;
993000f85bSManivannan Sadhasivam };
1003000f85bSManivannan Sadhasivam 
1013000f85bSManivannan Sadhasivam /**
1021d3173a3SManivannan Sadhasivam  * struct mhi_link_info - BW requirement
1031d3173a3SManivannan Sadhasivam  * target_link_speed - Link speed as defined by TLS bits in LinkControl reg
1041d3173a3SManivannan Sadhasivam  * target_link_width - Link width as defined by NLW bits in LinkStatus reg
1051d3173a3SManivannan Sadhasivam  */
1061d3173a3SManivannan Sadhasivam struct mhi_link_info {
1071d3173a3SManivannan Sadhasivam 	unsigned int target_link_speed;
1081d3173a3SManivannan Sadhasivam 	unsigned int target_link_width;
1091d3173a3SManivannan Sadhasivam };
1101d3173a3SManivannan Sadhasivam 
1111d3173a3SManivannan Sadhasivam /**
1120cbf2608SManivannan Sadhasivam  * enum mhi_ee_type - Execution environment types
1130cbf2608SManivannan Sadhasivam  * @MHI_EE_PBL: Primary Bootloader
1140cbf2608SManivannan Sadhasivam  * @MHI_EE_SBL: Secondary Bootloader
1150cbf2608SManivannan Sadhasivam  * @MHI_EE_AMSS: Modem, aka the primary runtime EE
1160cbf2608SManivannan Sadhasivam  * @MHI_EE_RDDM: Ram dump download mode
1170cbf2608SManivannan Sadhasivam  * @MHI_EE_WFW: WLAN firmware mode
1180cbf2608SManivannan Sadhasivam  * @MHI_EE_PTHRU: Passthrough
1190cbf2608SManivannan Sadhasivam  * @MHI_EE_EDL: Embedded downloader
12066ac7985SCarl Yin  * @MHI_EE_FP: Flash Programmer Environment
1210cbf2608SManivannan Sadhasivam  */
1220cbf2608SManivannan Sadhasivam enum mhi_ee_type {
1230cbf2608SManivannan Sadhasivam 	MHI_EE_PBL,
1240cbf2608SManivannan Sadhasivam 	MHI_EE_SBL,
1250cbf2608SManivannan Sadhasivam 	MHI_EE_AMSS,
1260cbf2608SManivannan Sadhasivam 	MHI_EE_RDDM,
1270cbf2608SManivannan Sadhasivam 	MHI_EE_WFW,
1280cbf2608SManivannan Sadhasivam 	MHI_EE_PTHRU,
1290cbf2608SManivannan Sadhasivam 	MHI_EE_EDL,
13066ac7985SCarl Yin 	MHI_EE_FP,
13166ac7985SCarl Yin 	MHI_EE_MAX_SUPPORTED = MHI_EE_FP,
1320cbf2608SManivannan Sadhasivam 	MHI_EE_DISABLE_TRANSITION, /* local EE, not related to mhi spec */
1330cbf2608SManivannan Sadhasivam 	MHI_EE_NOT_SUPPORTED,
1340cbf2608SManivannan Sadhasivam 	MHI_EE_MAX,
1350cbf2608SManivannan Sadhasivam };
1360cbf2608SManivannan Sadhasivam 
1370cbf2608SManivannan Sadhasivam /**
138a6e2e352SManivannan Sadhasivam  * enum mhi_state - MHI states
139a6e2e352SManivannan Sadhasivam  * @MHI_STATE_RESET: Reset state
140a6e2e352SManivannan Sadhasivam  * @MHI_STATE_READY: Ready state
141a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M0: M0 state
142a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M1: M1 state
143a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M2: M2 state
144a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M3: M3 state
145a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M3_FAST: M3 Fast state
146a6e2e352SManivannan Sadhasivam  * @MHI_STATE_BHI: BHI state
147a6e2e352SManivannan Sadhasivam  * @MHI_STATE_SYS_ERR: System Error state
148a6e2e352SManivannan Sadhasivam  */
149a6e2e352SManivannan Sadhasivam enum mhi_state {
150a6e2e352SManivannan Sadhasivam 	MHI_STATE_RESET = 0x0,
151a6e2e352SManivannan Sadhasivam 	MHI_STATE_READY = 0x1,
152a6e2e352SManivannan Sadhasivam 	MHI_STATE_M0 = 0x2,
153a6e2e352SManivannan Sadhasivam 	MHI_STATE_M1 = 0x3,
154a6e2e352SManivannan Sadhasivam 	MHI_STATE_M2 = 0x4,
155a6e2e352SManivannan Sadhasivam 	MHI_STATE_M3 = 0x5,
156a6e2e352SManivannan Sadhasivam 	MHI_STATE_M3_FAST = 0x6,
157a6e2e352SManivannan Sadhasivam 	MHI_STATE_BHI = 0x7,
158a6e2e352SManivannan Sadhasivam 	MHI_STATE_SYS_ERR = 0xFF,
159a6e2e352SManivannan Sadhasivam 	MHI_STATE_MAX,
160a6e2e352SManivannan Sadhasivam };
161a6e2e352SManivannan Sadhasivam 
162a6e2e352SManivannan Sadhasivam /**
1630cbf2608SManivannan Sadhasivam  * enum mhi_ch_ee_mask - Execution environment mask for channel
1640cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_PBL: Allow channel to be used in PBL EE
1650cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_SBL: Allow channel to be used in SBL EE
1660cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_AMSS: Allow channel to be used in AMSS EE
1670cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_RDDM: Allow channel to be used in RDDM EE
1680cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_PTHRU: Allow channel to be used in PTHRU EE
1690cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_WFW: Allow channel to be used in WFW EE
1700cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_EDL: Allow channel to be used in EDL EE
1710cbf2608SManivannan Sadhasivam  */
1720cbf2608SManivannan Sadhasivam enum mhi_ch_ee_mask {
1730cbf2608SManivannan Sadhasivam 	MHI_CH_EE_PBL = BIT(MHI_EE_PBL),
1740cbf2608SManivannan Sadhasivam 	MHI_CH_EE_SBL = BIT(MHI_EE_SBL),
1750cbf2608SManivannan Sadhasivam 	MHI_CH_EE_AMSS = BIT(MHI_EE_AMSS),
1760cbf2608SManivannan Sadhasivam 	MHI_CH_EE_RDDM = BIT(MHI_EE_RDDM),
1770cbf2608SManivannan Sadhasivam 	MHI_CH_EE_PTHRU = BIT(MHI_EE_PTHRU),
1780cbf2608SManivannan Sadhasivam 	MHI_CH_EE_WFW = BIT(MHI_EE_WFW),
1790cbf2608SManivannan Sadhasivam 	MHI_CH_EE_EDL = BIT(MHI_EE_EDL),
1800cbf2608SManivannan Sadhasivam };
1810cbf2608SManivannan Sadhasivam 
1820cbf2608SManivannan Sadhasivam /**
1830cbf2608SManivannan Sadhasivam  * enum mhi_er_data_type - Event ring data types
1840cbf2608SManivannan Sadhasivam  * @MHI_ER_DATA: Only client data over this ring
1850cbf2608SManivannan Sadhasivam  * @MHI_ER_CTRL: MHI control data and client data
1860cbf2608SManivannan Sadhasivam  */
1870cbf2608SManivannan Sadhasivam enum mhi_er_data_type {
1880cbf2608SManivannan Sadhasivam 	MHI_ER_DATA,
1890cbf2608SManivannan Sadhasivam 	MHI_ER_CTRL,
1900cbf2608SManivannan Sadhasivam };
1910cbf2608SManivannan Sadhasivam 
1920cbf2608SManivannan Sadhasivam /**
1930cbf2608SManivannan Sadhasivam  * enum mhi_db_brst_mode - Doorbell mode
1940cbf2608SManivannan Sadhasivam  * @MHI_DB_BRST_DISABLE: Burst mode disable
1950cbf2608SManivannan Sadhasivam  * @MHI_DB_BRST_ENABLE: Burst mode enable
1960cbf2608SManivannan Sadhasivam  */
1970cbf2608SManivannan Sadhasivam enum mhi_db_brst_mode {
1980cbf2608SManivannan Sadhasivam 	MHI_DB_BRST_DISABLE = 0x2,
1990cbf2608SManivannan Sadhasivam 	MHI_DB_BRST_ENABLE = 0x3,
2000cbf2608SManivannan Sadhasivam };
2010cbf2608SManivannan Sadhasivam 
2020cbf2608SManivannan Sadhasivam /**
2030cbf2608SManivannan Sadhasivam  * struct mhi_channel_config - Channel configuration structure for controller
2040cbf2608SManivannan Sadhasivam  * @name: The name of this channel
2050cbf2608SManivannan Sadhasivam  * @num: The number assigned to this channel
2060cbf2608SManivannan Sadhasivam  * @num_elements: The number of elements that can be queued to this channel
2070cbf2608SManivannan Sadhasivam  * @local_elements: The local ring length of the channel
208a503d162SJarvis Jiang  * @event_ring: The event ring index that services this channel
2090cbf2608SManivannan Sadhasivam  * @dir: Direction that data may flow on this channel
2100cbf2608SManivannan Sadhasivam  * @type: Channel type
2110cbf2608SManivannan Sadhasivam  * @ee_mask: Execution Environment mask for this channel
2120cbf2608SManivannan Sadhasivam  * @pollcfg: Polling configuration for burst mode.  0 is default.  milliseconds
2130cbf2608SManivannan Sadhasivam 	     for UL channels, multiple of 8 ring elements for DL channels
2140cbf2608SManivannan Sadhasivam  * @doorbell: Doorbell mode
2150cbf2608SManivannan Sadhasivam  * @lpm_notify: The channel master requires low power mode notifications
2160cbf2608SManivannan Sadhasivam  * @offload_channel: The client manages the channel completely
2170cbf2608SManivannan Sadhasivam  * @doorbell_mode_switch: Channel switches to doorbell mode on M0 transition
2180cbf2608SManivannan Sadhasivam  * @auto_queue: Framework will automatically queue buffers for DL traffic
219da1c4f85SManivannan Sadhasivam  * @wake-capable: Channel capable of waking up the system
2200cbf2608SManivannan Sadhasivam  */
2210cbf2608SManivannan Sadhasivam struct mhi_channel_config {
2220cbf2608SManivannan Sadhasivam 	char *name;
2230cbf2608SManivannan Sadhasivam 	u32 num;
2240cbf2608SManivannan Sadhasivam 	u32 num_elements;
2250cbf2608SManivannan Sadhasivam 	u32 local_elements;
2260cbf2608SManivannan Sadhasivam 	u32 event_ring;
2270cbf2608SManivannan Sadhasivam 	enum dma_data_direction dir;
2280cbf2608SManivannan Sadhasivam 	enum mhi_ch_type type;
2290cbf2608SManivannan Sadhasivam 	u32 ee_mask;
2300cbf2608SManivannan Sadhasivam 	u32 pollcfg;
2310cbf2608SManivannan Sadhasivam 	enum mhi_db_brst_mode doorbell;
2320cbf2608SManivannan Sadhasivam 	bool lpm_notify;
2330cbf2608SManivannan Sadhasivam 	bool offload_channel;
2340cbf2608SManivannan Sadhasivam 	bool doorbell_mode_switch;
2350cbf2608SManivannan Sadhasivam 	bool auto_queue;
236da1c4f85SManivannan Sadhasivam 	bool wake_capable;
2370cbf2608SManivannan Sadhasivam };
2380cbf2608SManivannan Sadhasivam 
2390cbf2608SManivannan Sadhasivam /**
2400cbf2608SManivannan Sadhasivam  * struct mhi_event_config - Event ring configuration structure for controller
2410cbf2608SManivannan Sadhasivam  * @num_elements: The number of elements that can be queued to this ring
2420cbf2608SManivannan Sadhasivam  * @irq_moderation_ms: Delay irq for additional events to be aggregated
2430cbf2608SManivannan Sadhasivam  * @irq: IRQ associated with this ring
2440cbf2608SManivannan Sadhasivam  * @channel: Dedicated channel number. U32_MAX indicates a non-dedicated ring
2450cbf2608SManivannan Sadhasivam  * @priority: Priority of this ring. Use 1 for now
2460cbf2608SManivannan Sadhasivam  * @mode: Doorbell mode
2470cbf2608SManivannan Sadhasivam  * @data_type: Type of data this ring will process
2480cbf2608SManivannan Sadhasivam  * @hardware_event: This ring is associated with hardware channels
2490cbf2608SManivannan Sadhasivam  * @client_managed: This ring is client managed
2500cbf2608SManivannan Sadhasivam  * @offload_channel: This ring is associated with an offloaded channel
2510cbf2608SManivannan Sadhasivam  */
2520cbf2608SManivannan Sadhasivam struct mhi_event_config {
2530cbf2608SManivannan Sadhasivam 	u32 num_elements;
2540cbf2608SManivannan Sadhasivam 	u32 irq_moderation_ms;
2550cbf2608SManivannan Sadhasivam 	u32 irq;
2560cbf2608SManivannan Sadhasivam 	u32 channel;
2570cbf2608SManivannan Sadhasivam 	u32 priority;
2580cbf2608SManivannan Sadhasivam 	enum mhi_db_brst_mode mode;
2590cbf2608SManivannan Sadhasivam 	enum mhi_er_data_type data_type;
2600cbf2608SManivannan Sadhasivam 	bool hardware_event;
2610cbf2608SManivannan Sadhasivam 	bool client_managed;
2620cbf2608SManivannan Sadhasivam 	bool offload_channel;
2630cbf2608SManivannan Sadhasivam };
2640cbf2608SManivannan Sadhasivam 
2650cbf2608SManivannan Sadhasivam /**
2660cbf2608SManivannan Sadhasivam  * struct mhi_controller_config - Root MHI controller configuration
2670cbf2608SManivannan Sadhasivam  * @max_channels: Maximum number of channels supported
2680cbf2608SManivannan Sadhasivam  * @timeout_ms: Timeout value for operations. 0 means use default
2690cbf2608SManivannan Sadhasivam  * @buf_len: Size of automatically allocated buffers. 0 means use default
2700cbf2608SManivannan Sadhasivam  * @num_channels: Number of channels defined in @ch_cfg
2710cbf2608SManivannan Sadhasivam  * @ch_cfg: Array of defined channels
2720cbf2608SManivannan Sadhasivam  * @num_events: Number of event rings defined in @event_cfg
2730cbf2608SManivannan Sadhasivam  * @event_cfg: Array of defined event rings
2740cbf2608SManivannan Sadhasivam  * @use_bounce_buf: Use a bounce buffer pool due to limited DDR access
2750cbf2608SManivannan Sadhasivam  * @m2_no_db: Host is not allowed to ring DB in M2 state
2760cbf2608SManivannan Sadhasivam  */
2770cbf2608SManivannan Sadhasivam struct mhi_controller_config {
2780cbf2608SManivannan Sadhasivam 	u32 max_channels;
2790cbf2608SManivannan Sadhasivam 	u32 timeout_ms;
2800cbf2608SManivannan Sadhasivam 	u32 buf_len;
2810cbf2608SManivannan Sadhasivam 	u32 num_channels;
282f38173a7SHemant Kumar 	const struct mhi_channel_config *ch_cfg;
2830cbf2608SManivannan Sadhasivam 	u32 num_events;
284fcba4b20SLoic Poulain 	struct mhi_event_config *event_cfg;
2850cbf2608SManivannan Sadhasivam 	bool use_bounce_buf;
2860cbf2608SManivannan Sadhasivam 	bool m2_no_db;
2870cbf2608SManivannan Sadhasivam };
2880cbf2608SManivannan Sadhasivam 
2890cbf2608SManivannan Sadhasivam /**
2900cbf2608SManivannan Sadhasivam  * struct mhi_controller - Master MHI controller structure
2910cbf2608SManivannan Sadhasivam  * @cntrl_dev: Pointer to the struct device of physical bus acting as the MHI
2920cbf2608SManivannan Sadhasivam  *            controller (required)
2930cbf2608SManivannan Sadhasivam  * @mhi_dev: MHI device instance for the controller
294c7bd825eSBhaumik Bhatt  * @debugfs_dentry: MHI controller debugfs directory
2950cbf2608SManivannan Sadhasivam  * @regs: Base address of MHI MMIO register space (required)
2966cd330aeSManivannan Sadhasivam  * @bhi: Points to base of MHI BHI register space
2973000f85bSManivannan Sadhasivam  * @bhie: Points to base of MHI BHIe register space
2986cd330aeSManivannan Sadhasivam  * @wake_db: MHI WAKE doorbell register address
2990cbf2608SManivannan Sadhasivam  * @iova_start: IOMMU starting address for data (required)
3000cbf2608SManivannan Sadhasivam  * @iova_stop: IOMMU stop address for data (required)
3014d5f5283SBhaumik Bhatt  * @fw_image: Firmware image name for normal booting (optional)
302*efe47a18SKalle Valo  * @fw_data: Firmware image data content for normal booting, used only
303*efe47a18SKalle Valo  *           if fw_image is NULL and fbc_download is true (optional)
304*efe47a18SKalle Valo  * @fw_sz: Firmware image data size for normal booting, used only if fw_image
305*efe47a18SKalle Valo  *         is NULL and fbc_download is true (optional)
3060cbf2608SManivannan Sadhasivam  * @edl_image: Firmware image name for emergency download mode (optional)
3076fdfdd27SManivannan Sadhasivam  * @rddm_size: RAM dump size that host should allocate for debugging purpose
3080cbf2608SManivannan Sadhasivam  * @sbl_size: SBL image size downloaded through BHIe (optional)
3090cbf2608SManivannan Sadhasivam  * @seg_len: BHIe vector size (optional)
310baa7a085SBhaumik Bhatt  * @reg_len: Length of the MHI MMIO region (required)
3113000f85bSManivannan Sadhasivam  * @fbc_image: Points to firmware image buffer
3126fdfdd27SManivannan Sadhasivam  * @rddm_image: Points to RAM dump buffer
3130cbf2608SManivannan Sadhasivam  * @mhi_chan: Points to the channel configuration table
3140cbf2608SManivannan Sadhasivam  * @lpm_chans: List of channels that require LPM notifications
3150cbf2608SManivannan Sadhasivam  * @irq: base irq # to request (required)
3160cbf2608SManivannan Sadhasivam  * @max_chan: Maximum number of channels the controller supports
3170cbf2608SManivannan Sadhasivam  * @total_ev_rings: Total # of event rings allocated
3180cbf2608SManivannan Sadhasivam  * @hw_ev_rings: Number of hardware event rings
3190cbf2608SManivannan Sadhasivam  * @sw_ev_rings: Number of software event rings
3200cbf2608SManivannan Sadhasivam  * @nr_irqs: Number of IRQ allocated by bus master (required)
3213316ab2bSManivannan Sadhasivam  * @family_number: MHI controller family number
3223316ab2bSManivannan Sadhasivam  * @device_number: MHI controller device number
3233316ab2bSManivannan Sadhasivam  * @major_version: MHI controller major revision number
3243316ab2bSManivannan Sadhasivam  * @minor_version: MHI controller minor revision number
3258e3729bfSBhaumik Bhatt  * @serial_number: MHI controller serial number obtained from BHI
3268e3729bfSBhaumik Bhatt  * @oem_pk_hash: MHI controller OEM PK Hash obtained from BHI
3270cbf2608SManivannan Sadhasivam  * @mhi_event: MHI event ring configurations table
3280cbf2608SManivannan Sadhasivam  * @mhi_cmd: MHI command ring configurations table
3290cbf2608SManivannan Sadhasivam  * @mhi_ctxt: MHI device context, shared memory between host and device
3300cbf2608SManivannan Sadhasivam  * @pm_mutex: Mutex for suspend/resume operation
3310cbf2608SManivannan Sadhasivam  * @pm_lock: Lock for protecting MHI power management state
3320cbf2608SManivannan Sadhasivam  * @timeout_ms: Timeout in ms for state transitions
3330cbf2608SManivannan Sadhasivam  * @pm_state: MHI power management state
3340cbf2608SManivannan Sadhasivam  * @db_access: DB access states
3350cbf2608SManivannan Sadhasivam  * @ee: MHI device execution environment
336a6e2e352SManivannan Sadhasivam  * @dev_state: MHI device state
3370cbf2608SManivannan Sadhasivam  * @dev_wake: Device wakeup count
3380cbf2608SManivannan Sadhasivam  * @pending_pkts: Pending packets for the controller
339601455daSBhaumik Bhatt  * @M0, M2, M3: Counters to track number of device MHI state changes
3400cbf2608SManivannan Sadhasivam  * @transition_list: List of MHI state transitions
3410cbf2608SManivannan Sadhasivam  * @transition_lock: Lock for protecting MHI state transition list
3420cbf2608SManivannan Sadhasivam  * @wlock: Lock for protecting device wakeup
3431d3173a3SManivannan Sadhasivam  * @mhi_link_info: Device bandwidth info
3440cbf2608SManivannan Sadhasivam  * @st_worker: State transition worker
3458f703978SBhaumik Bhatt  * @hiprio_wq: High priority workqueue for MHI work such as state transitions
3460cbf2608SManivannan Sadhasivam  * @state_event: State change event
3470cbf2608SManivannan Sadhasivam  * @status_cb: CB function to notify power states of the device (required)
3480cbf2608SManivannan Sadhasivam  * @wake_get: CB function to assert device wake (optional)
3490cbf2608SManivannan Sadhasivam  * @wake_put: CB function to de-assert device wake (optional)
3500cbf2608SManivannan Sadhasivam  * @wake_toggle: CB function to assert and de-assert device wake (optional)
3510cbf2608SManivannan Sadhasivam  * @runtime_get: CB function to controller runtime resume (required)
352af2e5881SJeffrey Hugo  * @runtime_put: CB function to decrement pm usage (required)
353189ff97cSManivannan Sadhasivam  * @map_single: CB function to create TRE buffer
354189ff97cSManivannan Sadhasivam  * @unmap_single: CB function to destroy TRE buffer
35545723a44SJeffrey Hugo  * @read_reg: Read a MHI register via the physical link (required)
35645723a44SJeffrey Hugo  * @write_reg: Write a MHI register via the physical link (required)
357b5a8d233SLoic Poulain  * @reset: Controller specific reset function (optional)
3580cbf2608SManivannan Sadhasivam  * @buffer_len: Bounce buffer length
359206e7383SLoic Poulain  * @index: Index of the MHI controller instance
3600cbf2608SManivannan Sadhasivam  * @bounce_buf: Use of bounce buffer
3610cbf2608SManivannan Sadhasivam  * @fbc_download: MHI host needs to do complete image transfer (optional)
3620cbf2608SManivannan Sadhasivam  * @wake_set: Device wakeup set flag
3636ffcc18dSCarl Huang  * @irq_flags: irq flags passed to request_irq (optional)
3645c2c8531SRichard Laing  * @mru: the default MRU for the MHI device
3650cbf2608SManivannan Sadhasivam  *
3660cbf2608SManivannan Sadhasivam  * Fields marked as (required) need to be populated by the controller driver
3670cbf2608SManivannan Sadhasivam  * before calling mhi_register_controller(). For the fields marked as (optional)
3680cbf2608SManivannan Sadhasivam  * they can be populated depending on the usecase.
3693316ab2bSManivannan Sadhasivam  *
3703316ab2bSManivannan Sadhasivam  * The following fields are present for the purpose of implementing any device
3713316ab2bSManivannan Sadhasivam  * specific quirks or customizations for specific MHI revisions used in device
3723316ab2bSManivannan Sadhasivam  * by the controller drivers. The MHI stack will just populate these fields
3733316ab2bSManivannan Sadhasivam  * during mhi_register_controller():
3743316ab2bSManivannan Sadhasivam  *  family_number
3753316ab2bSManivannan Sadhasivam  *  device_number
3763316ab2bSManivannan Sadhasivam  *  major_version
3773316ab2bSManivannan Sadhasivam  *  minor_version
3780cbf2608SManivannan Sadhasivam  */
3790cbf2608SManivannan Sadhasivam struct mhi_controller {
3800cbf2608SManivannan Sadhasivam 	struct device *cntrl_dev;
3810cbf2608SManivannan Sadhasivam 	struct mhi_device *mhi_dev;
382c7bd825eSBhaumik Bhatt 	struct dentry *debugfs_dentry;
3830cbf2608SManivannan Sadhasivam 	void __iomem *regs;
3846cd330aeSManivannan Sadhasivam 	void __iomem *bhi;
3853000f85bSManivannan Sadhasivam 	void __iomem *bhie;
3866cd330aeSManivannan Sadhasivam 	void __iomem *wake_db;
387a6e2e352SManivannan Sadhasivam 
3880cbf2608SManivannan Sadhasivam 	dma_addr_t iova_start;
3890cbf2608SManivannan Sadhasivam 	dma_addr_t iova_stop;
3900cbf2608SManivannan Sadhasivam 	const char *fw_image;
391*efe47a18SKalle Valo 	const u8 *fw_data;
392*efe47a18SKalle Valo 	size_t fw_sz;
3930cbf2608SManivannan Sadhasivam 	const char *edl_image;
3946fdfdd27SManivannan Sadhasivam 	size_t rddm_size;
3950cbf2608SManivannan Sadhasivam 	size_t sbl_size;
3960cbf2608SManivannan Sadhasivam 	size_t seg_len;
397baa7a085SBhaumik Bhatt 	size_t reg_len;
3983000f85bSManivannan Sadhasivam 	struct image_info *fbc_image;
3996fdfdd27SManivannan Sadhasivam 	struct image_info *rddm_image;
4000cbf2608SManivannan Sadhasivam 	struct mhi_chan *mhi_chan;
4010cbf2608SManivannan Sadhasivam 	struct list_head lpm_chans;
4020cbf2608SManivannan Sadhasivam 	int *irq;
4030cbf2608SManivannan Sadhasivam 	u32 max_chan;
4040cbf2608SManivannan Sadhasivam 	u32 total_ev_rings;
4050cbf2608SManivannan Sadhasivam 	u32 hw_ev_rings;
4060cbf2608SManivannan Sadhasivam 	u32 sw_ev_rings;
4070cbf2608SManivannan Sadhasivam 	u32 nr_irqs;
4083316ab2bSManivannan Sadhasivam 	u32 family_number;
4093316ab2bSManivannan Sadhasivam 	u32 device_number;
4103316ab2bSManivannan Sadhasivam 	u32 major_version;
4113316ab2bSManivannan Sadhasivam 	u32 minor_version;
4128e3729bfSBhaumik Bhatt 	u32 serial_number;
4138e3729bfSBhaumik Bhatt 	u32 oem_pk_hash[MHI_MAX_OEM_PK_HASH_SEGMENTS];
4140cbf2608SManivannan Sadhasivam 
4150cbf2608SManivannan Sadhasivam 	struct mhi_event *mhi_event;
4160cbf2608SManivannan Sadhasivam 	struct mhi_cmd *mhi_cmd;
4170cbf2608SManivannan Sadhasivam 	struct mhi_ctxt *mhi_ctxt;
4180cbf2608SManivannan Sadhasivam 
4190cbf2608SManivannan Sadhasivam 	struct mutex pm_mutex;
4200cbf2608SManivannan Sadhasivam 	rwlock_t pm_lock;
4210cbf2608SManivannan Sadhasivam 	u32 timeout_ms;
4220cbf2608SManivannan Sadhasivam 	u32 pm_state;
4230cbf2608SManivannan Sadhasivam 	u32 db_access;
4240cbf2608SManivannan Sadhasivam 	enum mhi_ee_type ee;
425a6e2e352SManivannan Sadhasivam 	enum mhi_state dev_state;
4260cbf2608SManivannan Sadhasivam 	atomic_t dev_wake;
4270cbf2608SManivannan Sadhasivam 	atomic_t pending_pkts;
428601455daSBhaumik Bhatt 	u32 M0, M2, M3;
4290cbf2608SManivannan Sadhasivam 	struct list_head transition_list;
4300cbf2608SManivannan Sadhasivam 	spinlock_t transition_lock;
4310cbf2608SManivannan Sadhasivam 	spinlock_t wlock;
4321d3173a3SManivannan Sadhasivam 	struct mhi_link_info mhi_link_info;
4330cbf2608SManivannan Sadhasivam 	struct work_struct st_worker;
4348f703978SBhaumik Bhatt 	struct workqueue_struct *hiprio_wq;
4350cbf2608SManivannan Sadhasivam 	wait_queue_head_t state_event;
4360cbf2608SManivannan Sadhasivam 
4370cbf2608SManivannan Sadhasivam 	void (*status_cb)(struct mhi_controller *mhi_cntrl,
4380cbf2608SManivannan Sadhasivam 			  enum mhi_callback cb);
4390cbf2608SManivannan Sadhasivam 	void (*wake_get)(struct mhi_controller *mhi_cntrl, bool override);
4400cbf2608SManivannan Sadhasivam 	void (*wake_put)(struct mhi_controller *mhi_cntrl, bool override);
4410cbf2608SManivannan Sadhasivam 	void (*wake_toggle)(struct mhi_controller *mhi_cntrl);
4420cbf2608SManivannan Sadhasivam 	int (*runtime_get)(struct mhi_controller *mhi_cntrl);
4430cbf2608SManivannan Sadhasivam 	void (*runtime_put)(struct mhi_controller *mhi_cntrl);
444189ff97cSManivannan Sadhasivam 	int (*map_single)(struct mhi_controller *mhi_cntrl,
445189ff97cSManivannan Sadhasivam 			  struct mhi_buf_info *buf);
446189ff97cSManivannan Sadhasivam 	void (*unmap_single)(struct mhi_controller *mhi_cntrl,
447189ff97cSManivannan Sadhasivam 			     struct mhi_buf_info *buf);
44845723a44SJeffrey Hugo 	int (*read_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr,
44945723a44SJeffrey Hugo 			u32 *out);
45045723a44SJeffrey Hugo 	void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr,
45145723a44SJeffrey Hugo 			  u32 val);
452b5a8d233SLoic Poulain 	void (*reset)(struct mhi_controller *mhi_cntrl);
4530cbf2608SManivannan Sadhasivam 
4540cbf2608SManivannan Sadhasivam 	size_t buffer_len;
455206e7383SLoic Poulain 	int index;
4560cbf2608SManivannan Sadhasivam 	bool bounce_buf;
4570cbf2608SManivannan Sadhasivam 	bool fbc_download;
4580cbf2608SManivannan Sadhasivam 	bool wake_set;
4596ffcc18dSCarl Huang 	unsigned long irq_flags;
4605c2c8531SRichard Laing 	u32 mru;
4610cbf2608SManivannan Sadhasivam };
4620cbf2608SManivannan Sadhasivam 
4630cbf2608SManivannan Sadhasivam /**
4645aa93f05SBhaumik Bhatt  * struct mhi_device - Structure representing an MHI device which binds
4655aa93f05SBhaumik Bhatt  *                     to channels or is associated with controllers
4660cbf2608SManivannan Sadhasivam  * @id: Pointer to MHI device ID struct
4675aa93f05SBhaumik Bhatt  * @name: Name of the associated MHI device
4680cbf2608SManivannan Sadhasivam  * @mhi_cntrl: Controller the device belongs to
4690cbf2608SManivannan Sadhasivam  * @ul_chan: UL channel for the device
4700cbf2608SManivannan Sadhasivam  * @dl_chan: DL channel for the device
4710cbf2608SManivannan Sadhasivam  * @dev: Driver model device node for the MHI device
4720cbf2608SManivannan Sadhasivam  * @dev_type: MHI device type
473e755cadbSManivannan Sadhasivam  * @ul_chan_id: MHI channel id for UL transfer
474e755cadbSManivannan Sadhasivam  * @dl_chan_id: MHI channel id for DL transfer
4750cbf2608SManivannan Sadhasivam  * @dev_wake: Device wakeup counter
4760cbf2608SManivannan Sadhasivam  */
4770cbf2608SManivannan Sadhasivam struct mhi_device {
4780cbf2608SManivannan Sadhasivam 	const struct mhi_device_id *id;
4795aa93f05SBhaumik Bhatt 	const char *name;
4800cbf2608SManivannan Sadhasivam 	struct mhi_controller *mhi_cntrl;
4810cbf2608SManivannan Sadhasivam 	struct mhi_chan *ul_chan;
4820cbf2608SManivannan Sadhasivam 	struct mhi_chan *dl_chan;
4830cbf2608SManivannan Sadhasivam 	struct device dev;
4840cbf2608SManivannan Sadhasivam 	enum mhi_device_type dev_type;
485e755cadbSManivannan Sadhasivam 	int ul_chan_id;
486e755cadbSManivannan Sadhasivam 	int dl_chan_id;
4870cbf2608SManivannan Sadhasivam 	u32 dev_wake;
4880cbf2608SManivannan Sadhasivam };
4890cbf2608SManivannan Sadhasivam 
4900cbf2608SManivannan Sadhasivam /**
4910cbf2608SManivannan Sadhasivam  * struct mhi_result - Completed buffer information
4920cbf2608SManivannan Sadhasivam  * @buf_addr: Address of data buffer
4930cbf2608SManivannan Sadhasivam  * @bytes_xferd: # of bytes transferred
4940cbf2608SManivannan Sadhasivam  * @dir: Channel direction
4950cbf2608SManivannan Sadhasivam  * @transaction_status: Status of last transaction
4960cbf2608SManivannan Sadhasivam  */
4970cbf2608SManivannan Sadhasivam struct mhi_result {
4980cbf2608SManivannan Sadhasivam 	void *buf_addr;
4990cbf2608SManivannan Sadhasivam 	size_t bytes_xferd;
5000cbf2608SManivannan Sadhasivam 	enum dma_data_direction dir;
5010cbf2608SManivannan Sadhasivam 	int transaction_status;
5020cbf2608SManivannan Sadhasivam };
5030cbf2608SManivannan Sadhasivam 
504e755cadbSManivannan Sadhasivam /**
505a6e2e352SManivannan Sadhasivam  * struct mhi_buf - MHI Buffer description
506a6e2e352SManivannan Sadhasivam  * @buf: Virtual address of the buffer
507a6e2e352SManivannan Sadhasivam  * @name: Buffer label. For offload channel, configurations name must be:
508a6e2e352SManivannan Sadhasivam  *        ECA - Event context array data
509a6e2e352SManivannan Sadhasivam  *        CCA - Channel context array data
510a6e2e352SManivannan Sadhasivam  * @dma_addr: IOMMU address of the buffer
511a6e2e352SManivannan Sadhasivam  * @len: # of bytes
512a6e2e352SManivannan Sadhasivam  */
513a6e2e352SManivannan Sadhasivam struct mhi_buf {
514a6e2e352SManivannan Sadhasivam 	void *buf;
515a6e2e352SManivannan Sadhasivam 	const char *name;
516a6e2e352SManivannan Sadhasivam 	dma_addr_t dma_addr;
517a6e2e352SManivannan Sadhasivam 	size_t len;
518a6e2e352SManivannan Sadhasivam };
519a6e2e352SManivannan Sadhasivam 
520a6e2e352SManivannan Sadhasivam /**
521e755cadbSManivannan Sadhasivam  * struct mhi_driver - Structure representing a MHI client driver
522e755cadbSManivannan Sadhasivam  * @probe: CB function for client driver probe function
523e755cadbSManivannan Sadhasivam  * @remove: CB function for client driver remove function
524e755cadbSManivannan Sadhasivam  * @ul_xfer_cb: CB function for UL data transfer
525e755cadbSManivannan Sadhasivam  * @dl_xfer_cb: CB function for DL data transfer
526e755cadbSManivannan Sadhasivam  * @status_cb: CB functions for asynchronous status
527e755cadbSManivannan Sadhasivam  * @driver: Device driver model driver
528e755cadbSManivannan Sadhasivam  */
529e755cadbSManivannan Sadhasivam struct mhi_driver {
530e755cadbSManivannan Sadhasivam 	const struct mhi_device_id *id_table;
531e755cadbSManivannan Sadhasivam 	int (*probe)(struct mhi_device *mhi_dev,
532e755cadbSManivannan Sadhasivam 		     const struct mhi_device_id *id);
533e755cadbSManivannan Sadhasivam 	void (*remove)(struct mhi_device *mhi_dev);
534e755cadbSManivannan Sadhasivam 	void (*ul_xfer_cb)(struct mhi_device *mhi_dev,
535e755cadbSManivannan Sadhasivam 			   struct mhi_result *result);
536e755cadbSManivannan Sadhasivam 	void (*dl_xfer_cb)(struct mhi_device *mhi_dev,
537e755cadbSManivannan Sadhasivam 			   struct mhi_result *result);
538e755cadbSManivannan Sadhasivam 	void (*status_cb)(struct mhi_device *mhi_dev, enum mhi_callback mhi_cb);
539e755cadbSManivannan Sadhasivam 	struct device_driver driver;
540e755cadbSManivannan Sadhasivam };
541e755cadbSManivannan Sadhasivam 
542e755cadbSManivannan Sadhasivam #define to_mhi_driver(drv) container_of(drv, struct mhi_driver, driver)
5430cbf2608SManivannan Sadhasivam #define to_mhi_device(dev) container_of(dev, struct mhi_device, dev)
5440cbf2608SManivannan Sadhasivam 
5450cbf2608SManivannan Sadhasivam /**
546f42dfbe8SBhaumik Bhatt  * mhi_alloc_controller - Allocate the MHI Controller structure
547f42dfbe8SBhaumik Bhatt  * Allocate the mhi_controller structure using zero initialized memory
548f42dfbe8SBhaumik Bhatt  */
549f42dfbe8SBhaumik Bhatt struct mhi_controller *mhi_alloc_controller(void);
550f42dfbe8SBhaumik Bhatt 
551f42dfbe8SBhaumik Bhatt /**
552f42dfbe8SBhaumik Bhatt  * mhi_free_controller - Free the MHI Controller structure
553f42dfbe8SBhaumik Bhatt  * Free the mhi_controller structure which was previously allocated
554f42dfbe8SBhaumik Bhatt  */
555f42dfbe8SBhaumik Bhatt void mhi_free_controller(struct mhi_controller *mhi_cntrl);
556f42dfbe8SBhaumik Bhatt 
557f42dfbe8SBhaumik Bhatt /**
5580cbf2608SManivannan Sadhasivam  * mhi_register_controller - Register MHI controller
5590cbf2608SManivannan Sadhasivam  * @mhi_cntrl: MHI controller to register
5600cbf2608SManivannan Sadhasivam  * @config: Configuration to use for the controller
5610cbf2608SManivannan Sadhasivam  */
5620cbf2608SManivannan Sadhasivam int mhi_register_controller(struct mhi_controller *mhi_cntrl,
563f38173a7SHemant Kumar 			const struct mhi_controller_config *config);
5640cbf2608SManivannan Sadhasivam 
5650cbf2608SManivannan Sadhasivam /**
5660cbf2608SManivannan Sadhasivam  * mhi_unregister_controller - Unregister MHI controller
5670cbf2608SManivannan Sadhasivam  * @mhi_cntrl: MHI controller to unregister
5680cbf2608SManivannan Sadhasivam  */
5690cbf2608SManivannan Sadhasivam void mhi_unregister_controller(struct mhi_controller *mhi_cntrl);
5700cbf2608SManivannan Sadhasivam 
57182174738SManivannan Sadhasivam /*
57282174738SManivannan Sadhasivam  * module_mhi_driver() - Helper macro for drivers that don't do
57382174738SManivannan Sadhasivam  * anything special other than using default mhi_driver_register() and
57482174738SManivannan Sadhasivam  * mhi_driver_unregister().  This eliminates a lot of boilerplate.
57582174738SManivannan Sadhasivam  * Each module may only use this macro once.
576e755cadbSManivannan Sadhasivam  */
57782174738SManivannan Sadhasivam #define module_mhi_driver(mhi_drv) \
57882174738SManivannan Sadhasivam 	module_driver(mhi_drv, mhi_driver_register, \
57982174738SManivannan Sadhasivam 		      mhi_driver_unregister)
58082174738SManivannan Sadhasivam 
58182174738SManivannan Sadhasivam /*
58282174738SManivannan Sadhasivam  * Macro to avoid include chaining to get THIS_MODULE
58382174738SManivannan Sadhasivam  */
58482174738SManivannan Sadhasivam #define mhi_driver_register(mhi_drv) \
58582174738SManivannan Sadhasivam 	__mhi_driver_register(mhi_drv, THIS_MODULE)
58682174738SManivannan Sadhasivam 
58782174738SManivannan Sadhasivam /**
58882174738SManivannan Sadhasivam  * __mhi_driver_register - Register driver with MHI framework
58982174738SManivannan Sadhasivam  * @mhi_drv: Driver associated with the device
59082174738SManivannan Sadhasivam  * @owner: The module owner
59182174738SManivannan Sadhasivam  */
59282174738SManivannan Sadhasivam int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner);
593e755cadbSManivannan Sadhasivam 
594e755cadbSManivannan Sadhasivam /**
595e755cadbSManivannan Sadhasivam  * mhi_driver_unregister - Unregister a driver for mhi_devices
596e755cadbSManivannan Sadhasivam  * @mhi_drv: Driver associated with the device
597e755cadbSManivannan Sadhasivam  */
598e755cadbSManivannan Sadhasivam void mhi_driver_unregister(struct mhi_driver *mhi_drv);
599e755cadbSManivannan Sadhasivam 
600a6e2e352SManivannan Sadhasivam /**
601a6e2e352SManivannan Sadhasivam  * mhi_set_mhi_state - Set MHI device state
602a6e2e352SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
603a6e2e352SManivannan Sadhasivam  * @state: State to set
604a6e2e352SManivannan Sadhasivam  */
605a6e2e352SManivannan Sadhasivam void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl,
606a6e2e352SManivannan Sadhasivam 		       enum mhi_state state);
607a6e2e352SManivannan Sadhasivam 
6083000f85bSManivannan Sadhasivam /**
6090c6b20a1SManivannan Sadhasivam  * mhi_notify - Notify the MHI client driver about client device status
6100c6b20a1SManivannan Sadhasivam  * @mhi_dev: MHI device instance
6110c6b20a1SManivannan Sadhasivam  * @cb_reason: MHI callback reason
6120c6b20a1SManivannan Sadhasivam  */
6130c6b20a1SManivannan Sadhasivam void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason);
6140c6b20a1SManivannan Sadhasivam 
6150c6b20a1SManivannan Sadhasivam /**
61687baa23eSHemant Kumar  * mhi_get_free_desc_count - Get transfer ring length
61787baa23eSHemant Kumar  * Get # of TD available to queue buffers
61887baa23eSHemant Kumar  * @mhi_dev: Device associated with the channels
61987baa23eSHemant Kumar  * @dir: Direction of the channel
62087baa23eSHemant Kumar  */
62187baa23eSHemant Kumar int mhi_get_free_desc_count(struct mhi_device *mhi_dev,
62287baa23eSHemant Kumar 				enum dma_data_direction dir);
62387baa23eSHemant Kumar 
62487baa23eSHemant Kumar /**
6253000f85bSManivannan Sadhasivam  * mhi_prepare_for_power_up - Do pre-initialization before power up.
6263000f85bSManivannan Sadhasivam  *                            This is optional, call this before power up if
6273000f85bSManivannan Sadhasivam  *                            the controller does not want bus framework to
6283000f85bSManivannan Sadhasivam  *                            automatically free any allocated memory during
6293000f85bSManivannan Sadhasivam  *                            shutdown process.
6303000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6313000f85bSManivannan Sadhasivam  */
6323000f85bSManivannan Sadhasivam int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl);
6333000f85bSManivannan Sadhasivam 
6343000f85bSManivannan Sadhasivam /**
6353000f85bSManivannan Sadhasivam  * mhi_async_power_up - Start MHI power up sequence
6363000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6373000f85bSManivannan Sadhasivam  */
6383000f85bSManivannan Sadhasivam int mhi_async_power_up(struct mhi_controller *mhi_cntrl);
6393000f85bSManivannan Sadhasivam 
6403000f85bSManivannan Sadhasivam /**
6413000f85bSManivannan Sadhasivam  * mhi_sync_power_up - Start MHI power up sequence and wait till the device
6424d12a897SRandy Dunlap  *                     enters valid EE state
6433000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6443000f85bSManivannan Sadhasivam  */
6453000f85bSManivannan Sadhasivam int mhi_sync_power_up(struct mhi_controller *mhi_cntrl);
6463000f85bSManivannan Sadhasivam 
6473000f85bSManivannan Sadhasivam /**
6483000f85bSManivannan Sadhasivam  * mhi_power_down - Start MHI power down sequence
6493000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6503000f85bSManivannan Sadhasivam  * @graceful: Link is still accessible, so do a graceful shutdown process
6513000f85bSManivannan Sadhasivam  */
6523000f85bSManivannan Sadhasivam void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful);
6533000f85bSManivannan Sadhasivam 
6543000f85bSManivannan Sadhasivam /**
6553000f85bSManivannan Sadhasivam  * mhi_unprepare_after_power_down - Free any allocated memory after power down
6563000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6573000f85bSManivannan Sadhasivam  */
6583000f85bSManivannan Sadhasivam void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl);
6593000f85bSManivannan Sadhasivam 
6606fdfdd27SManivannan Sadhasivam /**
6610c6b20a1SManivannan Sadhasivam  * mhi_pm_suspend - Move MHI into a suspended state
6620c6b20a1SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6630c6b20a1SManivannan Sadhasivam  */
6640c6b20a1SManivannan Sadhasivam int mhi_pm_suspend(struct mhi_controller *mhi_cntrl);
6650c6b20a1SManivannan Sadhasivam 
6660c6b20a1SManivannan Sadhasivam /**
6670c6b20a1SManivannan Sadhasivam  * mhi_pm_resume - Resume MHI from suspended state
6680c6b20a1SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6690c6b20a1SManivannan Sadhasivam  */
6700c6b20a1SManivannan Sadhasivam int mhi_pm_resume(struct mhi_controller *mhi_cntrl);
6710c6b20a1SManivannan Sadhasivam 
6720c6b20a1SManivannan Sadhasivam /**
673cab2d3fdSLoic Poulain  * mhi_pm_resume_force - Force resume MHI from suspended state
674cab2d3fdSLoic Poulain  * @mhi_cntrl: MHI controller
675cab2d3fdSLoic Poulain  *
676cab2d3fdSLoic Poulain  * Resume the device irrespective of its MHI state. As per the MHI spec, devices
677cab2d3fdSLoic Poulain  * has to be in M3 state during resume. But some devices seem to be in a
678cab2d3fdSLoic Poulain  * different MHI state other than M3 but they continue working fine if allowed.
679cab2d3fdSLoic Poulain  * This API is intented to be used for such devices.
680cab2d3fdSLoic Poulain  *
681cab2d3fdSLoic Poulain  * Return: 0 if the resume succeeds, a negative error code otherwise
682cab2d3fdSLoic Poulain  */
683cab2d3fdSLoic Poulain int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl);
684cab2d3fdSLoic Poulain 
685cab2d3fdSLoic Poulain /**
6869e1660e5SBhaumik Bhatt  * mhi_download_rddm_image - Download ramdump image from device for
6876fdfdd27SManivannan Sadhasivam  *                           debugging purpose.
6886fdfdd27SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6896fdfdd27SManivannan Sadhasivam  * @in_panic: Download rddm image during kernel panic
6906fdfdd27SManivannan Sadhasivam  */
6919e1660e5SBhaumik Bhatt int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic);
6926fdfdd27SManivannan Sadhasivam 
6936fdfdd27SManivannan Sadhasivam /**
6946fdfdd27SManivannan Sadhasivam  * mhi_force_rddm_mode - Force device into rddm mode
6956fdfdd27SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
6966fdfdd27SManivannan Sadhasivam  */
6976fdfdd27SManivannan Sadhasivam int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl);
6986fdfdd27SManivannan Sadhasivam 
6996fdfdd27SManivannan Sadhasivam /**
70078e1d226SBhaumik Bhatt  * mhi_get_exec_env - Get BHI execution environment of the device
70178e1d226SBhaumik Bhatt  * @mhi_cntrl: MHI controller
70278e1d226SBhaumik Bhatt  */
70378e1d226SBhaumik Bhatt enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl);
70478e1d226SBhaumik Bhatt 
70578e1d226SBhaumik Bhatt /**
7066fdfdd27SManivannan Sadhasivam  * mhi_get_mhi_state - Get MHI state of the device
7076fdfdd27SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
7086fdfdd27SManivannan Sadhasivam  */
7096fdfdd27SManivannan Sadhasivam enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl);
7106fdfdd27SManivannan Sadhasivam 
711189ff97cSManivannan Sadhasivam /**
712b5a8d233SLoic Poulain  * mhi_soc_reset - Trigger a device reset. This can be used as a last resort
713b5a8d233SLoic Poulain  *		   to reset and recover a device.
714b5a8d233SLoic Poulain  * @mhi_cntrl: MHI controller
715b5a8d233SLoic Poulain  */
716b5a8d233SLoic Poulain void mhi_soc_reset(struct mhi_controller *mhi_cntrl);
717b5a8d233SLoic Poulain 
718b5a8d233SLoic Poulain /**
719189ff97cSManivannan Sadhasivam  * mhi_device_get - Disable device low power mode
720189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channel
721189ff97cSManivannan Sadhasivam  */
722189ff97cSManivannan Sadhasivam void mhi_device_get(struct mhi_device *mhi_dev);
723189ff97cSManivannan Sadhasivam 
724189ff97cSManivannan Sadhasivam /**
725189ff97cSManivannan Sadhasivam  * mhi_device_get_sync - Disable device low power mode. Synchronously
726189ff97cSManivannan Sadhasivam  *                       take the controller out of suspended state
727189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channel
728189ff97cSManivannan Sadhasivam  */
729189ff97cSManivannan Sadhasivam int mhi_device_get_sync(struct mhi_device *mhi_dev);
730189ff97cSManivannan Sadhasivam 
731189ff97cSManivannan Sadhasivam /**
732189ff97cSManivannan Sadhasivam  * mhi_device_put - Re-enable device low power mode
733189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channel
734189ff97cSManivannan Sadhasivam  */
735189ff97cSManivannan Sadhasivam void mhi_device_put(struct mhi_device *mhi_dev);
736189ff97cSManivannan Sadhasivam 
737189ff97cSManivannan Sadhasivam /**
7386731fefdSBhaumik Bhatt  * mhi_prepare_for_transfer - Setup UL and DL channels for data transfer.
739189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channels
740227fee5fSManivannan Sadhasivam  *
741227fee5fSManivannan Sadhasivam  * Allocate and initialize the channel context and also issue the START channel
742227fee5fSManivannan Sadhasivam  * command to both channels. Channels can be started only if both host and
743227fee5fSManivannan Sadhasivam  * device execution environments match and channels are in a DISABLED state.
744189ff97cSManivannan Sadhasivam  */
7459ebc2758SKalle Valo int mhi_prepare_for_transfer(struct mhi_device *mhi_dev);
746189ff97cSManivannan Sadhasivam 
747189ff97cSManivannan Sadhasivam /**
748227fee5fSManivannan Sadhasivam  * mhi_prepare_for_transfer_autoqueue - Setup UL and DL channels with auto queue
749227fee5fSManivannan Sadhasivam  *                                      buffers for DL traffic
750227fee5fSManivannan Sadhasivam  * @mhi_dev: Device associated with the channels
751227fee5fSManivannan Sadhasivam  *
752227fee5fSManivannan Sadhasivam  * Allocate and initialize the channel context and also issue the START channel
753227fee5fSManivannan Sadhasivam  * command to both channels. Channels can be started only if both host and
754227fee5fSManivannan Sadhasivam  * device execution environments match and channels are in a DISABLED state.
755227fee5fSManivannan Sadhasivam  * The MHI core will automatically allocate and queue buffers for the DL traffic.
756227fee5fSManivannan Sadhasivam  */
757227fee5fSManivannan Sadhasivam int mhi_prepare_for_transfer_autoqueue(struct mhi_device *mhi_dev);
758227fee5fSManivannan Sadhasivam 
759227fee5fSManivannan Sadhasivam /**
7606731fefdSBhaumik Bhatt  * mhi_unprepare_from_transfer - Reset UL and DL channels for data transfer.
7616731fefdSBhaumik Bhatt  *                               Issue the RESET channel command and let the
7626731fefdSBhaumik Bhatt  *                               device clean-up the context so no incoming
7636731fefdSBhaumik Bhatt  *                               transfers are seen on the host. Free memory
7646731fefdSBhaumik Bhatt  *                               associated with the context on host. If device
7656731fefdSBhaumik Bhatt  *                               is unresponsive, only perform a host side
7666731fefdSBhaumik Bhatt  *                               clean-up. Channels can be reset only if both
7676731fefdSBhaumik Bhatt  *                               host and device execution environments match
7686731fefdSBhaumik Bhatt  *                               and channels are in an ENABLED, STOPPED or
7696731fefdSBhaumik Bhatt  *                               SUSPENDED state.
770189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channels
771189ff97cSManivannan Sadhasivam  */
772189ff97cSManivannan Sadhasivam void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev);
773189ff97cSManivannan Sadhasivam 
774189ff97cSManivannan Sadhasivam /**
775189ff97cSManivannan Sadhasivam  * mhi_queue_dma - Send or receive DMA mapped buffers from client device
776189ff97cSManivannan Sadhasivam  *                 over MHI channel
777189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channels
778189ff97cSManivannan Sadhasivam  * @dir: DMA direction for the channel
779189ff97cSManivannan Sadhasivam  * @mhi_buf: Buffer for holding the DMA mapped data
780189ff97cSManivannan Sadhasivam  * @len: Buffer length
781189ff97cSManivannan Sadhasivam  * @mflags: MHI transfer flags used for the transfer
782189ff97cSManivannan Sadhasivam  */
783189ff97cSManivannan Sadhasivam int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir,
784189ff97cSManivannan Sadhasivam 		  struct mhi_buf *mhi_buf, size_t len, enum mhi_flags mflags);
785189ff97cSManivannan Sadhasivam 
786189ff97cSManivannan Sadhasivam /**
787189ff97cSManivannan Sadhasivam  * mhi_queue_buf - Send or receive raw buffers from client device over MHI
788189ff97cSManivannan Sadhasivam  *                 channel
789189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channels
790189ff97cSManivannan Sadhasivam  * @dir: DMA direction for the channel
791189ff97cSManivannan Sadhasivam  * @buf: Buffer for holding the data
792189ff97cSManivannan Sadhasivam  * @len: Buffer length
793189ff97cSManivannan Sadhasivam  * @mflags: MHI transfer flags used for the transfer
794189ff97cSManivannan Sadhasivam  */
795189ff97cSManivannan Sadhasivam int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir,
796189ff97cSManivannan Sadhasivam 		  void *buf, size_t len, enum mhi_flags mflags);
797189ff97cSManivannan Sadhasivam 
798189ff97cSManivannan Sadhasivam /**
799189ff97cSManivannan Sadhasivam  * mhi_queue_skb - Send or receive SKBs from client device over MHI channel
800189ff97cSManivannan Sadhasivam  * @mhi_dev: Device associated with the channels
801189ff97cSManivannan Sadhasivam  * @dir: DMA direction for the channel
802189ff97cSManivannan Sadhasivam  * @skb: Buffer for holding SKBs
803189ff97cSManivannan Sadhasivam  * @len: Buffer length
804189ff97cSManivannan Sadhasivam  * @mflags: MHI transfer flags used for the transfer
805189ff97cSManivannan Sadhasivam  */
806189ff97cSManivannan Sadhasivam int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir,
807189ff97cSManivannan Sadhasivam 		  struct sk_buff *skb, size_t len, enum mhi_flags mflags);
808189ff97cSManivannan Sadhasivam 
809d8c4a223SLoic Poulain /**
810d8c4a223SLoic Poulain  * mhi_queue_is_full - Determine whether queueing new elements is possible
811d8c4a223SLoic Poulain  * @mhi_dev: Device associated with the channels
812d8c4a223SLoic Poulain  * @dir: DMA direction for the channel
813d8c4a223SLoic Poulain  */
814d8c4a223SLoic Poulain bool mhi_queue_is_full(struct mhi_device *mhi_dev, enum dma_data_direction dir);
815d8c4a223SLoic Poulain 
8160cbf2608SManivannan Sadhasivam #endif /* _MHI_H_ */
817