10cbf2608SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0 */ 20cbf2608SManivannan Sadhasivam /* 30cbf2608SManivannan Sadhasivam * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 40cbf2608SManivannan Sadhasivam * 50cbf2608SManivannan Sadhasivam */ 60cbf2608SManivannan Sadhasivam #ifndef _MHI_H_ 70cbf2608SManivannan Sadhasivam #define _MHI_H_ 80cbf2608SManivannan Sadhasivam 90cbf2608SManivannan Sadhasivam #include <linux/device.h> 100cbf2608SManivannan Sadhasivam #include <linux/dma-direction.h> 110cbf2608SManivannan Sadhasivam #include <linux/mutex.h> 12189ff97cSManivannan Sadhasivam #include <linux/skbuff.h> 130cbf2608SManivannan Sadhasivam #include <linux/slab.h> 14e1427f32SClark Williams #include <linux/spinlock.h> 150cbf2608SManivannan Sadhasivam #include <linux/wait.h> 160cbf2608SManivannan Sadhasivam #include <linux/workqueue.h> 170cbf2608SManivannan Sadhasivam 188e3729bfSBhaumik Bhatt #define MHI_MAX_OEM_PK_HASH_SEGMENTS 16 198e3729bfSBhaumik Bhatt 200cbf2608SManivannan Sadhasivam struct mhi_chan; 210cbf2608SManivannan Sadhasivam struct mhi_event; 220cbf2608SManivannan Sadhasivam struct mhi_ctxt; 230cbf2608SManivannan Sadhasivam struct mhi_cmd; 240cbf2608SManivannan Sadhasivam struct mhi_buf_info; 250cbf2608SManivannan Sadhasivam 260cbf2608SManivannan Sadhasivam /** 270cbf2608SManivannan Sadhasivam * enum mhi_callback - MHI callback 280cbf2608SManivannan Sadhasivam * @MHI_CB_IDLE: MHI entered idle state 290cbf2608SManivannan Sadhasivam * @MHI_CB_PENDING_DATA: New data available for client to process 300cbf2608SManivannan Sadhasivam * @MHI_CB_LPM_ENTER: MHI host entered low power mode 310cbf2608SManivannan Sadhasivam * @MHI_CB_LPM_EXIT: MHI host about to exit low power mode 320cbf2608SManivannan Sadhasivam * @MHI_CB_EE_RDDM: MHI device entered RDDM exec env 330cbf2608SManivannan Sadhasivam * @MHI_CB_EE_MISSION_MODE: MHI device entered Mission Mode exec env 340cbf2608SManivannan Sadhasivam * @MHI_CB_SYS_ERROR: MHI device entered error state (may recover) 350cbf2608SManivannan Sadhasivam * @MHI_CB_FATAL_ERROR: MHI device entered fatal error state 361d3173a3SManivannan Sadhasivam * @MHI_CB_BW_REQ: Received a bandwidth switch request from device 370cbf2608SManivannan Sadhasivam */ 380cbf2608SManivannan Sadhasivam enum mhi_callback { 390cbf2608SManivannan Sadhasivam MHI_CB_IDLE, 400cbf2608SManivannan Sadhasivam MHI_CB_PENDING_DATA, 410cbf2608SManivannan Sadhasivam MHI_CB_LPM_ENTER, 420cbf2608SManivannan Sadhasivam MHI_CB_LPM_EXIT, 430cbf2608SManivannan Sadhasivam MHI_CB_EE_RDDM, 440cbf2608SManivannan Sadhasivam MHI_CB_EE_MISSION_MODE, 450cbf2608SManivannan Sadhasivam MHI_CB_SYS_ERROR, 460cbf2608SManivannan Sadhasivam MHI_CB_FATAL_ERROR, 471d3173a3SManivannan Sadhasivam MHI_CB_BW_REQ, 480cbf2608SManivannan Sadhasivam }; 490cbf2608SManivannan Sadhasivam 500cbf2608SManivannan Sadhasivam /** 510cbf2608SManivannan Sadhasivam * enum mhi_flags - Transfer flags 520cbf2608SManivannan Sadhasivam * @MHI_EOB: End of buffer for bulk transfer 530cbf2608SManivannan Sadhasivam * @MHI_EOT: End of transfer 540cbf2608SManivannan Sadhasivam * @MHI_CHAIN: Linked transfer 550cbf2608SManivannan Sadhasivam */ 560cbf2608SManivannan Sadhasivam enum mhi_flags { 57115f3251SManivannan Sadhasivam MHI_EOB = BIT(0), 58115f3251SManivannan Sadhasivam MHI_EOT = BIT(1), 59115f3251SManivannan Sadhasivam MHI_CHAIN = BIT(2), 600cbf2608SManivannan Sadhasivam }; 610cbf2608SManivannan Sadhasivam 620cbf2608SManivannan Sadhasivam /** 630cbf2608SManivannan Sadhasivam * enum mhi_device_type - Device types 640cbf2608SManivannan Sadhasivam * @MHI_DEVICE_XFER: Handles data transfer 650cbf2608SManivannan Sadhasivam * @MHI_DEVICE_CONTROLLER: Control device 660cbf2608SManivannan Sadhasivam */ 670cbf2608SManivannan Sadhasivam enum mhi_device_type { 680cbf2608SManivannan Sadhasivam MHI_DEVICE_XFER, 690cbf2608SManivannan Sadhasivam MHI_DEVICE_CONTROLLER, 700cbf2608SManivannan Sadhasivam }; 710cbf2608SManivannan Sadhasivam 720cbf2608SManivannan Sadhasivam /** 730cbf2608SManivannan Sadhasivam * enum mhi_ch_type - Channel types 740cbf2608SManivannan Sadhasivam * @MHI_CH_TYPE_INVALID: Invalid channel type 750cbf2608SManivannan Sadhasivam * @MHI_CH_TYPE_OUTBOUND: Outbound channel to the device 760cbf2608SManivannan Sadhasivam * @MHI_CH_TYPE_INBOUND: Inbound channel from the device 770cbf2608SManivannan Sadhasivam * @MHI_CH_TYPE_INBOUND_COALESCED: Coalesced channel for the device to combine 780cbf2608SManivannan Sadhasivam * multiple packets and send them as a single 790cbf2608SManivannan Sadhasivam * large packet to reduce CPU consumption 800cbf2608SManivannan Sadhasivam */ 810cbf2608SManivannan Sadhasivam enum mhi_ch_type { 820cbf2608SManivannan Sadhasivam MHI_CH_TYPE_INVALID = 0, 830cbf2608SManivannan Sadhasivam MHI_CH_TYPE_OUTBOUND = DMA_TO_DEVICE, 840cbf2608SManivannan Sadhasivam MHI_CH_TYPE_INBOUND = DMA_FROM_DEVICE, 850cbf2608SManivannan Sadhasivam MHI_CH_TYPE_INBOUND_COALESCED = 3, 860cbf2608SManivannan Sadhasivam }; 870cbf2608SManivannan Sadhasivam 880cbf2608SManivannan Sadhasivam /** 894d12a897SRandy Dunlap * struct image_info - Firmware and RDDM table 904d12a897SRandy Dunlap * @mhi_buf: Buffer for firmware and RDDM table 914d12a897SRandy Dunlap * @entries: # of entries in table 923000f85bSManivannan Sadhasivam */ 933000f85bSManivannan Sadhasivam struct image_info { 943000f85bSManivannan Sadhasivam struct mhi_buf *mhi_buf; 954d12a897SRandy Dunlap /* private: from internal.h */ 963000f85bSManivannan Sadhasivam struct bhi_vec_entry *bhi_vec; 974d12a897SRandy Dunlap /* public: */ 983000f85bSManivannan Sadhasivam u32 entries; 993000f85bSManivannan Sadhasivam }; 1003000f85bSManivannan Sadhasivam 1013000f85bSManivannan Sadhasivam /** 1021d3173a3SManivannan Sadhasivam * struct mhi_link_info - BW requirement 1031d3173a3SManivannan Sadhasivam * target_link_speed - Link speed as defined by TLS bits in LinkControl reg 1041d3173a3SManivannan Sadhasivam * target_link_width - Link width as defined by NLW bits in LinkStatus reg 1051d3173a3SManivannan Sadhasivam */ 1061d3173a3SManivannan Sadhasivam struct mhi_link_info { 1071d3173a3SManivannan Sadhasivam unsigned int target_link_speed; 1081d3173a3SManivannan Sadhasivam unsigned int target_link_width; 1091d3173a3SManivannan Sadhasivam }; 1101d3173a3SManivannan Sadhasivam 1111d3173a3SManivannan Sadhasivam /** 1120cbf2608SManivannan Sadhasivam * enum mhi_ee_type - Execution environment types 1130cbf2608SManivannan Sadhasivam * @MHI_EE_PBL: Primary Bootloader 1140cbf2608SManivannan Sadhasivam * @MHI_EE_SBL: Secondary Bootloader 1150cbf2608SManivannan Sadhasivam * @MHI_EE_AMSS: Modem, aka the primary runtime EE 1160cbf2608SManivannan Sadhasivam * @MHI_EE_RDDM: Ram dump download mode 1170cbf2608SManivannan Sadhasivam * @MHI_EE_WFW: WLAN firmware mode 1180cbf2608SManivannan Sadhasivam * @MHI_EE_PTHRU: Passthrough 1190cbf2608SManivannan Sadhasivam * @MHI_EE_EDL: Embedded downloader 12066ac7985SCarl Yin * @MHI_EE_FP: Flash Programmer Environment 1210cbf2608SManivannan Sadhasivam */ 1220cbf2608SManivannan Sadhasivam enum mhi_ee_type { 1230cbf2608SManivannan Sadhasivam MHI_EE_PBL, 1240cbf2608SManivannan Sadhasivam MHI_EE_SBL, 1250cbf2608SManivannan Sadhasivam MHI_EE_AMSS, 1260cbf2608SManivannan Sadhasivam MHI_EE_RDDM, 1270cbf2608SManivannan Sadhasivam MHI_EE_WFW, 1280cbf2608SManivannan Sadhasivam MHI_EE_PTHRU, 1290cbf2608SManivannan Sadhasivam MHI_EE_EDL, 13066ac7985SCarl Yin MHI_EE_FP, 13166ac7985SCarl Yin MHI_EE_MAX_SUPPORTED = MHI_EE_FP, 1320cbf2608SManivannan Sadhasivam MHI_EE_DISABLE_TRANSITION, /* local EE, not related to mhi spec */ 1330cbf2608SManivannan Sadhasivam MHI_EE_NOT_SUPPORTED, 1340cbf2608SManivannan Sadhasivam MHI_EE_MAX, 1350cbf2608SManivannan Sadhasivam }; 1360cbf2608SManivannan Sadhasivam 1370cbf2608SManivannan Sadhasivam /** 138a6e2e352SManivannan Sadhasivam * enum mhi_state - MHI states 139a6e2e352SManivannan Sadhasivam * @MHI_STATE_RESET: Reset state 140a6e2e352SManivannan Sadhasivam * @MHI_STATE_READY: Ready state 141a6e2e352SManivannan Sadhasivam * @MHI_STATE_M0: M0 state 142a6e2e352SManivannan Sadhasivam * @MHI_STATE_M1: M1 state 143a6e2e352SManivannan Sadhasivam * @MHI_STATE_M2: M2 state 144a6e2e352SManivannan Sadhasivam * @MHI_STATE_M3: M3 state 145a6e2e352SManivannan Sadhasivam * @MHI_STATE_M3_FAST: M3 Fast state 146a6e2e352SManivannan Sadhasivam * @MHI_STATE_BHI: BHI state 147a6e2e352SManivannan Sadhasivam * @MHI_STATE_SYS_ERR: System Error state 148a6e2e352SManivannan Sadhasivam */ 149a6e2e352SManivannan Sadhasivam enum mhi_state { 150a6e2e352SManivannan Sadhasivam MHI_STATE_RESET = 0x0, 151a6e2e352SManivannan Sadhasivam MHI_STATE_READY = 0x1, 152a6e2e352SManivannan Sadhasivam MHI_STATE_M0 = 0x2, 153a6e2e352SManivannan Sadhasivam MHI_STATE_M1 = 0x3, 154a6e2e352SManivannan Sadhasivam MHI_STATE_M2 = 0x4, 155a6e2e352SManivannan Sadhasivam MHI_STATE_M3 = 0x5, 156a6e2e352SManivannan Sadhasivam MHI_STATE_M3_FAST = 0x6, 157a6e2e352SManivannan Sadhasivam MHI_STATE_BHI = 0x7, 158a6e2e352SManivannan Sadhasivam MHI_STATE_SYS_ERR = 0xFF, 159a6e2e352SManivannan Sadhasivam MHI_STATE_MAX, 160a6e2e352SManivannan Sadhasivam }; 161a6e2e352SManivannan Sadhasivam 162a6e2e352SManivannan Sadhasivam /** 1630cbf2608SManivannan Sadhasivam * enum mhi_ch_ee_mask - Execution environment mask for channel 1640cbf2608SManivannan Sadhasivam * @MHI_CH_EE_PBL: Allow channel to be used in PBL EE 1650cbf2608SManivannan Sadhasivam * @MHI_CH_EE_SBL: Allow channel to be used in SBL EE 1660cbf2608SManivannan Sadhasivam * @MHI_CH_EE_AMSS: Allow channel to be used in AMSS EE 1670cbf2608SManivannan Sadhasivam * @MHI_CH_EE_RDDM: Allow channel to be used in RDDM EE 1680cbf2608SManivannan Sadhasivam * @MHI_CH_EE_PTHRU: Allow channel to be used in PTHRU EE 1690cbf2608SManivannan Sadhasivam * @MHI_CH_EE_WFW: Allow channel to be used in WFW EE 1700cbf2608SManivannan Sadhasivam * @MHI_CH_EE_EDL: Allow channel to be used in EDL EE 1710cbf2608SManivannan Sadhasivam */ 1720cbf2608SManivannan Sadhasivam enum mhi_ch_ee_mask { 1730cbf2608SManivannan Sadhasivam MHI_CH_EE_PBL = BIT(MHI_EE_PBL), 1740cbf2608SManivannan Sadhasivam MHI_CH_EE_SBL = BIT(MHI_EE_SBL), 1750cbf2608SManivannan Sadhasivam MHI_CH_EE_AMSS = BIT(MHI_EE_AMSS), 1760cbf2608SManivannan Sadhasivam MHI_CH_EE_RDDM = BIT(MHI_EE_RDDM), 1770cbf2608SManivannan Sadhasivam MHI_CH_EE_PTHRU = BIT(MHI_EE_PTHRU), 1780cbf2608SManivannan Sadhasivam MHI_CH_EE_WFW = BIT(MHI_EE_WFW), 1790cbf2608SManivannan Sadhasivam MHI_CH_EE_EDL = BIT(MHI_EE_EDL), 1800cbf2608SManivannan Sadhasivam }; 1810cbf2608SManivannan Sadhasivam 1820cbf2608SManivannan Sadhasivam /** 1830cbf2608SManivannan Sadhasivam * enum mhi_er_data_type - Event ring data types 1840cbf2608SManivannan Sadhasivam * @MHI_ER_DATA: Only client data over this ring 1850cbf2608SManivannan Sadhasivam * @MHI_ER_CTRL: MHI control data and client data 1860cbf2608SManivannan Sadhasivam */ 1870cbf2608SManivannan Sadhasivam enum mhi_er_data_type { 1880cbf2608SManivannan Sadhasivam MHI_ER_DATA, 1890cbf2608SManivannan Sadhasivam MHI_ER_CTRL, 1900cbf2608SManivannan Sadhasivam }; 1910cbf2608SManivannan Sadhasivam 1920cbf2608SManivannan Sadhasivam /** 1930cbf2608SManivannan Sadhasivam * enum mhi_db_brst_mode - Doorbell mode 1940cbf2608SManivannan Sadhasivam * @MHI_DB_BRST_DISABLE: Burst mode disable 1950cbf2608SManivannan Sadhasivam * @MHI_DB_BRST_ENABLE: Burst mode enable 1960cbf2608SManivannan Sadhasivam */ 1970cbf2608SManivannan Sadhasivam enum mhi_db_brst_mode { 1980cbf2608SManivannan Sadhasivam MHI_DB_BRST_DISABLE = 0x2, 1990cbf2608SManivannan Sadhasivam MHI_DB_BRST_ENABLE = 0x3, 2000cbf2608SManivannan Sadhasivam }; 2010cbf2608SManivannan Sadhasivam 2020cbf2608SManivannan Sadhasivam /** 2030cbf2608SManivannan Sadhasivam * struct mhi_channel_config - Channel configuration structure for controller 2040cbf2608SManivannan Sadhasivam * @name: The name of this channel 2050cbf2608SManivannan Sadhasivam * @num: The number assigned to this channel 2060cbf2608SManivannan Sadhasivam * @num_elements: The number of elements that can be queued to this channel 2070cbf2608SManivannan Sadhasivam * @local_elements: The local ring length of the channel 208a503d162SJarvis Jiang * @event_ring: The event ring index that services this channel 2090cbf2608SManivannan Sadhasivam * @dir: Direction that data may flow on this channel 2100cbf2608SManivannan Sadhasivam * @type: Channel type 2110cbf2608SManivannan Sadhasivam * @ee_mask: Execution Environment mask for this channel 2120cbf2608SManivannan Sadhasivam * @pollcfg: Polling configuration for burst mode. 0 is default. milliseconds 2130cbf2608SManivannan Sadhasivam for UL channels, multiple of 8 ring elements for DL channels 2140cbf2608SManivannan Sadhasivam * @doorbell: Doorbell mode 2150cbf2608SManivannan Sadhasivam * @lpm_notify: The channel master requires low power mode notifications 2160cbf2608SManivannan Sadhasivam * @offload_channel: The client manages the channel completely 2170cbf2608SManivannan Sadhasivam * @doorbell_mode_switch: Channel switches to doorbell mode on M0 transition 2180cbf2608SManivannan Sadhasivam * @auto_queue: Framework will automatically queue buffers for DL traffic 219da1c4f85SManivannan Sadhasivam * @wake-capable: Channel capable of waking up the system 2200cbf2608SManivannan Sadhasivam */ 2210cbf2608SManivannan Sadhasivam struct mhi_channel_config { 2220cbf2608SManivannan Sadhasivam char *name; 2230cbf2608SManivannan Sadhasivam u32 num; 2240cbf2608SManivannan Sadhasivam u32 num_elements; 2250cbf2608SManivannan Sadhasivam u32 local_elements; 2260cbf2608SManivannan Sadhasivam u32 event_ring; 2270cbf2608SManivannan Sadhasivam enum dma_data_direction dir; 2280cbf2608SManivannan Sadhasivam enum mhi_ch_type type; 2290cbf2608SManivannan Sadhasivam u32 ee_mask; 2300cbf2608SManivannan Sadhasivam u32 pollcfg; 2310cbf2608SManivannan Sadhasivam enum mhi_db_brst_mode doorbell; 2320cbf2608SManivannan Sadhasivam bool lpm_notify; 2330cbf2608SManivannan Sadhasivam bool offload_channel; 2340cbf2608SManivannan Sadhasivam bool doorbell_mode_switch; 2350cbf2608SManivannan Sadhasivam bool auto_queue; 236da1c4f85SManivannan Sadhasivam bool wake_capable; 2370cbf2608SManivannan Sadhasivam }; 2380cbf2608SManivannan Sadhasivam 2390cbf2608SManivannan Sadhasivam /** 2400cbf2608SManivannan Sadhasivam * struct mhi_event_config - Event ring configuration structure for controller 2410cbf2608SManivannan Sadhasivam * @num_elements: The number of elements that can be queued to this ring 2420cbf2608SManivannan Sadhasivam * @irq_moderation_ms: Delay irq for additional events to be aggregated 2430cbf2608SManivannan Sadhasivam * @irq: IRQ associated with this ring 2440cbf2608SManivannan Sadhasivam * @channel: Dedicated channel number. U32_MAX indicates a non-dedicated ring 2450cbf2608SManivannan Sadhasivam * @priority: Priority of this ring. Use 1 for now 2460cbf2608SManivannan Sadhasivam * @mode: Doorbell mode 2470cbf2608SManivannan Sadhasivam * @data_type: Type of data this ring will process 2480cbf2608SManivannan Sadhasivam * @hardware_event: This ring is associated with hardware channels 2490cbf2608SManivannan Sadhasivam * @client_managed: This ring is client managed 2500cbf2608SManivannan Sadhasivam * @offload_channel: This ring is associated with an offloaded channel 2510cbf2608SManivannan Sadhasivam */ 2520cbf2608SManivannan Sadhasivam struct mhi_event_config { 2530cbf2608SManivannan Sadhasivam u32 num_elements; 2540cbf2608SManivannan Sadhasivam u32 irq_moderation_ms; 2550cbf2608SManivannan Sadhasivam u32 irq; 2560cbf2608SManivannan Sadhasivam u32 channel; 2570cbf2608SManivannan Sadhasivam u32 priority; 2580cbf2608SManivannan Sadhasivam enum mhi_db_brst_mode mode; 2590cbf2608SManivannan Sadhasivam enum mhi_er_data_type data_type; 2600cbf2608SManivannan Sadhasivam bool hardware_event; 2610cbf2608SManivannan Sadhasivam bool client_managed; 2620cbf2608SManivannan Sadhasivam bool offload_channel; 2630cbf2608SManivannan Sadhasivam }; 2640cbf2608SManivannan Sadhasivam 2650cbf2608SManivannan Sadhasivam /** 2660cbf2608SManivannan Sadhasivam * struct mhi_controller_config - Root MHI controller configuration 2670cbf2608SManivannan Sadhasivam * @max_channels: Maximum number of channels supported 2680cbf2608SManivannan Sadhasivam * @timeout_ms: Timeout value for operations. 0 means use default 2690cbf2608SManivannan Sadhasivam * @buf_len: Size of automatically allocated buffers. 0 means use default 2700cbf2608SManivannan Sadhasivam * @num_channels: Number of channels defined in @ch_cfg 2710cbf2608SManivannan Sadhasivam * @ch_cfg: Array of defined channels 2720cbf2608SManivannan Sadhasivam * @num_events: Number of event rings defined in @event_cfg 2730cbf2608SManivannan Sadhasivam * @event_cfg: Array of defined event rings 2740cbf2608SManivannan Sadhasivam * @use_bounce_buf: Use a bounce buffer pool due to limited DDR access 2750cbf2608SManivannan Sadhasivam * @m2_no_db: Host is not allowed to ring DB in M2 state 2760cbf2608SManivannan Sadhasivam */ 2770cbf2608SManivannan Sadhasivam struct mhi_controller_config { 2780cbf2608SManivannan Sadhasivam u32 max_channels; 2790cbf2608SManivannan Sadhasivam u32 timeout_ms; 2800cbf2608SManivannan Sadhasivam u32 buf_len; 2810cbf2608SManivannan Sadhasivam u32 num_channels; 282f38173a7SHemant Kumar const struct mhi_channel_config *ch_cfg; 2830cbf2608SManivannan Sadhasivam u32 num_events; 284fcba4b20SLoic Poulain struct mhi_event_config *event_cfg; 2850cbf2608SManivannan Sadhasivam bool use_bounce_buf; 2860cbf2608SManivannan Sadhasivam bool m2_no_db; 2870cbf2608SManivannan Sadhasivam }; 2880cbf2608SManivannan Sadhasivam 2890cbf2608SManivannan Sadhasivam /** 2900cbf2608SManivannan Sadhasivam * struct mhi_controller - Master MHI controller structure 2910cbf2608SManivannan Sadhasivam * @cntrl_dev: Pointer to the struct device of physical bus acting as the MHI 2920cbf2608SManivannan Sadhasivam * controller (required) 2930cbf2608SManivannan Sadhasivam * @mhi_dev: MHI device instance for the controller 294c7bd825eSBhaumik Bhatt * @debugfs_dentry: MHI controller debugfs directory 2950cbf2608SManivannan Sadhasivam * @regs: Base address of MHI MMIO register space (required) 2966cd330aeSManivannan Sadhasivam * @bhi: Points to base of MHI BHI register space 2973000f85bSManivannan Sadhasivam * @bhie: Points to base of MHI BHIe register space 2986cd330aeSManivannan Sadhasivam * @wake_db: MHI WAKE doorbell register address 2990cbf2608SManivannan Sadhasivam * @iova_start: IOMMU starting address for data (required) 3000cbf2608SManivannan Sadhasivam * @iova_stop: IOMMU stop address for data (required) 3014d5f5283SBhaumik Bhatt * @fw_image: Firmware image name for normal booting (optional) 3020cbf2608SManivannan Sadhasivam * @edl_image: Firmware image name for emergency download mode (optional) 3036fdfdd27SManivannan Sadhasivam * @rddm_size: RAM dump size that host should allocate for debugging purpose 3040cbf2608SManivannan Sadhasivam * @sbl_size: SBL image size downloaded through BHIe (optional) 3050cbf2608SManivannan Sadhasivam * @seg_len: BHIe vector size (optional) 3063000f85bSManivannan Sadhasivam * @fbc_image: Points to firmware image buffer 3076fdfdd27SManivannan Sadhasivam * @rddm_image: Points to RAM dump buffer 3080cbf2608SManivannan Sadhasivam * @mhi_chan: Points to the channel configuration table 3090cbf2608SManivannan Sadhasivam * @lpm_chans: List of channels that require LPM notifications 3100cbf2608SManivannan Sadhasivam * @irq: base irq # to request (required) 3110cbf2608SManivannan Sadhasivam * @max_chan: Maximum number of channels the controller supports 3120cbf2608SManivannan Sadhasivam * @total_ev_rings: Total # of event rings allocated 3130cbf2608SManivannan Sadhasivam * @hw_ev_rings: Number of hardware event rings 3140cbf2608SManivannan Sadhasivam * @sw_ev_rings: Number of software event rings 3150cbf2608SManivannan Sadhasivam * @nr_irqs: Number of IRQ allocated by bus master (required) 3163316ab2bSManivannan Sadhasivam * @family_number: MHI controller family number 3173316ab2bSManivannan Sadhasivam * @device_number: MHI controller device number 3183316ab2bSManivannan Sadhasivam * @major_version: MHI controller major revision number 3193316ab2bSManivannan Sadhasivam * @minor_version: MHI controller minor revision number 3208e3729bfSBhaumik Bhatt * @serial_number: MHI controller serial number obtained from BHI 3218e3729bfSBhaumik Bhatt * @oem_pk_hash: MHI controller OEM PK Hash obtained from BHI 3220cbf2608SManivannan Sadhasivam * @mhi_event: MHI event ring configurations table 3230cbf2608SManivannan Sadhasivam * @mhi_cmd: MHI command ring configurations table 3240cbf2608SManivannan Sadhasivam * @mhi_ctxt: MHI device context, shared memory between host and device 3250cbf2608SManivannan Sadhasivam * @pm_mutex: Mutex for suspend/resume operation 3260cbf2608SManivannan Sadhasivam * @pm_lock: Lock for protecting MHI power management state 3270cbf2608SManivannan Sadhasivam * @timeout_ms: Timeout in ms for state transitions 3280cbf2608SManivannan Sadhasivam * @pm_state: MHI power management state 3290cbf2608SManivannan Sadhasivam * @db_access: DB access states 3300cbf2608SManivannan Sadhasivam * @ee: MHI device execution environment 331a6e2e352SManivannan Sadhasivam * @dev_state: MHI device state 3320cbf2608SManivannan Sadhasivam * @dev_wake: Device wakeup count 3330cbf2608SManivannan Sadhasivam * @pending_pkts: Pending packets for the controller 334601455daSBhaumik Bhatt * @M0, M2, M3: Counters to track number of device MHI state changes 3350cbf2608SManivannan Sadhasivam * @transition_list: List of MHI state transitions 3360cbf2608SManivannan Sadhasivam * @transition_lock: Lock for protecting MHI state transition list 3370cbf2608SManivannan Sadhasivam * @wlock: Lock for protecting device wakeup 3381d3173a3SManivannan Sadhasivam * @mhi_link_info: Device bandwidth info 3390cbf2608SManivannan Sadhasivam * @st_worker: State transition worker 3408f703978SBhaumik Bhatt * @hiprio_wq: High priority workqueue for MHI work such as state transitions 3410cbf2608SManivannan Sadhasivam * @state_event: State change event 3420cbf2608SManivannan Sadhasivam * @status_cb: CB function to notify power states of the device (required) 3430cbf2608SManivannan Sadhasivam * @wake_get: CB function to assert device wake (optional) 3440cbf2608SManivannan Sadhasivam * @wake_put: CB function to de-assert device wake (optional) 3450cbf2608SManivannan Sadhasivam * @wake_toggle: CB function to assert and de-assert device wake (optional) 3460cbf2608SManivannan Sadhasivam * @runtime_get: CB function to controller runtime resume (required) 347af2e5881SJeffrey Hugo * @runtime_put: CB function to decrement pm usage (required) 348189ff97cSManivannan Sadhasivam * @map_single: CB function to create TRE buffer 349189ff97cSManivannan Sadhasivam * @unmap_single: CB function to destroy TRE buffer 35045723a44SJeffrey Hugo * @read_reg: Read a MHI register via the physical link (required) 35145723a44SJeffrey Hugo * @write_reg: Write a MHI register via the physical link (required) 352b5a8d233SLoic Poulain * @reset: Controller specific reset function (optional) 3530cbf2608SManivannan Sadhasivam * @buffer_len: Bounce buffer length 354206e7383SLoic Poulain * @index: Index of the MHI controller instance 3550cbf2608SManivannan Sadhasivam * @bounce_buf: Use of bounce buffer 3560cbf2608SManivannan Sadhasivam * @fbc_download: MHI host needs to do complete image transfer (optional) 3570cbf2608SManivannan Sadhasivam * @wake_set: Device wakeup set flag 3586ffcc18dSCarl Huang * @irq_flags: irq flags passed to request_irq (optional) 3590cbf2608SManivannan Sadhasivam * 3600cbf2608SManivannan Sadhasivam * Fields marked as (required) need to be populated by the controller driver 3610cbf2608SManivannan Sadhasivam * before calling mhi_register_controller(). For the fields marked as (optional) 3620cbf2608SManivannan Sadhasivam * they can be populated depending on the usecase. 3633316ab2bSManivannan Sadhasivam * 3643316ab2bSManivannan Sadhasivam * The following fields are present for the purpose of implementing any device 3653316ab2bSManivannan Sadhasivam * specific quirks or customizations for specific MHI revisions used in device 3663316ab2bSManivannan Sadhasivam * by the controller drivers. The MHI stack will just populate these fields 3673316ab2bSManivannan Sadhasivam * during mhi_register_controller(): 3683316ab2bSManivannan Sadhasivam * family_number 3693316ab2bSManivannan Sadhasivam * device_number 3703316ab2bSManivannan Sadhasivam * major_version 3713316ab2bSManivannan Sadhasivam * minor_version 3720cbf2608SManivannan Sadhasivam */ 3730cbf2608SManivannan Sadhasivam struct mhi_controller { 3740cbf2608SManivannan Sadhasivam struct device *cntrl_dev; 3750cbf2608SManivannan Sadhasivam struct mhi_device *mhi_dev; 376c7bd825eSBhaumik Bhatt struct dentry *debugfs_dentry; 3770cbf2608SManivannan Sadhasivam void __iomem *regs; 3786cd330aeSManivannan Sadhasivam void __iomem *bhi; 3793000f85bSManivannan Sadhasivam void __iomem *bhie; 3806cd330aeSManivannan Sadhasivam void __iomem *wake_db; 381a6e2e352SManivannan Sadhasivam 3820cbf2608SManivannan Sadhasivam dma_addr_t iova_start; 3830cbf2608SManivannan Sadhasivam dma_addr_t iova_stop; 3840cbf2608SManivannan Sadhasivam const char *fw_image; 3850cbf2608SManivannan Sadhasivam const char *edl_image; 3866fdfdd27SManivannan Sadhasivam size_t rddm_size; 3870cbf2608SManivannan Sadhasivam size_t sbl_size; 3880cbf2608SManivannan Sadhasivam size_t seg_len; 3893000f85bSManivannan Sadhasivam struct image_info *fbc_image; 3906fdfdd27SManivannan Sadhasivam struct image_info *rddm_image; 3910cbf2608SManivannan Sadhasivam struct mhi_chan *mhi_chan; 3920cbf2608SManivannan Sadhasivam struct list_head lpm_chans; 3930cbf2608SManivannan Sadhasivam int *irq; 3940cbf2608SManivannan Sadhasivam u32 max_chan; 3950cbf2608SManivannan Sadhasivam u32 total_ev_rings; 3960cbf2608SManivannan Sadhasivam u32 hw_ev_rings; 3970cbf2608SManivannan Sadhasivam u32 sw_ev_rings; 3980cbf2608SManivannan Sadhasivam u32 nr_irqs; 3993316ab2bSManivannan Sadhasivam u32 family_number; 4003316ab2bSManivannan Sadhasivam u32 device_number; 4013316ab2bSManivannan Sadhasivam u32 major_version; 4023316ab2bSManivannan Sadhasivam u32 minor_version; 4038e3729bfSBhaumik Bhatt u32 serial_number; 4048e3729bfSBhaumik Bhatt u32 oem_pk_hash[MHI_MAX_OEM_PK_HASH_SEGMENTS]; 4050cbf2608SManivannan Sadhasivam 4060cbf2608SManivannan Sadhasivam struct mhi_event *mhi_event; 4070cbf2608SManivannan Sadhasivam struct mhi_cmd *mhi_cmd; 4080cbf2608SManivannan Sadhasivam struct mhi_ctxt *mhi_ctxt; 4090cbf2608SManivannan Sadhasivam 4100cbf2608SManivannan Sadhasivam struct mutex pm_mutex; 4110cbf2608SManivannan Sadhasivam rwlock_t pm_lock; 4120cbf2608SManivannan Sadhasivam u32 timeout_ms; 4130cbf2608SManivannan Sadhasivam u32 pm_state; 4140cbf2608SManivannan Sadhasivam u32 db_access; 4150cbf2608SManivannan Sadhasivam enum mhi_ee_type ee; 416a6e2e352SManivannan Sadhasivam enum mhi_state dev_state; 4170cbf2608SManivannan Sadhasivam atomic_t dev_wake; 4180cbf2608SManivannan Sadhasivam atomic_t pending_pkts; 419601455daSBhaumik Bhatt u32 M0, M2, M3; 4200cbf2608SManivannan Sadhasivam struct list_head transition_list; 4210cbf2608SManivannan Sadhasivam spinlock_t transition_lock; 4220cbf2608SManivannan Sadhasivam spinlock_t wlock; 4231d3173a3SManivannan Sadhasivam struct mhi_link_info mhi_link_info; 4240cbf2608SManivannan Sadhasivam struct work_struct st_worker; 4258f703978SBhaumik Bhatt struct workqueue_struct *hiprio_wq; 4260cbf2608SManivannan Sadhasivam wait_queue_head_t state_event; 4270cbf2608SManivannan Sadhasivam 4280cbf2608SManivannan Sadhasivam void (*status_cb)(struct mhi_controller *mhi_cntrl, 4290cbf2608SManivannan Sadhasivam enum mhi_callback cb); 4300cbf2608SManivannan Sadhasivam void (*wake_get)(struct mhi_controller *mhi_cntrl, bool override); 4310cbf2608SManivannan Sadhasivam void (*wake_put)(struct mhi_controller *mhi_cntrl, bool override); 4320cbf2608SManivannan Sadhasivam void (*wake_toggle)(struct mhi_controller *mhi_cntrl); 4330cbf2608SManivannan Sadhasivam int (*runtime_get)(struct mhi_controller *mhi_cntrl); 4340cbf2608SManivannan Sadhasivam void (*runtime_put)(struct mhi_controller *mhi_cntrl); 435189ff97cSManivannan Sadhasivam int (*map_single)(struct mhi_controller *mhi_cntrl, 436189ff97cSManivannan Sadhasivam struct mhi_buf_info *buf); 437189ff97cSManivannan Sadhasivam void (*unmap_single)(struct mhi_controller *mhi_cntrl, 438189ff97cSManivannan Sadhasivam struct mhi_buf_info *buf); 43945723a44SJeffrey Hugo int (*read_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr, 44045723a44SJeffrey Hugo u32 *out); 44145723a44SJeffrey Hugo void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr, 44245723a44SJeffrey Hugo u32 val); 443b5a8d233SLoic Poulain void (*reset)(struct mhi_controller *mhi_cntrl); 4440cbf2608SManivannan Sadhasivam 4450cbf2608SManivannan Sadhasivam size_t buffer_len; 446206e7383SLoic Poulain int index; 4470cbf2608SManivannan Sadhasivam bool bounce_buf; 4480cbf2608SManivannan Sadhasivam bool fbc_download; 4490cbf2608SManivannan Sadhasivam bool wake_set; 4506ffcc18dSCarl Huang unsigned long irq_flags; 4510cbf2608SManivannan Sadhasivam }; 4520cbf2608SManivannan Sadhasivam 4530cbf2608SManivannan Sadhasivam /** 4545aa93f05SBhaumik Bhatt * struct mhi_device - Structure representing an MHI device which binds 4555aa93f05SBhaumik Bhatt * to channels or is associated with controllers 4560cbf2608SManivannan Sadhasivam * @id: Pointer to MHI device ID struct 4575aa93f05SBhaumik Bhatt * @name: Name of the associated MHI device 4580cbf2608SManivannan Sadhasivam * @mhi_cntrl: Controller the device belongs to 4590cbf2608SManivannan Sadhasivam * @ul_chan: UL channel for the device 4600cbf2608SManivannan Sadhasivam * @dl_chan: DL channel for the device 4610cbf2608SManivannan Sadhasivam * @dev: Driver model device node for the MHI device 4620cbf2608SManivannan Sadhasivam * @dev_type: MHI device type 463e755cadbSManivannan Sadhasivam * @ul_chan_id: MHI channel id for UL transfer 464e755cadbSManivannan Sadhasivam * @dl_chan_id: MHI channel id for DL transfer 4650cbf2608SManivannan Sadhasivam * @dev_wake: Device wakeup counter 4660cbf2608SManivannan Sadhasivam */ 4670cbf2608SManivannan Sadhasivam struct mhi_device { 4680cbf2608SManivannan Sadhasivam const struct mhi_device_id *id; 4695aa93f05SBhaumik Bhatt const char *name; 4700cbf2608SManivannan Sadhasivam struct mhi_controller *mhi_cntrl; 4710cbf2608SManivannan Sadhasivam struct mhi_chan *ul_chan; 4720cbf2608SManivannan Sadhasivam struct mhi_chan *dl_chan; 4730cbf2608SManivannan Sadhasivam struct device dev; 4740cbf2608SManivannan Sadhasivam enum mhi_device_type dev_type; 475e755cadbSManivannan Sadhasivam int ul_chan_id; 476e755cadbSManivannan Sadhasivam int dl_chan_id; 4770cbf2608SManivannan Sadhasivam u32 dev_wake; 4780cbf2608SManivannan Sadhasivam }; 4790cbf2608SManivannan Sadhasivam 4800cbf2608SManivannan Sadhasivam /** 4810cbf2608SManivannan Sadhasivam * struct mhi_result - Completed buffer information 4820cbf2608SManivannan Sadhasivam * @buf_addr: Address of data buffer 4830cbf2608SManivannan Sadhasivam * @bytes_xferd: # of bytes transferred 4840cbf2608SManivannan Sadhasivam * @dir: Channel direction 4850cbf2608SManivannan Sadhasivam * @transaction_status: Status of last transaction 4860cbf2608SManivannan Sadhasivam */ 4870cbf2608SManivannan Sadhasivam struct mhi_result { 4880cbf2608SManivannan Sadhasivam void *buf_addr; 4890cbf2608SManivannan Sadhasivam size_t bytes_xferd; 4900cbf2608SManivannan Sadhasivam enum dma_data_direction dir; 4910cbf2608SManivannan Sadhasivam int transaction_status; 4920cbf2608SManivannan Sadhasivam }; 4930cbf2608SManivannan Sadhasivam 494e755cadbSManivannan Sadhasivam /** 495a6e2e352SManivannan Sadhasivam * struct mhi_buf - MHI Buffer description 496a6e2e352SManivannan Sadhasivam * @buf: Virtual address of the buffer 497a6e2e352SManivannan Sadhasivam * @name: Buffer label. For offload channel, configurations name must be: 498a6e2e352SManivannan Sadhasivam * ECA - Event context array data 499a6e2e352SManivannan Sadhasivam * CCA - Channel context array data 500a6e2e352SManivannan Sadhasivam * @dma_addr: IOMMU address of the buffer 501a6e2e352SManivannan Sadhasivam * @len: # of bytes 502a6e2e352SManivannan Sadhasivam */ 503a6e2e352SManivannan Sadhasivam struct mhi_buf { 504a6e2e352SManivannan Sadhasivam void *buf; 505a6e2e352SManivannan Sadhasivam const char *name; 506a6e2e352SManivannan Sadhasivam dma_addr_t dma_addr; 507a6e2e352SManivannan Sadhasivam size_t len; 508a6e2e352SManivannan Sadhasivam }; 509a6e2e352SManivannan Sadhasivam 510a6e2e352SManivannan Sadhasivam /** 511e755cadbSManivannan Sadhasivam * struct mhi_driver - Structure representing a MHI client driver 512e755cadbSManivannan Sadhasivam * @probe: CB function for client driver probe function 513e755cadbSManivannan Sadhasivam * @remove: CB function for client driver remove function 514e755cadbSManivannan Sadhasivam * @ul_xfer_cb: CB function for UL data transfer 515e755cadbSManivannan Sadhasivam * @dl_xfer_cb: CB function for DL data transfer 516e755cadbSManivannan Sadhasivam * @status_cb: CB functions for asynchronous status 517e755cadbSManivannan Sadhasivam * @driver: Device driver model driver 518e755cadbSManivannan Sadhasivam */ 519e755cadbSManivannan Sadhasivam struct mhi_driver { 520e755cadbSManivannan Sadhasivam const struct mhi_device_id *id_table; 521e755cadbSManivannan Sadhasivam int (*probe)(struct mhi_device *mhi_dev, 522e755cadbSManivannan Sadhasivam const struct mhi_device_id *id); 523e755cadbSManivannan Sadhasivam void (*remove)(struct mhi_device *mhi_dev); 524e755cadbSManivannan Sadhasivam void (*ul_xfer_cb)(struct mhi_device *mhi_dev, 525e755cadbSManivannan Sadhasivam struct mhi_result *result); 526e755cadbSManivannan Sadhasivam void (*dl_xfer_cb)(struct mhi_device *mhi_dev, 527e755cadbSManivannan Sadhasivam struct mhi_result *result); 528e755cadbSManivannan Sadhasivam void (*status_cb)(struct mhi_device *mhi_dev, enum mhi_callback mhi_cb); 529e755cadbSManivannan Sadhasivam struct device_driver driver; 530e755cadbSManivannan Sadhasivam }; 531e755cadbSManivannan Sadhasivam 532e755cadbSManivannan Sadhasivam #define to_mhi_driver(drv) container_of(drv, struct mhi_driver, driver) 5330cbf2608SManivannan Sadhasivam #define to_mhi_device(dev) container_of(dev, struct mhi_device, dev) 5340cbf2608SManivannan Sadhasivam 5350cbf2608SManivannan Sadhasivam /** 536f42dfbe8SBhaumik Bhatt * mhi_alloc_controller - Allocate the MHI Controller structure 537f42dfbe8SBhaumik Bhatt * Allocate the mhi_controller structure using zero initialized memory 538f42dfbe8SBhaumik Bhatt */ 539f42dfbe8SBhaumik Bhatt struct mhi_controller *mhi_alloc_controller(void); 540f42dfbe8SBhaumik Bhatt 541f42dfbe8SBhaumik Bhatt /** 542f42dfbe8SBhaumik Bhatt * mhi_free_controller - Free the MHI Controller structure 543f42dfbe8SBhaumik Bhatt * Free the mhi_controller structure which was previously allocated 544f42dfbe8SBhaumik Bhatt */ 545f42dfbe8SBhaumik Bhatt void mhi_free_controller(struct mhi_controller *mhi_cntrl); 546f42dfbe8SBhaumik Bhatt 547f42dfbe8SBhaumik Bhatt /** 5480cbf2608SManivannan Sadhasivam * mhi_register_controller - Register MHI controller 5490cbf2608SManivannan Sadhasivam * @mhi_cntrl: MHI controller to register 5500cbf2608SManivannan Sadhasivam * @config: Configuration to use for the controller 5510cbf2608SManivannan Sadhasivam */ 5520cbf2608SManivannan Sadhasivam int mhi_register_controller(struct mhi_controller *mhi_cntrl, 553f38173a7SHemant Kumar const struct mhi_controller_config *config); 5540cbf2608SManivannan Sadhasivam 5550cbf2608SManivannan Sadhasivam /** 5560cbf2608SManivannan Sadhasivam * mhi_unregister_controller - Unregister MHI controller 5570cbf2608SManivannan Sadhasivam * @mhi_cntrl: MHI controller to unregister 5580cbf2608SManivannan Sadhasivam */ 5590cbf2608SManivannan Sadhasivam void mhi_unregister_controller(struct mhi_controller *mhi_cntrl); 5600cbf2608SManivannan Sadhasivam 56182174738SManivannan Sadhasivam /* 56282174738SManivannan Sadhasivam * module_mhi_driver() - Helper macro for drivers that don't do 56382174738SManivannan Sadhasivam * anything special other than using default mhi_driver_register() and 56482174738SManivannan Sadhasivam * mhi_driver_unregister(). This eliminates a lot of boilerplate. 56582174738SManivannan Sadhasivam * Each module may only use this macro once. 566e755cadbSManivannan Sadhasivam */ 56782174738SManivannan Sadhasivam #define module_mhi_driver(mhi_drv) \ 56882174738SManivannan Sadhasivam module_driver(mhi_drv, mhi_driver_register, \ 56982174738SManivannan Sadhasivam mhi_driver_unregister) 57082174738SManivannan Sadhasivam 57182174738SManivannan Sadhasivam /* 57282174738SManivannan Sadhasivam * Macro to avoid include chaining to get THIS_MODULE 57382174738SManivannan Sadhasivam */ 57482174738SManivannan Sadhasivam #define mhi_driver_register(mhi_drv) \ 57582174738SManivannan Sadhasivam __mhi_driver_register(mhi_drv, THIS_MODULE) 57682174738SManivannan Sadhasivam 57782174738SManivannan Sadhasivam /** 57882174738SManivannan Sadhasivam * __mhi_driver_register - Register driver with MHI framework 57982174738SManivannan Sadhasivam * @mhi_drv: Driver associated with the device 58082174738SManivannan Sadhasivam * @owner: The module owner 58182174738SManivannan Sadhasivam */ 58282174738SManivannan Sadhasivam int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner); 583e755cadbSManivannan Sadhasivam 584e755cadbSManivannan Sadhasivam /** 585e755cadbSManivannan Sadhasivam * mhi_driver_unregister - Unregister a driver for mhi_devices 586e755cadbSManivannan Sadhasivam * @mhi_drv: Driver associated with the device 587e755cadbSManivannan Sadhasivam */ 588e755cadbSManivannan Sadhasivam void mhi_driver_unregister(struct mhi_driver *mhi_drv); 589e755cadbSManivannan Sadhasivam 590a6e2e352SManivannan Sadhasivam /** 591a6e2e352SManivannan Sadhasivam * mhi_set_mhi_state - Set MHI device state 592a6e2e352SManivannan Sadhasivam * @mhi_cntrl: MHI controller 593a6e2e352SManivannan Sadhasivam * @state: State to set 594a6e2e352SManivannan Sadhasivam */ 595a6e2e352SManivannan Sadhasivam void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, 596a6e2e352SManivannan Sadhasivam enum mhi_state state); 597a6e2e352SManivannan Sadhasivam 5983000f85bSManivannan Sadhasivam /** 5990c6b20a1SManivannan Sadhasivam * mhi_notify - Notify the MHI client driver about client device status 6000c6b20a1SManivannan Sadhasivam * @mhi_dev: MHI device instance 6010c6b20a1SManivannan Sadhasivam * @cb_reason: MHI callback reason 6020c6b20a1SManivannan Sadhasivam */ 6030c6b20a1SManivannan Sadhasivam void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason); 6040c6b20a1SManivannan Sadhasivam 6050c6b20a1SManivannan Sadhasivam /** 60687baa23eSHemant Kumar * mhi_get_free_desc_count - Get transfer ring length 60787baa23eSHemant Kumar * Get # of TD available to queue buffers 60887baa23eSHemant Kumar * @mhi_dev: Device associated with the channels 60987baa23eSHemant Kumar * @dir: Direction of the channel 61087baa23eSHemant Kumar */ 61187baa23eSHemant Kumar int mhi_get_free_desc_count(struct mhi_device *mhi_dev, 61287baa23eSHemant Kumar enum dma_data_direction dir); 61387baa23eSHemant Kumar 61487baa23eSHemant Kumar /** 6153000f85bSManivannan Sadhasivam * mhi_prepare_for_power_up - Do pre-initialization before power up. 6163000f85bSManivannan Sadhasivam * This is optional, call this before power up if 6173000f85bSManivannan Sadhasivam * the controller does not want bus framework to 6183000f85bSManivannan Sadhasivam * automatically free any allocated memory during 6193000f85bSManivannan Sadhasivam * shutdown process. 6203000f85bSManivannan Sadhasivam * @mhi_cntrl: MHI controller 6213000f85bSManivannan Sadhasivam */ 6223000f85bSManivannan Sadhasivam int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl); 6233000f85bSManivannan Sadhasivam 6243000f85bSManivannan Sadhasivam /** 6253000f85bSManivannan Sadhasivam * mhi_async_power_up - Start MHI power up sequence 6263000f85bSManivannan Sadhasivam * @mhi_cntrl: MHI controller 6273000f85bSManivannan Sadhasivam */ 6283000f85bSManivannan Sadhasivam int mhi_async_power_up(struct mhi_controller *mhi_cntrl); 6293000f85bSManivannan Sadhasivam 6303000f85bSManivannan Sadhasivam /** 6313000f85bSManivannan Sadhasivam * mhi_sync_power_up - Start MHI power up sequence and wait till the device 6324d12a897SRandy Dunlap * enters valid EE state 6333000f85bSManivannan Sadhasivam * @mhi_cntrl: MHI controller 6343000f85bSManivannan Sadhasivam */ 6353000f85bSManivannan Sadhasivam int mhi_sync_power_up(struct mhi_controller *mhi_cntrl); 6363000f85bSManivannan Sadhasivam 6373000f85bSManivannan Sadhasivam /** 6383000f85bSManivannan Sadhasivam * mhi_power_down - Start MHI power down sequence 6393000f85bSManivannan Sadhasivam * @mhi_cntrl: MHI controller 6403000f85bSManivannan Sadhasivam * @graceful: Link is still accessible, so do a graceful shutdown process 6413000f85bSManivannan Sadhasivam */ 6423000f85bSManivannan Sadhasivam void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful); 6433000f85bSManivannan Sadhasivam 6443000f85bSManivannan Sadhasivam /** 6453000f85bSManivannan Sadhasivam * mhi_unprepare_after_power_down - Free any allocated memory after power down 6463000f85bSManivannan Sadhasivam * @mhi_cntrl: MHI controller 6473000f85bSManivannan Sadhasivam */ 6483000f85bSManivannan Sadhasivam void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl); 6493000f85bSManivannan Sadhasivam 6506fdfdd27SManivannan Sadhasivam /** 6510c6b20a1SManivannan Sadhasivam * mhi_pm_suspend - Move MHI into a suspended state 6520c6b20a1SManivannan Sadhasivam * @mhi_cntrl: MHI controller 6530c6b20a1SManivannan Sadhasivam */ 6540c6b20a1SManivannan Sadhasivam int mhi_pm_suspend(struct mhi_controller *mhi_cntrl); 6550c6b20a1SManivannan Sadhasivam 6560c6b20a1SManivannan Sadhasivam /** 6570c6b20a1SManivannan Sadhasivam * mhi_pm_resume - Resume MHI from suspended state 6580c6b20a1SManivannan Sadhasivam * @mhi_cntrl: MHI controller 6590c6b20a1SManivannan Sadhasivam */ 6600c6b20a1SManivannan Sadhasivam int mhi_pm_resume(struct mhi_controller *mhi_cntrl); 6610c6b20a1SManivannan Sadhasivam 6620c6b20a1SManivannan Sadhasivam /** 6639e1660e5SBhaumik Bhatt * mhi_download_rddm_image - Download ramdump image from device for 6646fdfdd27SManivannan Sadhasivam * debugging purpose. 6656fdfdd27SManivannan Sadhasivam * @mhi_cntrl: MHI controller 6666fdfdd27SManivannan Sadhasivam * @in_panic: Download rddm image during kernel panic 6676fdfdd27SManivannan Sadhasivam */ 6689e1660e5SBhaumik Bhatt int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic); 6696fdfdd27SManivannan Sadhasivam 6706fdfdd27SManivannan Sadhasivam /** 6716fdfdd27SManivannan Sadhasivam * mhi_force_rddm_mode - Force device into rddm mode 6726fdfdd27SManivannan Sadhasivam * @mhi_cntrl: MHI controller 6736fdfdd27SManivannan Sadhasivam */ 6746fdfdd27SManivannan Sadhasivam int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl); 6756fdfdd27SManivannan Sadhasivam 6766fdfdd27SManivannan Sadhasivam /** 67778e1d226SBhaumik Bhatt * mhi_get_exec_env - Get BHI execution environment of the device 67878e1d226SBhaumik Bhatt * @mhi_cntrl: MHI controller 67978e1d226SBhaumik Bhatt */ 68078e1d226SBhaumik Bhatt enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); 68178e1d226SBhaumik Bhatt 68278e1d226SBhaumik Bhatt /** 6836fdfdd27SManivannan Sadhasivam * mhi_get_mhi_state - Get MHI state of the device 6846fdfdd27SManivannan Sadhasivam * @mhi_cntrl: MHI controller 6856fdfdd27SManivannan Sadhasivam */ 6866fdfdd27SManivannan Sadhasivam enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl); 6876fdfdd27SManivannan Sadhasivam 688189ff97cSManivannan Sadhasivam /** 689b5a8d233SLoic Poulain * mhi_soc_reset - Trigger a device reset. This can be used as a last resort 690b5a8d233SLoic Poulain * to reset and recover a device. 691b5a8d233SLoic Poulain * @mhi_cntrl: MHI controller 692b5a8d233SLoic Poulain */ 693b5a8d233SLoic Poulain void mhi_soc_reset(struct mhi_controller *mhi_cntrl); 694b5a8d233SLoic Poulain 695b5a8d233SLoic Poulain /** 696189ff97cSManivannan Sadhasivam * mhi_device_get - Disable device low power mode 697189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channel 698189ff97cSManivannan Sadhasivam */ 699189ff97cSManivannan Sadhasivam void mhi_device_get(struct mhi_device *mhi_dev); 700189ff97cSManivannan Sadhasivam 701189ff97cSManivannan Sadhasivam /** 702189ff97cSManivannan Sadhasivam * mhi_device_get_sync - Disable device low power mode. Synchronously 703189ff97cSManivannan Sadhasivam * take the controller out of suspended state 704189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channel 705189ff97cSManivannan Sadhasivam */ 706189ff97cSManivannan Sadhasivam int mhi_device_get_sync(struct mhi_device *mhi_dev); 707189ff97cSManivannan Sadhasivam 708189ff97cSManivannan Sadhasivam /** 709189ff97cSManivannan Sadhasivam * mhi_device_put - Re-enable device low power mode 710189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channel 711189ff97cSManivannan Sadhasivam */ 712189ff97cSManivannan Sadhasivam void mhi_device_put(struct mhi_device *mhi_dev); 713189ff97cSManivannan Sadhasivam 714189ff97cSManivannan Sadhasivam /** 7156731fefdSBhaumik Bhatt * mhi_prepare_for_transfer - Setup UL and DL channels for data transfer. 7166731fefdSBhaumik Bhatt * Allocate and initialize the channel context and 7176731fefdSBhaumik Bhatt * also issue the START channel command to both 7186731fefdSBhaumik Bhatt * channels. Channels can be started only if both 7196731fefdSBhaumik Bhatt * host and device execution environments match and 7206731fefdSBhaumik Bhatt * channels are in a DISABLED state. 721189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channels 722189ff97cSManivannan Sadhasivam */ 723*9ebc2758SKalle Valo int mhi_prepare_for_transfer(struct mhi_device *mhi_dev); 724189ff97cSManivannan Sadhasivam 725189ff97cSManivannan Sadhasivam /** 7266731fefdSBhaumik Bhatt * mhi_unprepare_from_transfer - Reset UL and DL channels for data transfer. 7276731fefdSBhaumik Bhatt * Issue the RESET channel command and let the 7286731fefdSBhaumik Bhatt * device clean-up the context so no incoming 7296731fefdSBhaumik Bhatt * transfers are seen on the host. Free memory 7306731fefdSBhaumik Bhatt * associated with the context on host. If device 7316731fefdSBhaumik Bhatt * is unresponsive, only perform a host side 7326731fefdSBhaumik Bhatt * clean-up. Channels can be reset only if both 7336731fefdSBhaumik Bhatt * host and device execution environments match 7346731fefdSBhaumik Bhatt * and channels are in an ENABLED, STOPPED or 7356731fefdSBhaumik Bhatt * SUSPENDED state. 736189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channels 737189ff97cSManivannan Sadhasivam */ 738189ff97cSManivannan Sadhasivam void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev); 739189ff97cSManivannan Sadhasivam 740189ff97cSManivannan Sadhasivam /** 741189ff97cSManivannan Sadhasivam * mhi_poll - Poll for any available data in DL direction 742189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channels 743189ff97cSManivannan Sadhasivam * @budget: # of events to process 744189ff97cSManivannan Sadhasivam */ 745189ff97cSManivannan Sadhasivam int mhi_poll(struct mhi_device *mhi_dev, u32 budget); 746189ff97cSManivannan Sadhasivam 747189ff97cSManivannan Sadhasivam /** 748189ff97cSManivannan Sadhasivam * mhi_queue_dma - Send or receive DMA mapped buffers from client device 749189ff97cSManivannan Sadhasivam * over MHI channel 750189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channels 751189ff97cSManivannan Sadhasivam * @dir: DMA direction for the channel 752189ff97cSManivannan Sadhasivam * @mhi_buf: Buffer for holding the DMA mapped data 753189ff97cSManivannan Sadhasivam * @len: Buffer length 754189ff97cSManivannan Sadhasivam * @mflags: MHI transfer flags used for the transfer 755189ff97cSManivannan Sadhasivam */ 756189ff97cSManivannan Sadhasivam int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, 757189ff97cSManivannan Sadhasivam struct mhi_buf *mhi_buf, size_t len, enum mhi_flags mflags); 758189ff97cSManivannan Sadhasivam 759189ff97cSManivannan Sadhasivam /** 760189ff97cSManivannan Sadhasivam * mhi_queue_buf - Send or receive raw buffers from client device over MHI 761189ff97cSManivannan Sadhasivam * channel 762189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channels 763189ff97cSManivannan Sadhasivam * @dir: DMA direction for the channel 764189ff97cSManivannan Sadhasivam * @buf: Buffer for holding the data 765189ff97cSManivannan Sadhasivam * @len: Buffer length 766189ff97cSManivannan Sadhasivam * @mflags: MHI transfer flags used for the transfer 767189ff97cSManivannan Sadhasivam */ 768189ff97cSManivannan Sadhasivam int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, 769189ff97cSManivannan Sadhasivam void *buf, size_t len, enum mhi_flags mflags); 770189ff97cSManivannan Sadhasivam 771189ff97cSManivannan Sadhasivam /** 772189ff97cSManivannan Sadhasivam * mhi_queue_skb - Send or receive SKBs from client device over MHI channel 773189ff97cSManivannan Sadhasivam * @mhi_dev: Device associated with the channels 774189ff97cSManivannan Sadhasivam * @dir: DMA direction for the channel 775189ff97cSManivannan Sadhasivam * @skb: Buffer for holding SKBs 776189ff97cSManivannan Sadhasivam * @len: Buffer length 777189ff97cSManivannan Sadhasivam * @mflags: MHI transfer flags used for the transfer 778189ff97cSManivannan Sadhasivam */ 779189ff97cSManivannan Sadhasivam int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, 780189ff97cSManivannan Sadhasivam struct sk_buff *skb, size_t len, enum mhi_flags mflags); 781189ff97cSManivannan Sadhasivam 782d8c4a223SLoic Poulain /** 783d8c4a223SLoic Poulain * mhi_queue_is_full - Determine whether queueing new elements is possible 784d8c4a223SLoic Poulain * @mhi_dev: Device associated with the channels 785d8c4a223SLoic Poulain * @dir: DMA direction for the channel 786d8c4a223SLoic Poulain */ 787d8c4a223SLoic Poulain bool mhi_queue_is_full(struct mhi_device *mhi_dev, enum dma_data_direction dir); 788d8c4a223SLoic Poulain 7890cbf2608SManivannan Sadhasivam #endif /* _MHI_H_ */ 790