xref: /linux-6.15/include/linux/mhi.h (revision 6fdfdd27)
10cbf2608SManivannan Sadhasivam /* SPDX-License-Identifier: GPL-2.0 */
20cbf2608SManivannan Sadhasivam /*
30cbf2608SManivannan Sadhasivam  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
40cbf2608SManivannan Sadhasivam  *
50cbf2608SManivannan Sadhasivam  */
60cbf2608SManivannan Sadhasivam #ifndef _MHI_H_
70cbf2608SManivannan Sadhasivam #define _MHI_H_
80cbf2608SManivannan Sadhasivam 
90cbf2608SManivannan Sadhasivam #include <linux/device.h>
100cbf2608SManivannan Sadhasivam #include <linux/dma-direction.h>
110cbf2608SManivannan Sadhasivam #include <linux/mutex.h>
120cbf2608SManivannan Sadhasivam #include <linux/rwlock_types.h>
130cbf2608SManivannan Sadhasivam #include <linux/slab.h>
140cbf2608SManivannan Sadhasivam #include <linux/spinlock_types.h>
150cbf2608SManivannan Sadhasivam #include <linux/wait.h>
160cbf2608SManivannan Sadhasivam #include <linux/workqueue.h>
170cbf2608SManivannan Sadhasivam 
180cbf2608SManivannan Sadhasivam struct mhi_chan;
190cbf2608SManivannan Sadhasivam struct mhi_event;
200cbf2608SManivannan Sadhasivam struct mhi_ctxt;
210cbf2608SManivannan Sadhasivam struct mhi_cmd;
220cbf2608SManivannan Sadhasivam struct mhi_buf_info;
230cbf2608SManivannan Sadhasivam 
240cbf2608SManivannan Sadhasivam /**
250cbf2608SManivannan Sadhasivam  * enum mhi_callback - MHI callback
260cbf2608SManivannan Sadhasivam  * @MHI_CB_IDLE: MHI entered idle state
270cbf2608SManivannan Sadhasivam  * @MHI_CB_PENDING_DATA: New data available for client to process
280cbf2608SManivannan Sadhasivam  * @MHI_CB_LPM_ENTER: MHI host entered low power mode
290cbf2608SManivannan Sadhasivam  * @MHI_CB_LPM_EXIT: MHI host about to exit low power mode
300cbf2608SManivannan Sadhasivam  * @MHI_CB_EE_RDDM: MHI device entered RDDM exec env
310cbf2608SManivannan Sadhasivam  * @MHI_CB_EE_MISSION_MODE: MHI device entered Mission Mode exec env
320cbf2608SManivannan Sadhasivam  * @MHI_CB_SYS_ERROR: MHI device entered error state (may recover)
330cbf2608SManivannan Sadhasivam  * @MHI_CB_FATAL_ERROR: MHI device entered fatal error state
340cbf2608SManivannan Sadhasivam  */
350cbf2608SManivannan Sadhasivam enum mhi_callback {
360cbf2608SManivannan Sadhasivam 	MHI_CB_IDLE,
370cbf2608SManivannan Sadhasivam 	MHI_CB_PENDING_DATA,
380cbf2608SManivannan Sadhasivam 	MHI_CB_LPM_ENTER,
390cbf2608SManivannan Sadhasivam 	MHI_CB_LPM_EXIT,
400cbf2608SManivannan Sadhasivam 	MHI_CB_EE_RDDM,
410cbf2608SManivannan Sadhasivam 	MHI_CB_EE_MISSION_MODE,
420cbf2608SManivannan Sadhasivam 	MHI_CB_SYS_ERROR,
430cbf2608SManivannan Sadhasivam 	MHI_CB_FATAL_ERROR,
440cbf2608SManivannan Sadhasivam };
450cbf2608SManivannan Sadhasivam 
460cbf2608SManivannan Sadhasivam /**
470cbf2608SManivannan Sadhasivam  * enum mhi_flags - Transfer flags
480cbf2608SManivannan Sadhasivam  * @MHI_EOB: End of buffer for bulk transfer
490cbf2608SManivannan Sadhasivam  * @MHI_EOT: End of transfer
500cbf2608SManivannan Sadhasivam  * @MHI_CHAIN: Linked transfer
510cbf2608SManivannan Sadhasivam  */
520cbf2608SManivannan Sadhasivam enum mhi_flags {
530cbf2608SManivannan Sadhasivam 	MHI_EOB,
540cbf2608SManivannan Sadhasivam 	MHI_EOT,
550cbf2608SManivannan Sadhasivam 	MHI_CHAIN,
560cbf2608SManivannan Sadhasivam };
570cbf2608SManivannan Sadhasivam 
580cbf2608SManivannan Sadhasivam /**
590cbf2608SManivannan Sadhasivam  * enum mhi_device_type - Device types
600cbf2608SManivannan Sadhasivam  * @MHI_DEVICE_XFER: Handles data transfer
610cbf2608SManivannan Sadhasivam  * @MHI_DEVICE_CONTROLLER: Control device
620cbf2608SManivannan Sadhasivam  */
630cbf2608SManivannan Sadhasivam enum mhi_device_type {
640cbf2608SManivannan Sadhasivam 	MHI_DEVICE_XFER,
650cbf2608SManivannan Sadhasivam 	MHI_DEVICE_CONTROLLER,
660cbf2608SManivannan Sadhasivam };
670cbf2608SManivannan Sadhasivam 
680cbf2608SManivannan Sadhasivam /**
690cbf2608SManivannan Sadhasivam  * enum mhi_ch_type - Channel types
700cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_INVALID: Invalid channel type
710cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_OUTBOUND: Outbound channel to the device
720cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_INBOUND: Inbound channel from the device
730cbf2608SManivannan Sadhasivam  * @MHI_CH_TYPE_INBOUND_COALESCED: Coalesced channel for the device to combine
740cbf2608SManivannan Sadhasivam  *				   multiple packets and send them as a single
750cbf2608SManivannan Sadhasivam  *				   large packet to reduce CPU consumption
760cbf2608SManivannan Sadhasivam  */
770cbf2608SManivannan Sadhasivam enum mhi_ch_type {
780cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_INVALID = 0,
790cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_OUTBOUND = DMA_TO_DEVICE,
800cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_INBOUND = DMA_FROM_DEVICE,
810cbf2608SManivannan Sadhasivam 	MHI_CH_TYPE_INBOUND_COALESCED = 3,
820cbf2608SManivannan Sadhasivam };
830cbf2608SManivannan Sadhasivam 
840cbf2608SManivannan Sadhasivam /**
853000f85bSManivannan Sadhasivam  * struct image_info - Firmware and RDDM table table
863000f85bSManivannan Sadhasivam  * @mhi_buf - Buffer for firmware and RDDM table
873000f85bSManivannan Sadhasivam  * @entries - # of entries in table
883000f85bSManivannan Sadhasivam  */
893000f85bSManivannan Sadhasivam struct image_info {
903000f85bSManivannan Sadhasivam 	struct mhi_buf *mhi_buf;
913000f85bSManivannan Sadhasivam 	struct bhi_vec_entry *bhi_vec;
923000f85bSManivannan Sadhasivam 	u32 entries;
933000f85bSManivannan Sadhasivam };
943000f85bSManivannan Sadhasivam 
953000f85bSManivannan Sadhasivam /**
960cbf2608SManivannan Sadhasivam  * enum mhi_ee_type - Execution environment types
970cbf2608SManivannan Sadhasivam  * @MHI_EE_PBL: Primary Bootloader
980cbf2608SManivannan Sadhasivam  * @MHI_EE_SBL: Secondary Bootloader
990cbf2608SManivannan Sadhasivam  * @MHI_EE_AMSS: Modem, aka the primary runtime EE
1000cbf2608SManivannan Sadhasivam  * @MHI_EE_RDDM: Ram dump download mode
1010cbf2608SManivannan Sadhasivam  * @MHI_EE_WFW: WLAN firmware mode
1020cbf2608SManivannan Sadhasivam  * @MHI_EE_PTHRU: Passthrough
1030cbf2608SManivannan Sadhasivam  * @MHI_EE_EDL: Embedded downloader
1040cbf2608SManivannan Sadhasivam  */
1050cbf2608SManivannan Sadhasivam enum mhi_ee_type {
1060cbf2608SManivannan Sadhasivam 	MHI_EE_PBL,
1070cbf2608SManivannan Sadhasivam 	MHI_EE_SBL,
1080cbf2608SManivannan Sadhasivam 	MHI_EE_AMSS,
1090cbf2608SManivannan Sadhasivam 	MHI_EE_RDDM,
1100cbf2608SManivannan Sadhasivam 	MHI_EE_WFW,
1110cbf2608SManivannan Sadhasivam 	MHI_EE_PTHRU,
1120cbf2608SManivannan Sadhasivam 	MHI_EE_EDL,
1130cbf2608SManivannan Sadhasivam 	MHI_EE_MAX_SUPPORTED = MHI_EE_EDL,
1140cbf2608SManivannan Sadhasivam 	MHI_EE_DISABLE_TRANSITION, /* local EE, not related to mhi spec */
1150cbf2608SManivannan Sadhasivam 	MHI_EE_NOT_SUPPORTED,
1160cbf2608SManivannan Sadhasivam 	MHI_EE_MAX,
1170cbf2608SManivannan Sadhasivam };
1180cbf2608SManivannan Sadhasivam 
1190cbf2608SManivannan Sadhasivam /**
120a6e2e352SManivannan Sadhasivam  * enum mhi_state - MHI states
121a6e2e352SManivannan Sadhasivam  * @MHI_STATE_RESET: Reset state
122a6e2e352SManivannan Sadhasivam  * @MHI_STATE_READY: Ready state
123a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M0: M0 state
124a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M1: M1 state
125a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M2: M2 state
126a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M3: M3 state
127a6e2e352SManivannan Sadhasivam  * @MHI_STATE_M3_FAST: M3 Fast state
128a6e2e352SManivannan Sadhasivam  * @MHI_STATE_BHI: BHI state
129a6e2e352SManivannan Sadhasivam  * @MHI_STATE_SYS_ERR: System Error state
130a6e2e352SManivannan Sadhasivam  */
131a6e2e352SManivannan Sadhasivam enum mhi_state {
132a6e2e352SManivannan Sadhasivam 	MHI_STATE_RESET = 0x0,
133a6e2e352SManivannan Sadhasivam 	MHI_STATE_READY = 0x1,
134a6e2e352SManivannan Sadhasivam 	MHI_STATE_M0 = 0x2,
135a6e2e352SManivannan Sadhasivam 	MHI_STATE_M1 = 0x3,
136a6e2e352SManivannan Sadhasivam 	MHI_STATE_M2 = 0x4,
137a6e2e352SManivannan Sadhasivam 	MHI_STATE_M3 = 0x5,
138a6e2e352SManivannan Sadhasivam 	MHI_STATE_M3_FAST = 0x6,
139a6e2e352SManivannan Sadhasivam 	MHI_STATE_BHI = 0x7,
140a6e2e352SManivannan Sadhasivam 	MHI_STATE_SYS_ERR = 0xFF,
141a6e2e352SManivannan Sadhasivam 	MHI_STATE_MAX,
142a6e2e352SManivannan Sadhasivam };
143a6e2e352SManivannan Sadhasivam 
144a6e2e352SManivannan Sadhasivam /**
1450cbf2608SManivannan Sadhasivam  * enum mhi_ch_ee_mask - Execution environment mask for channel
1460cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_PBL: Allow channel to be used in PBL EE
1470cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_SBL: Allow channel to be used in SBL EE
1480cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_AMSS: Allow channel to be used in AMSS EE
1490cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_RDDM: Allow channel to be used in RDDM EE
1500cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_PTHRU: Allow channel to be used in PTHRU EE
1510cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_WFW: Allow channel to be used in WFW EE
1520cbf2608SManivannan Sadhasivam  * @MHI_CH_EE_EDL: Allow channel to be used in EDL EE
1530cbf2608SManivannan Sadhasivam  */
1540cbf2608SManivannan Sadhasivam enum mhi_ch_ee_mask {
1550cbf2608SManivannan Sadhasivam 	MHI_CH_EE_PBL = BIT(MHI_EE_PBL),
1560cbf2608SManivannan Sadhasivam 	MHI_CH_EE_SBL = BIT(MHI_EE_SBL),
1570cbf2608SManivannan Sadhasivam 	MHI_CH_EE_AMSS = BIT(MHI_EE_AMSS),
1580cbf2608SManivannan Sadhasivam 	MHI_CH_EE_RDDM = BIT(MHI_EE_RDDM),
1590cbf2608SManivannan Sadhasivam 	MHI_CH_EE_PTHRU = BIT(MHI_EE_PTHRU),
1600cbf2608SManivannan Sadhasivam 	MHI_CH_EE_WFW = BIT(MHI_EE_WFW),
1610cbf2608SManivannan Sadhasivam 	MHI_CH_EE_EDL = BIT(MHI_EE_EDL),
1620cbf2608SManivannan Sadhasivam };
1630cbf2608SManivannan Sadhasivam 
1640cbf2608SManivannan Sadhasivam /**
1650cbf2608SManivannan Sadhasivam  * enum mhi_er_data_type - Event ring data types
1660cbf2608SManivannan Sadhasivam  * @MHI_ER_DATA: Only client data over this ring
1670cbf2608SManivannan Sadhasivam  * @MHI_ER_CTRL: MHI control data and client data
1680cbf2608SManivannan Sadhasivam  */
1690cbf2608SManivannan Sadhasivam enum mhi_er_data_type {
1700cbf2608SManivannan Sadhasivam 	MHI_ER_DATA,
1710cbf2608SManivannan Sadhasivam 	MHI_ER_CTRL,
1720cbf2608SManivannan Sadhasivam };
1730cbf2608SManivannan Sadhasivam 
1740cbf2608SManivannan Sadhasivam /**
1750cbf2608SManivannan Sadhasivam  * enum mhi_db_brst_mode - Doorbell mode
1760cbf2608SManivannan Sadhasivam  * @MHI_DB_BRST_DISABLE: Burst mode disable
1770cbf2608SManivannan Sadhasivam  * @MHI_DB_BRST_ENABLE: Burst mode enable
1780cbf2608SManivannan Sadhasivam  */
1790cbf2608SManivannan Sadhasivam enum mhi_db_brst_mode {
1800cbf2608SManivannan Sadhasivam 	MHI_DB_BRST_DISABLE = 0x2,
1810cbf2608SManivannan Sadhasivam 	MHI_DB_BRST_ENABLE = 0x3,
1820cbf2608SManivannan Sadhasivam };
1830cbf2608SManivannan Sadhasivam 
1840cbf2608SManivannan Sadhasivam /**
1850cbf2608SManivannan Sadhasivam  * struct mhi_channel_config - Channel configuration structure for controller
1860cbf2608SManivannan Sadhasivam  * @name: The name of this channel
1870cbf2608SManivannan Sadhasivam  * @num: The number assigned to this channel
1880cbf2608SManivannan Sadhasivam  * @num_elements: The number of elements that can be queued to this channel
1890cbf2608SManivannan Sadhasivam  * @local_elements: The local ring length of the channel
1900cbf2608SManivannan Sadhasivam  * @event_ring: The event rung index that services this channel
1910cbf2608SManivannan Sadhasivam  * @dir: Direction that data may flow on this channel
1920cbf2608SManivannan Sadhasivam  * @type: Channel type
1930cbf2608SManivannan Sadhasivam  * @ee_mask: Execution Environment mask for this channel
1940cbf2608SManivannan Sadhasivam  * @pollcfg: Polling configuration for burst mode.  0 is default.  milliseconds
1950cbf2608SManivannan Sadhasivam 	     for UL channels, multiple of 8 ring elements for DL channels
1960cbf2608SManivannan Sadhasivam  * @doorbell: Doorbell mode
1970cbf2608SManivannan Sadhasivam  * @lpm_notify: The channel master requires low power mode notifications
1980cbf2608SManivannan Sadhasivam  * @offload_channel: The client manages the channel completely
1990cbf2608SManivannan Sadhasivam  * @doorbell_mode_switch: Channel switches to doorbell mode on M0 transition
2000cbf2608SManivannan Sadhasivam  * @auto_queue: Framework will automatically queue buffers for DL traffic
2010cbf2608SManivannan Sadhasivam  * @auto_start: Automatically start (open) this channel
202da1c4f85SManivannan Sadhasivam  * @wake-capable: Channel capable of waking up the system
2030cbf2608SManivannan Sadhasivam  */
2040cbf2608SManivannan Sadhasivam struct mhi_channel_config {
2050cbf2608SManivannan Sadhasivam 	char *name;
2060cbf2608SManivannan Sadhasivam 	u32 num;
2070cbf2608SManivannan Sadhasivam 	u32 num_elements;
2080cbf2608SManivannan Sadhasivam 	u32 local_elements;
2090cbf2608SManivannan Sadhasivam 	u32 event_ring;
2100cbf2608SManivannan Sadhasivam 	enum dma_data_direction dir;
2110cbf2608SManivannan Sadhasivam 	enum mhi_ch_type type;
2120cbf2608SManivannan Sadhasivam 	u32 ee_mask;
2130cbf2608SManivannan Sadhasivam 	u32 pollcfg;
2140cbf2608SManivannan Sadhasivam 	enum mhi_db_brst_mode doorbell;
2150cbf2608SManivannan Sadhasivam 	bool lpm_notify;
2160cbf2608SManivannan Sadhasivam 	bool offload_channel;
2170cbf2608SManivannan Sadhasivam 	bool doorbell_mode_switch;
2180cbf2608SManivannan Sadhasivam 	bool auto_queue;
2190cbf2608SManivannan Sadhasivam 	bool auto_start;
220da1c4f85SManivannan Sadhasivam 	bool wake_capable;
2210cbf2608SManivannan Sadhasivam };
2220cbf2608SManivannan Sadhasivam 
2230cbf2608SManivannan Sadhasivam /**
2240cbf2608SManivannan Sadhasivam  * struct mhi_event_config - Event ring configuration structure for controller
2250cbf2608SManivannan Sadhasivam  * @num_elements: The number of elements that can be queued to this ring
2260cbf2608SManivannan Sadhasivam  * @irq_moderation_ms: Delay irq for additional events to be aggregated
2270cbf2608SManivannan Sadhasivam  * @irq: IRQ associated with this ring
2280cbf2608SManivannan Sadhasivam  * @channel: Dedicated channel number. U32_MAX indicates a non-dedicated ring
2290cbf2608SManivannan Sadhasivam  * @priority: Priority of this ring. Use 1 for now
2300cbf2608SManivannan Sadhasivam  * @mode: Doorbell mode
2310cbf2608SManivannan Sadhasivam  * @data_type: Type of data this ring will process
2320cbf2608SManivannan Sadhasivam  * @hardware_event: This ring is associated with hardware channels
2330cbf2608SManivannan Sadhasivam  * @client_managed: This ring is client managed
2340cbf2608SManivannan Sadhasivam  * @offload_channel: This ring is associated with an offloaded channel
2350cbf2608SManivannan Sadhasivam  */
2360cbf2608SManivannan Sadhasivam struct mhi_event_config {
2370cbf2608SManivannan Sadhasivam 	u32 num_elements;
2380cbf2608SManivannan Sadhasivam 	u32 irq_moderation_ms;
2390cbf2608SManivannan Sadhasivam 	u32 irq;
2400cbf2608SManivannan Sadhasivam 	u32 channel;
2410cbf2608SManivannan Sadhasivam 	u32 priority;
2420cbf2608SManivannan Sadhasivam 	enum mhi_db_brst_mode mode;
2430cbf2608SManivannan Sadhasivam 	enum mhi_er_data_type data_type;
2440cbf2608SManivannan Sadhasivam 	bool hardware_event;
2450cbf2608SManivannan Sadhasivam 	bool client_managed;
2460cbf2608SManivannan Sadhasivam 	bool offload_channel;
2470cbf2608SManivannan Sadhasivam };
2480cbf2608SManivannan Sadhasivam 
2490cbf2608SManivannan Sadhasivam /**
2500cbf2608SManivannan Sadhasivam  * struct mhi_controller_config - Root MHI controller configuration
2510cbf2608SManivannan Sadhasivam  * @max_channels: Maximum number of channels supported
2520cbf2608SManivannan Sadhasivam  * @timeout_ms: Timeout value for operations. 0 means use default
2530cbf2608SManivannan Sadhasivam  * @buf_len: Size of automatically allocated buffers. 0 means use default
2540cbf2608SManivannan Sadhasivam  * @num_channels: Number of channels defined in @ch_cfg
2550cbf2608SManivannan Sadhasivam  * @ch_cfg: Array of defined channels
2560cbf2608SManivannan Sadhasivam  * @num_events: Number of event rings defined in @event_cfg
2570cbf2608SManivannan Sadhasivam  * @event_cfg: Array of defined event rings
2580cbf2608SManivannan Sadhasivam  * @use_bounce_buf: Use a bounce buffer pool due to limited DDR access
2590cbf2608SManivannan Sadhasivam  * @m2_no_db: Host is not allowed to ring DB in M2 state
2600cbf2608SManivannan Sadhasivam  */
2610cbf2608SManivannan Sadhasivam struct mhi_controller_config {
2620cbf2608SManivannan Sadhasivam 	u32 max_channels;
2630cbf2608SManivannan Sadhasivam 	u32 timeout_ms;
2640cbf2608SManivannan Sadhasivam 	u32 buf_len;
2650cbf2608SManivannan Sadhasivam 	u32 num_channels;
2660cbf2608SManivannan Sadhasivam 	struct mhi_channel_config *ch_cfg;
2670cbf2608SManivannan Sadhasivam 	u32 num_events;
2680cbf2608SManivannan Sadhasivam 	struct mhi_event_config *event_cfg;
2690cbf2608SManivannan Sadhasivam 	bool use_bounce_buf;
2700cbf2608SManivannan Sadhasivam 	bool m2_no_db;
2710cbf2608SManivannan Sadhasivam };
2720cbf2608SManivannan Sadhasivam 
2730cbf2608SManivannan Sadhasivam /**
2740cbf2608SManivannan Sadhasivam  * struct mhi_controller - Master MHI controller structure
2750cbf2608SManivannan Sadhasivam  * @cntrl_dev: Pointer to the struct device of physical bus acting as the MHI
2760cbf2608SManivannan Sadhasivam  *            controller (required)
2770cbf2608SManivannan Sadhasivam  * @mhi_dev: MHI device instance for the controller
2780cbf2608SManivannan Sadhasivam  * @regs: Base address of MHI MMIO register space (required)
2796cd330aeSManivannan Sadhasivam  * @bhi: Points to base of MHI BHI register space
2803000f85bSManivannan Sadhasivam  * @bhie: Points to base of MHI BHIe register space
2816cd330aeSManivannan Sadhasivam  * @wake_db: MHI WAKE doorbell register address
2820cbf2608SManivannan Sadhasivam  * @iova_start: IOMMU starting address for data (required)
2830cbf2608SManivannan Sadhasivam  * @iova_stop: IOMMU stop address for data (required)
2840cbf2608SManivannan Sadhasivam  * @fw_image: Firmware image name for normal booting (required)
2850cbf2608SManivannan Sadhasivam  * @edl_image: Firmware image name for emergency download mode (optional)
286*6fdfdd27SManivannan Sadhasivam  * @rddm_size: RAM dump size that host should allocate for debugging purpose
2870cbf2608SManivannan Sadhasivam  * @sbl_size: SBL image size downloaded through BHIe (optional)
2880cbf2608SManivannan Sadhasivam  * @seg_len: BHIe vector size (optional)
2893000f85bSManivannan Sadhasivam  * @fbc_image: Points to firmware image buffer
290*6fdfdd27SManivannan Sadhasivam  * @rddm_image: Points to RAM dump buffer
2910cbf2608SManivannan Sadhasivam  * @mhi_chan: Points to the channel configuration table
2920cbf2608SManivannan Sadhasivam  * @lpm_chans: List of channels that require LPM notifications
2930cbf2608SManivannan Sadhasivam  * @irq: base irq # to request (required)
2940cbf2608SManivannan Sadhasivam  * @max_chan: Maximum number of channels the controller supports
2950cbf2608SManivannan Sadhasivam  * @total_ev_rings: Total # of event rings allocated
2960cbf2608SManivannan Sadhasivam  * @hw_ev_rings: Number of hardware event rings
2970cbf2608SManivannan Sadhasivam  * @sw_ev_rings: Number of software event rings
2980cbf2608SManivannan Sadhasivam  * @nr_irqs_req: Number of IRQs required to operate (optional)
2990cbf2608SManivannan Sadhasivam  * @nr_irqs: Number of IRQ allocated by bus master (required)
3000cbf2608SManivannan Sadhasivam  * @mhi_event: MHI event ring configurations table
3010cbf2608SManivannan Sadhasivam  * @mhi_cmd: MHI command ring configurations table
3020cbf2608SManivannan Sadhasivam  * @mhi_ctxt: MHI device context, shared memory between host and device
3030cbf2608SManivannan Sadhasivam  * @pm_mutex: Mutex for suspend/resume operation
3040cbf2608SManivannan Sadhasivam  * @pm_lock: Lock for protecting MHI power management state
3050cbf2608SManivannan Sadhasivam  * @timeout_ms: Timeout in ms for state transitions
3060cbf2608SManivannan Sadhasivam  * @pm_state: MHI power management state
3070cbf2608SManivannan Sadhasivam  * @db_access: DB access states
3080cbf2608SManivannan Sadhasivam  * @ee: MHI device execution environment
309a6e2e352SManivannan Sadhasivam  * @dev_state: MHI device state
3100cbf2608SManivannan Sadhasivam  * @dev_wake: Device wakeup count
3110cbf2608SManivannan Sadhasivam  * @pending_pkts: Pending packets for the controller
3120cbf2608SManivannan Sadhasivam  * @transition_list: List of MHI state transitions
3130cbf2608SManivannan Sadhasivam  * @transition_lock: Lock for protecting MHI state transition list
3140cbf2608SManivannan Sadhasivam  * @wlock: Lock for protecting device wakeup
3150cbf2608SManivannan Sadhasivam  * @st_worker: State transition worker
3160cbf2608SManivannan Sadhasivam  * @fw_worker: Firmware download worker
3170cbf2608SManivannan Sadhasivam  * @syserr_worker: System error worker
3180cbf2608SManivannan Sadhasivam  * @state_event: State change event
3190cbf2608SManivannan Sadhasivam  * @status_cb: CB function to notify power states of the device (required)
3200cbf2608SManivannan Sadhasivam  * @link_status: CB function to query link status of the device (required)
3210cbf2608SManivannan Sadhasivam  * @wake_get: CB function to assert device wake (optional)
3220cbf2608SManivannan Sadhasivam  * @wake_put: CB function to de-assert device wake (optional)
3230cbf2608SManivannan Sadhasivam  * @wake_toggle: CB function to assert and de-assert device wake (optional)
3240cbf2608SManivannan Sadhasivam  * @runtime_get: CB function to controller runtime resume (required)
3250cbf2608SManivannan Sadhasivam  * @runtimet_put: CB function to decrement pm usage (required)
3260cbf2608SManivannan Sadhasivam  * @buffer_len: Bounce buffer length
3270cbf2608SManivannan Sadhasivam  * @bounce_buf: Use of bounce buffer
3280cbf2608SManivannan Sadhasivam  * @fbc_download: MHI host needs to do complete image transfer (optional)
3290cbf2608SManivannan Sadhasivam  * @pre_init: MHI host needs to do pre-initialization before power up
3300cbf2608SManivannan Sadhasivam  * @wake_set: Device wakeup set flag
3310cbf2608SManivannan Sadhasivam  *
3320cbf2608SManivannan Sadhasivam  * Fields marked as (required) need to be populated by the controller driver
3330cbf2608SManivannan Sadhasivam  * before calling mhi_register_controller(). For the fields marked as (optional)
3340cbf2608SManivannan Sadhasivam  * they can be populated depending on the usecase.
3350cbf2608SManivannan Sadhasivam  */
3360cbf2608SManivannan Sadhasivam struct mhi_controller {
3370cbf2608SManivannan Sadhasivam 	struct device *cntrl_dev;
3380cbf2608SManivannan Sadhasivam 	struct mhi_device *mhi_dev;
3390cbf2608SManivannan Sadhasivam 	void __iomem *regs;
3406cd330aeSManivannan Sadhasivam 	void __iomem *bhi;
3413000f85bSManivannan Sadhasivam 	void __iomem *bhie;
3426cd330aeSManivannan Sadhasivam 	void __iomem *wake_db;
343a6e2e352SManivannan Sadhasivam 
3440cbf2608SManivannan Sadhasivam 	dma_addr_t iova_start;
3450cbf2608SManivannan Sadhasivam 	dma_addr_t iova_stop;
3460cbf2608SManivannan Sadhasivam 	const char *fw_image;
3470cbf2608SManivannan Sadhasivam 	const char *edl_image;
348*6fdfdd27SManivannan Sadhasivam 	size_t rddm_size;
3490cbf2608SManivannan Sadhasivam 	size_t sbl_size;
3500cbf2608SManivannan Sadhasivam 	size_t seg_len;
3513000f85bSManivannan Sadhasivam 	struct image_info *fbc_image;
352*6fdfdd27SManivannan Sadhasivam 	struct image_info *rddm_image;
3530cbf2608SManivannan Sadhasivam 	struct mhi_chan *mhi_chan;
3540cbf2608SManivannan Sadhasivam 	struct list_head lpm_chans;
3550cbf2608SManivannan Sadhasivam 	int *irq;
3560cbf2608SManivannan Sadhasivam 	u32 max_chan;
3570cbf2608SManivannan Sadhasivam 	u32 total_ev_rings;
3580cbf2608SManivannan Sadhasivam 	u32 hw_ev_rings;
3590cbf2608SManivannan Sadhasivam 	u32 sw_ev_rings;
3600cbf2608SManivannan Sadhasivam 	u32 nr_irqs_req;
3610cbf2608SManivannan Sadhasivam 	u32 nr_irqs;
3620cbf2608SManivannan Sadhasivam 
3630cbf2608SManivannan Sadhasivam 	struct mhi_event *mhi_event;
3640cbf2608SManivannan Sadhasivam 	struct mhi_cmd *mhi_cmd;
3650cbf2608SManivannan Sadhasivam 	struct mhi_ctxt *mhi_ctxt;
3660cbf2608SManivannan Sadhasivam 
3670cbf2608SManivannan Sadhasivam 	struct mutex pm_mutex;
3680cbf2608SManivannan Sadhasivam 	rwlock_t pm_lock;
3690cbf2608SManivannan Sadhasivam 	u32 timeout_ms;
3700cbf2608SManivannan Sadhasivam 	u32 pm_state;
3710cbf2608SManivannan Sadhasivam 	u32 db_access;
3720cbf2608SManivannan Sadhasivam 	enum mhi_ee_type ee;
373a6e2e352SManivannan Sadhasivam 	enum mhi_state dev_state;
3740cbf2608SManivannan Sadhasivam 	atomic_t dev_wake;
3750cbf2608SManivannan Sadhasivam 	atomic_t pending_pkts;
3760cbf2608SManivannan Sadhasivam 	struct list_head transition_list;
3770cbf2608SManivannan Sadhasivam 	spinlock_t transition_lock;
3780cbf2608SManivannan Sadhasivam 	spinlock_t wlock;
3790cbf2608SManivannan Sadhasivam 	struct work_struct st_worker;
3800cbf2608SManivannan Sadhasivam 	struct work_struct fw_worker;
3810cbf2608SManivannan Sadhasivam 	struct work_struct syserr_worker;
3820cbf2608SManivannan Sadhasivam 	wait_queue_head_t state_event;
3830cbf2608SManivannan Sadhasivam 
3840cbf2608SManivannan Sadhasivam 	void (*status_cb)(struct mhi_controller *mhi_cntrl,
3850cbf2608SManivannan Sadhasivam 			  enum mhi_callback cb);
3860cbf2608SManivannan Sadhasivam 	int (*link_status)(struct mhi_controller *mhi_cntrl);
3870cbf2608SManivannan Sadhasivam 	void (*wake_get)(struct mhi_controller *mhi_cntrl, bool override);
3880cbf2608SManivannan Sadhasivam 	void (*wake_put)(struct mhi_controller *mhi_cntrl, bool override);
3890cbf2608SManivannan Sadhasivam 	void (*wake_toggle)(struct mhi_controller *mhi_cntrl);
3900cbf2608SManivannan Sadhasivam 	int (*runtime_get)(struct mhi_controller *mhi_cntrl);
3910cbf2608SManivannan Sadhasivam 	void (*runtime_put)(struct mhi_controller *mhi_cntrl);
3920cbf2608SManivannan Sadhasivam 
3930cbf2608SManivannan Sadhasivam 	size_t buffer_len;
3940cbf2608SManivannan Sadhasivam 	bool bounce_buf;
3950cbf2608SManivannan Sadhasivam 	bool fbc_download;
3960cbf2608SManivannan Sadhasivam 	bool pre_init;
3970cbf2608SManivannan Sadhasivam 	bool wake_set;
3980cbf2608SManivannan Sadhasivam };
3990cbf2608SManivannan Sadhasivam 
4000cbf2608SManivannan Sadhasivam /**
4010cbf2608SManivannan Sadhasivam  * struct mhi_device - Structure representing a MHI device which binds
4020cbf2608SManivannan Sadhasivam  *                     to channels
4030cbf2608SManivannan Sadhasivam  * @id: Pointer to MHI device ID struct
4040cbf2608SManivannan Sadhasivam  * @chan_name: Name of the channel to which the device binds
4050cbf2608SManivannan Sadhasivam  * @mhi_cntrl: Controller the device belongs to
4060cbf2608SManivannan Sadhasivam  * @ul_chan: UL channel for the device
4070cbf2608SManivannan Sadhasivam  * @dl_chan: DL channel for the device
4080cbf2608SManivannan Sadhasivam  * @dev: Driver model device node for the MHI device
4090cbf2608SManivannan Sadhasivam  * @dev_type: MHI device type
410e755cadbSManivannan Sadhasivam  * @ul_chan_id: MHI channel id for UL transfer
411e755cadbSManivannan Sadhasivam  * @dl_chan_id: MHI channel id for DL transfer
4120cbf2608SManivannan Sadhasivam  * @dev_wake: Device wakeup counter
4130cbf2608SManivannan Sadhasivam  */
4140cbf2608SManivannan Sadhasivam struct mhi_device {
4150cbf2608SManivannan Sadhasivam 	const struct mhi_device_id *id;
4160cbf2608SManivannan Sadhasivam 	const char *chan_name;
4170cbf2608SManivannan Sadhasivam 	struct mhi_controller *mhi_cntrl;
4180cbf2608SManivannan Sadhasivam 	struct mhi_chan *ul_chan;
4190cbf2608SManivannan Sadhasivam 	struct mhi_chan *dl_chan;
4200cbf2608SManivannan Sadhasivam 	struct device dev;
4210cbf2608SManivannan Sadhasivam 	enum mhi_device_type dev_type;
422e755cadbSManivannan Sadhasivam 	int ul_chan_id;
423e755cadbSManivannan Sadhasivam 	int dl_chan_id;
4240cbf2608SManivannan Sadhasivam 	u32 dev_wake;
4250cbf2608SManivannan Sadhasivam };
4260cbf2608SManivannan Sadhasivam 
4270cbf2608SManivannan Sadhasivam /**
4280cbf2608SManivannan Sadhasivam  * struct mhi_result - Completed buffer information
4290cbf2608SManivannan Sadhasivam  * @buf_addr: Address of data buffer
4300cbf2608SManivannan Sadhasivam  * @bytes_xferd: # of bytes transferred
4310cbf2608SManivannan Sadhasivam  * @dir: Channel direction
4320cbf2608SManivannan Sadhasivam  * @transaction_status: Status of last transaction
4330cbf2608SManivannan Sadhasivam  */
4340cbf2608SManivannan Sadhasivam struct mhi_result {
4350cbf2608SManivannan Sadhasivam 	void *buf_addr;
4360cbf2608SManivannan Sadhasivam 	size_t bytes_xferd;
4370cbf2608SManivannan Sadhasivam 	enum dma_data_direction dir;
4380cbf2608SManivannan Sadhasivam 	int transaction_status;
4390cbf2608SManivannan Sadhasivam };
4400cbf2608SManivannan Sadhasivam 
441e755cadbSManivannan Sadhasivam /**
442a6e2e352SManivannan Sadhasivam  * struct mhi_buf - MHI Buffer description
443a6e2e352SManivannan Sadhasivam  * @buf: Virtual address of the buffer
444a6e2e352SManivannan Sadhasivam  * @name: Buffer label. For offload channel, configurations name must be:
445a6e2e352SManivannan Sadhasivam  *        ECA - Event context array data
446a6e2e352SManivannan Sadhasivam  *        CCA - Channel context array data
447a6e2e352SManivannan Sadhasivam  * @dma_addr: IOMMU address of the buffer
448a6e2e352SManivannan Sadhasivam  * @len: # of bytes
449a6e2e352SManivannan Sadhasivam  */
450a6e2e352SManivannan Sadhasivam struct mhi_buf {
451a6e2e352SManivannan Sadhasivam 	void *buf;
452a6e2e352SManivannan Sadhasivam 	const char *name;
453a6e2e352SManivannan Sadhasivam 	dma_addr_t dma_addr;
454a6e2e352SManivannan Sadhasivam 	size_t len;
455a6e2e352SManivannan Sadhasivam };
456a6e2e352SManivannan Sadhasivam 
457a6e2e352SManivannan Sadhasivam /**
458e755cadbSManivannan Sadhasivam  * struct mhi_driver - Structure representing a MHI client driver
459e755cadbSManivannan Sadhasivam  * @probe: CB function for client driver probe function
460e755cadbSManivannan Sadhasivam  * @remove: CB function for client driver remove function
461e755cadbSManivannan Sadhasivam  * @ul_xfer_cb: CB function for UL data transfer
462e755cadbSManivannan Sadhasivam  * @dl_xfer_cb: CB function for DL data transfer
463e755cadbSManivannan Sadhasivam  * @status_cb: CB functions for asynchronous status
464e755cadbSManivannan Sadhasivam  * @driver: Device driver model driver
465e755cadbSManivannan Sadhasivam  */
466e755cadbSManivannan Sadhasivam struct mhi_driver {
467e755cadbSManivannan Sadhasivam 	const struct mhi_device_id *id_table;
468e755cadbSManivannan Sadhasivam 	int (*probe)(struct mhi_device *mhi_dev,
469e755cadbSManivannan Sadhasivam 		     const struct mhi_device_id *id);
470e755cadbSManivannan Sadhasivam 	void (*remove)(struct mhi_device *mhi_dev);
471e755cadbSManivannan Sadhasivam 	void (*ul_xfer_cb)(struct mhi_device *mhi_dev,
472e755cadbSManivannan Sadhasivam 			   struct mhi_result *result);
473e755cadbSManivannan Sadhasivam 	void (*dl_xfer_cb)(struct mhi_device *mhi_dev,
474e755cadbSManivannan Sadhasivam 			   struct mhi_result *result);
475e755cadbSManivannan Sadhasivam 	void (*status_cb)(struct mhi_device *mhi_dev, enum mhi_callback mhi_cb);
476e755cadbSManivannan Sadhasivam 	struct device_driver driver;
477e755cadbSManivannan Sadhasivam };
478e755cadbSManivannan Sadhasivam 
479e755cadbSManivannan Sadhasivam #define to_mhi_driver(drv) container_of(drv, struct mhi_driver, driver)
4800cbf2608SManivannan Sadhasivam #define to_mhi_device(dev) container_of(dev, struct mhi_device, dev)
4810cbf2608SManivannan Sadhasivam 
4820cbf2608SManivannan Sadhasivam /**
4830cbf2608SManivannan Sadhasivam  * mhi_register_controller - Register MHI controller
4840cbf2608SManivannan Sadhasivam  * @mhi_cntrl: MHI controller to register
4850cbf2608SManivannan Sadhasivam  * @config: Configuration to use for the controller
4860cbf2608SManivannan Sadhasivam  */
4870cbf2608SManivannan Sadhasivam int mhi_register_controller(struct mhi_controller *mhi_cntrl,
4880cbf2608SManivannan Sadhasivam 			    struct mhi_controller_config *config);
4890cbf2608SManivannan Sadhasivam 
4900cbf2608SManivannan Sadhasivam /**
4910cbf2608SManivannan Sadhasivam  * mhi_unregister_controller - Unregister MHI controller
4920cbf2608SManivannan Sadhasivam  * @mhi_cntrl: MHI controller to unregister
4930cbf2608SManivannan Sadhasivam  */
4940cbf2608SManivannan Sadhasivam void mhi_unregister_controller(struct mhi_controller *mhi_cntrl);
4950cbf2608SManivannan Sadhasivam 
496e755cadbSManivannan Sadhasivam /**
497e755cadbSManivannan Sadhasivam  * mhi_driver_register - Register driver with MHI framework
498e755cadbSManivannan Sadhasivam  * @mhi_drv: Driver associated with the device
499e755cadbSManivannan Sadhasivam  */
500e755cadbSManivannan Sadhasivam int mhi_driver_register(struct mhi_driver *mhi_drv);
501e755cadbSManivannan Sadhasivam 
502e755cadbSManivannan Sadhasivam /**
503e755cadbSManivannan Sadhasivam  * mhi_driver_unregister - Unregister a driver for mhi_devices
504e755cadbSManivannan Sadhasivam  * @mhi_drv: Driver associated with the device
505e755cadbSManivannan Sadhasivam  */
506e755cadbSManivannan Sadhasivam void mhi_driver_unregister(struct mhi_driver *mhi_drv);
507e755cadbSManivannan Sadhasivam 
508a6e2e352SManivannan Sadhasivam /**
509a6e2e352SManivannan Sadhasivam  * mhi_set_mhi_state - Set MHI device state
510a6e2e352SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
511a6e2e352SManivannan Sadhasivam  * @state: State to set
512a6e2e352SManivannan Sadhasivam  */
513a6e2e352SManivannan Sadhasivam void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl,
514a6e2e352SManivannan Sadhasivam 		       enum mhi_state state);
515a6e2e352SManivannan Sadhasivam 
5163000f85bSManivannan Sadhasivam /**
5173000f85bSManivannan Sadhasivam  * mhi_prepare_for_power_up - Do pre-initialization before power up.
5183000f85bSManivannan Sadhasivam  *                            This is optional, call this before power up if
5193000f85bSManivannan Sadhasivam  *                            the controller does not want bus framework to
5203000f85bSManivannan Sadhasivam  *                            automatically free any allocated memory during
5213000f85bSManivannan Sadhasivam  *                            shutdown process.
5223000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
5233000f85bSManivannan Sadhasivam  */
5243000f85bSManivannan Sadhasivam int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl);
5253000f85bSManivannan Sadhasivam 
5263000f85bSManivannan Sadhasivam /**
5273000f85bSManivannan Sadhasivam  * mhi_async_power_up - Start MHI power up sequence
5283000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
5293000f85bSManivannan Sadhasivam  */
5303000f85bSManivannan Sadhasivam int mhi_async_power_up(struct mhi_controller *mhi_cntrl);
5313000f85bSManivannan Sadhasivam 
5323000f85bSManivannan Sadhasivam /**
5333000f85bSManivannan Sadhasivam  * mhi_sync_power_up - Start MHI power up sequence and wait till the device
5343000f85bSManivannan Sadhasivam  *                     device enters valid EE state
5353000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
5363000f85bSManivannan Sadhasivam  */
5373000f85bSManivannan Sadhasivam int mhi_sync_power_up(struct mhi_controller *mhi_cntrl);
5383000f85bSManivannan Sadhasivam 
5393000f85bSManivannan Sadhasivam /**
5403000f85bSManivannan Sadhasivam  * mhi_power_down - Start MHI power down sequence
5413000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
5423000f85bSManivannan Sadhasivam  * @graceful: Link is still accessible, so do a graceful shutdown process
5433000f85bSManivannan Sadhasivam  */
5443000f85bSManivannan Sadhasivam void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful);
5453000f85bSManivannan Sadhasivam 
5463000f85bSManivannan Sadhasivam /**
5473000f85bSManivannan Sadhasivam  * mhi_unprepare_after_power_down - Free any allocated memory after power down
5483000f85bSManivannan Sadhasivam  * @mhi_cntrl: MHI controller
5493000f85bSManivannan Sadhasivam  */
5503000f85bSManivannan Sadhasivam void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl);
5513000f85bSManivannan Sadhasivam 
552*6fdfdd27SManivannan Sadhasivam /**
553*6fdfdd27SManivannan Sadhasivam  * mhi_download_rddm_img - Download ramdump image from device for
554*6fdfdd27SManivannan Sadhasivam  *                         debugging purpose.
555*6fdfdd27SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
556*6fdfdd27SManivannan Sadhasivam  * @in_panic: Download rddm image during kernel panic
557*6fdfdd27SManivannan Sadhasivam  */
558*6fdfdd27SManivannan Sadhasivam int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic);
559*6fdfdd27SManivannan Sadhasivam 
560*6fdfdd27SManivannan Sadhasivam /**
561*6fdfdd27SManivannan Sadhasivam  * mhi_force_rddm_mode - Force device into rddm mode
562*6fdfdd27SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
563*6fdfdd27SManivannan Sadhasivam  */
564*6fdfdd27SManivannan Sadhasivam int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl);
565*6fdfdd27SManivannan Sadhasivam 
566*6fdfdd27SManivannan Sadhasivam /**
567*6fdfdd27SManivannan Sadhasivam  * mhi_get_mhi_state - Get MHI state of the device
568*6fdfdd27SManivannan Sadhasivam  * @mhi_cntrl: MHI controller
569*6fdfdd27SManivannan Sadhasivam  */
570*6fdfdd27SManivannan Sadhasivam enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl);
571*6fdfdd27SManivannan Sadhasivam 
5720cbf2608SManivannan Sadhasivam #endif /* _MHI_H_ */
573